15 results about "Design Error" patented technology

Disclosed are a method for calculating a design margin of a power device and a system for calculating a design margin of a power device. The method for calculating a design margin of a power device according to the present invention comprises the steps of: preparing a database storing design values and test values of the power device; performing statistical analysis on the basis of the stored design values and test values to calculate statistical moments considering uncertainties including design errors, manufacturing deviations, and test conditions; and calculating a design margin that minimizes a difference between a customer specification and a design value and minimizes a sum of failure cost and product production cost, on the basis of the calculated statistical moments.

The invention is in the field of computer technology. The invention describes an architecture of a safety automation system and a method for safely autonomously operating a technical device. The architecture solves the problem that every possible Byzantine error, whether caused by an accidental malfunction of hardware, a design error in software or an intrusion, must be identified and contained, so that no safety-relevant event occurs. The architecture consists of four largely independent subsystems, which are arranged hierarchically and each form an encapsulated fault containment unit. At the top of the hierarchy is the safety subsystem, i.e. the fault-tolerant decision subsystem, which executes simple software on fault-tolerant hardware. The other three subsystems are unsafe because they contain complex software. It is empirically difficult to find all design errors in a complex software system and to prevent intrusions. Due to redundancy and diversity, every error of the unsafe subsystems is masked so that no safety-critical malfunction occurs.

The invention provides a variable-diameter shield steel pipe piece joint design method based on random error accumulation, and precise control is realized through a double-path design method: a path 1 is based on a determined pipe piece joint form, the splicing precision of a single pipe piece is input, the bolt position and error redundancy of a top sealing block are optimized in a targeted manner, and a path 2 is obtained; error accumulation is controlled from the key component design level; in the path 2, the design of a capping block and a corresponding accumulative error tolerance are firstly determined, and then a standard segment joint connection mode is optimized so as to refine design and control splicing random errors. Meanwhile, a Monte Carlo method is introduced, and balance of construction efficiency and structural quality is realized by randomly generating segment assembly errors, simulating an accumulation process, comparing and verifying with design error redundancy, judging a ring forming probability and iteratively optimizing path design parameters to improve the segment ring forming probability.

The system according to this embodiment aims to automate the circuit design process and reduce design errors. [Solution] The system according to the embodiment comprises a requirements understanding unit, a design generation unit, an optimization unit, an error prediction unit, and a document generation unit. The requirements understanding unit understands the user's requirements. The design generation unit automatically generates a circuit design based on the requirements understood by the requirements understanding unit. The optimization unit optimizes the circuit design generated by the design generation unit. The error prediction unit predicts errors based on the circuit design optimized by the optimization unit. The document generation unit generates a technical document based on the errors predicted by the error prediction unit.

The invention discloses a ship building project management method. The method is divided into the following eight stages according to the project implementation sequence: pre-research, contract effectiveness, overall structure design, detailed structure design, production construction design, start-up implementation, shaped ship delivery, protection delay and scrapping. A complete system covering a plurality of standard deliverables is formed, and automatic connection of design, process and production data is realized through a standardized data link in the whole process. By adopting the technical scheme, a set of new refined design process management system is established; a clear and standard design development process model is established, invalid work and redundant links in the design execution process are eliminated, and the design process is more coherent and efficient; design developers are guided to carry out research and development design work according to a correct path, manpower resource waste, design errors and deviation in the design process are reduced, the standardization of the design process is improved, and then the design efficiency is improved.

The invention provides a multi-objective optimization design method and system for a liquid helium low-temperature subcooler, and the method comprises the steps: selecting initial design parameters from structure parameters which affect the performance of the low-temperature subcooler according to determined design working conditions and design indexes, and synchronously determining target parameters which need to be optimized from the initial design parameters; determining a corresponding constraint condition according to the parameter range of the initial design parameter, and synchronously creating a corresponding target calculation process according to the target parameter based on the constraint condition; based on a target calculation process, performing multi-target optimization design according to the defined optimization problem and a non-dominated sorting genetic algorithm NSGA-II to output a corresponding Pareto solution set; and selecting a corresponding decision-making method according to the optimization expectation, and synchronously performing decision-making processing on the Pareto solution set according to the decision-making method so as to correspondingly output a target scheme conforming to the design expectation. According to the method, design errors caused by improper selection of physical property parameters can be effectively avoided.

The invention discloses a method for correcting design errors of a CMOS (complementary metal oxide semiconductor) operational amplifier, which comprises the following steps: firstly, according to preset performance indexes, the performance indexes mainly comprise unity gain bandwidth, phase margin and slew rate; the method comprises the following steps: performing initial design on a CMOS operational amplifier by adopting a conventional design process to obtain initial circuit parameters; performing circuit simulation on the initial circuit, and obtaining an actual unit gain frequency, an actual phase margin and an actual slew rate obtained by simulation; calculating an error factor according to the performance index and the simulation result; and correcting the design parameters by using the error factors, and finally recalculating the size of each MOS tube according to the corrected design parameters to complete design error correction. According to the method, performance errors caused by process deviation, model inaccuracy or manual design simplification are identified and corrected in a mode of combining simulation and theoretical calculation, so that the final circuit performance meets or is superior to a preset index.

A non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to acquire a plurality of graphs that model results of a plurality of bug hunting searches for a register transfer level design, wherein the plurality of bug hunting searches determines a design error in the register transfer level design, construct a composite graph using the plurality of graphs, wherein the composite graph models a plurality of causal relationships between a plurality of detected bugs and a plurality of helper properties covered by the plurality of bug hunting searches, and execute an additional bug hunting search whose parameters are configured based on the composite graph.

A non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to acquire a plurality of graphs that model results of a plurality of bug hunting searches for a register transfer level design, wherein the plurality of bug hunting searches determines a design error in the register transfer level design, construct a composite graph using the plurality of graphs, wherein the composite graph models a plurality of causal relationships between a plurality of detected bugs and a plurality of helper properties covered by the plurality of bug hunting searches, and execute an additional bug hunting search whose parameters are configured based on the composite graph.

An object of a system according to an embodiment is to detect and notify a design error through analysis of an architectural drawing.SOLUTION: A system includes an architectural drawing analysis part, a design error detection part, and a notification part. The building drawing analysis unit analyzes a building drawing. The design error detection part detects a design error from the result analyzed by the construction drawing analysis part. The notification unit notifies the designer of the design error detected by the design error detection unit.SELECTED DRAWING: Figure 1

This application provides a method for designing ship piping system models. A control system diagram template is selected based on the system type. Each component in the control system diagram template is matched with a corresponding standard model block, and each standard model block is matched with a configuration table and parameter constraints. The parameter constraints of the ship piping system are obtained, and the parameter constraints of the standard model blocks are adjusted according to these constraints. The configuration table is reset, and each standard model block is adjusted accordingly. The geometric information of the adjusted model blocks is then obtained. A three-dimensional model of the ship piping system is obtained based on the geometric information of multiple model blocks. This application can be used in the design of piping systems for most civil ships, reducing the number of times designers need to modify layout schemes, improving design efficiency and quality, and avoiding design errors caused by lack of experience. The combination of parameter constraints and templates completes the standardized design of three-dimensional models for ship management, facilitating widespread use.

This invention discloses a visual modeling method based on the PML language in ship design software. Through a natural language interface, it eliminates the need for users to deeply understand the complex operations of professional ship modeling software, significantly reducing technical training costs and lowering the skill threshold for personnel. Using the system developed by this invention, designers can clearly view the complete process logic of model generation and modification, enhancing their understanding of the model construction mechanism, reducing errors caused by unfamiliarity with operations, and effectively improving the accuracy and reliability of the design. By combining parametric models with natural language processing, it achieves automated model generation and intelligent modification, significantly reducing manual operation and improving overall design efficiency. It also shortens model design and modification time, reduces reliance on highly skilled operators, lowers rework costs for design errors, and achieves cost savings and efficiency improvements from multiple dimensions, making it suitable for modern engineering design environments requiring frequent iteration and collaboration.

The invention discloses a material BOM information and system library consistency proofreading method, and belongs to the technical field of electronic design, and the method comprises the steps: exporting a BOM file containing to-be-proofreading attributes from schematic diagram design software, and opening the BOM file in an editable table format; the to-be-corrected attributes at least comprise material codes and material characteristic attributes; comparing material information in the BOM file with material information in a system library, matching characteristic attributes of corresponding materials in the BOM file and the system library through a table function according to the material codes, and identifying materials with inconsistent characteristic attributes; and verifying and modifying the inconsistent material characteristic attributes based on the identification result. According to the invention, problems caused by design errors and artificial modification are reduced. A comparison reference is established by taking a material code as a unique identifier, so that matching deviation caused by attribute name difference is avoided, the BOM is ensured to be accurately checked with characteristic attributes of a system library, and hidden dangers caused by model selection errors or parameter input deviation during design are intercepted from the source.

This invention discloses a method for correcting design errors in a CMOS operational amplifier. First, based on predetermined performance indicators, primarily including unity-gain bandwidth, phase margin, and slew rate, an initial design of the CMOS operational amplifier is performed using a conventional design process to obtain initial circuit parameters. The initial circuit is then simulated to obtain the simulated actual unity-gain frequency, actual phase margin, and actual slew rate. Based on the performance indicators and simulation results, an error factor is calculated. The design parameters are then corrected using the error factor. Finally, based on the corrected design parameters, the dimensions of each MOSFET are recalculated to complete the design error correction. This method, combining simulation and theoretical calculation, identifies and corrects performance errors caused by process deviations, inaccurate models, or simplifications in manual design, thereby ensuring that the final circuit performance meets or exceeds the predetermined indicators.

A method, apparatus and product comprising: obtaining alternative quantum circuits implementing a quantum program, each having a respective design error; identifying, for each quantum circuit, respective quantum resources that are used by the quantum circuit and are associated with respective hardware errors of a quantum computer; determining a total hardware error bound for the quantum circuit; determining a total error bound for the quantum circuit; applying a search algorithm over a plurality of total error bounds of the plurality of alternative quantum circuits, to identify an optimal total error bound that is associated with an optimal quantum circuit; and providing the optimal quantum circuit for execution on the quantum computer.