29 results about "Design Error" patented technology

The invention provides a hardware description language code generation system based on TypeScript, comprising a configuration conversion unit, a type verification unit, a parameter calculation unit, an intermediate representation construction unit and a code generation unit, through a type system of TypeScript, type inconformity can be effectively captured in a coding stage, illegal configuration with parameter type inconformity is effectively intercepted, and the code generation efficiency is improved. Therefore, the design error risk and the later debugging cost are reduced; meanwhile, based on the object-oriented characteristic of the TypeScript, the target hardware description language code with the structured hierarchy can be generated, so that the readability of the target hardware description language code is high, and then the maintainability and development efficiency of hardware design are improved.

The present invention provides a method for obtaining a control valve spool curved surface and a control valve throttling component, belonging to the field of regulating equipment. The method includes the following steps: according to the geometric structure of the control valve, obtain a model of the spool curved surface of the control valve with respect to the theoretical flow coefficient at a preset opening; according to the spatial relationship between the spool and the valve seat at the preset opening and the model, obtain the design coordinate data of the spool curved surface at the preset opening; adjust the preset opening, obtain the design coordinate data of the spool curved surface at each preset opening, and obtain the spool curved surface of the control valve according to the design coordinate data of the spool curved surface at each preset opening. The control valve throttling component includes a spool, and the throttling curved surface of the spool is obtained by using the method for obtaining the spool curved surface of the control valve described above. The present invention obtains the spool curved surface model by means of theoretical design and simulation correction. Compared with the traditional design method, it can improve the design efficiency, reduce the design error, and enable the control valve to obtain higher adjustment accuracy.

Disclosed are a method for calculating a design margin of a power device and a system for calculating a design margin of a power device. The method for calculating a design margin of a power device according to the present invention comprises the steps of: preparing a database storing design values and test values of the power device; performing statistical analysis on the basis of the stored design values and test values to calculate statistical moments considering uncertainties including design errors, manufacturing deviations, and test conditions; and calculating a design margin that minimizes a difference between a customer specification and a design value and minimizes a sum of failure cost and product production cost, on the basis of the calculated statistical moments.

A method, apparatus and product comprising: obtaining alternative quantum circuits implementing a quantum program, each having a respective design error; identifying, for each quantum circuit, respective quantum resources that are used by the quantum circuit and are associated with respective hardware errors of a quantum computer; determining a total hardware error bound for the quantum circuit; determining a total error bound for the quantum circuit; applying a search algorithm over a plurality of total error bounds of the plurality of alternative quantum circuits, to identify an optimal total error bound that is associated with an optimal quantum circuit; and providing the optimal quantum circuit for execution on the quantum computer.

To provide a technique for easily confirming the positional relationship of a plurality of structures constituting a device including errors.SOLUTION: An analysis method confirms a positional relationship between a first structure composed of a plurality of members and a second structure and includes: a step (S2) of calculating a contact possibility range by integrating design values and design errors of each member of the first structure, and a step (S4) of analyzing the positional relationship between the first structure and the second structure based on the contact possibility range. When a reference body of the first structure is composed of a first member to be fixed, a second member, and an intermediate member (optional) interposed between the first member and the second member, in the step (S2) of calculating the contact possibility range, the contact possibility range of the second member is calculated by integrating all design errors of the first member, the intermediate member, and the second member. Thus, the positional relationship of the plurality of structures constituting a device can be easily confirmed, including errors.SELECTED DRAWING: Figure 3

The invention discloses a layout quality verification method for an integrated circuit standard cell library, and aims to solve the problems that design errors are exposed during later integration and the design efficiency is reduced due to the fact that only a single standard cell is checked and an actual application scene cannot be simulated in a traditional method. It is ensured that errors are not reported when unit data are read in the layout and wiring stage; through modular random splicing, a layout and wiring environment can be simulated to the greatest extent, and a complete module is generated. A physical unit is inserted, invalid error reporting is avoided, DRC checking of the module is carried out, and layout and wiring are ensured; the units are spliced in a pairwise surrounding manner, so that the ergodicity of the spliced units and the test coverage rate of the spliced surfaces are ensured; through winding property inspection, it is ensured that accidental DRC is not generated due to connection punching when the layout wiring tool is connected to a standard unit.

The invention is in the field of computer technology. The invention describes an architecture of a safety automation system and a method for safely autonomously operating a technical device. The architecture solves the problem that every possible Byzantine error, whether caused by an accidental malfunction of hardware, a design error in software or an intrusion, must be identified and contained, so that no safety-relevant event occurs. The architecture consists of four largely independent subsystems, which are arranged hierarchically and each form an encapsulated fault containment unit. At the top of the hierarchy is the safety subsystem, i.e. the fault-tolerant decision subsystem, which executes simple software on fault-tolerant hardware. The other three subsystems are unsafe because they contain complex software. It is empirically difficult to find all design errors in a complex software system and to prevent intrusions. Due to redundancy and diversity, every error of the unsafe subsystems is masked so that no safety-critical malfunction occurs.

The invention provides a variable-diameter shield steel pipe piece joint design method based on random error accumulation, and precise control is realized through a double-path design method: a path 1 is based on a determined pipe piece joint form, the splicing precision of a single pipe piece is input, the bolt position and error redundancy of a top sealing block are optimized in a targeted manner, and a path 2 is obtained; error accumulation is controlled from the key component design level; in the path 2, the design of a capping block and a corresponding accumulative error tolerance are firstly determined, and then a standard segment joint connection mode is optimized so as to refine design and control splicing random errors. Meanwhile, a Monte Carlo method is introduced, and balance of construction efficiency and structural quality is realized by randomly generating segment assembly errors, simulating an accumulation process, comparing and verifying with design error redundancy, judging a ring forming probability and iteratively optimizing path design parameters to improve the segment ring forming probability.

The invention discloses an AI-based game design scheme generation method and a terminal, and the method comprises the steps: collecting excellent historical game design schemes with design scores higher than a first score threshold value and design templates thereof, and learning the generation process of the excellent design schemes, so as to obtain an AI model used for the generation of excellent schemes; the conditions of design errors are reduced; after a game design demand is received, functional modules are divided, and design templates are matched according to the divided functional modules to generate an initial scheme, so that the initial scheme can cover functions required by the game design demand, and the situation of design omission is reduced; afterwards, the initial scheme and the game design requirement are substituted into an AI model, and a final game design scheme is generated. In this way, the game design scheme can be automatically generated according to the game design requirement, and the situation of design omission or design errors is reduced.

The invention relates to the technical field of PCBs, in particular to a misoperation prevention and control method and system for CAM manufacturing in PCB production. According to the method, the lamination structure information of the CAM design data of the target PCB is automatically obtained, and the interlayer signal delay is calculated based on the lamination structure information, so that human judgment errors can be effectively avoided, the drilling overlapping rate is ensured to be within an acceptable range by automatically adjusting the CAM design data, and the drilling efficiency is improved by accurately calculating and adjusting the drilling parameters. It is ensured that the drill hole overlapping rate meets the preset requirement, design errors caused by human negligence, improper use of software tools or flow management vulnerabilities can be effectively avoided, verification is conducted through an automatic simulation system, subjective factors in manual judgment can be eliminated, it is ensured that design data meets the preset process standard, and the design efficiency is improved. Communication obstacles between design and production are reduced, misunderstanding and errors between the design stage and the production stage can be reduced through efficient cooperation, and the working efficiency is improved.

The invention discloses a CATIA (computer-graphics aided three-dimensional interactive application)-based automatic generation and design method for an aircraft integrated control board. The design method is realized based on CATIA software, and specifically comprises the following steps: S1, constructing a general basic model of the CPA: constructing the general basic model of the CPA according to modeling parameters; s2, constructing a super copy of the structural features for switch installation; s3, modifying the key parameters according to the CPA needing to be designed; s4, based on the modified key parameters, updating the CPA general basic model to obtain a CPA model meeting design requirements; and S5, the super copy is used for conducting structural detail modification on the CPA model meeting the design requirement, and then all design of the CPA model can be completed. The method has the beneficial effects that repeated design work is reduced, the design efficiency is improved, and the design error rate is reduced.

The system according to this embodiment aims to automate the circuit design process and reduce design errors. [Solution] The system according to the embodiment comprises a requirements understanding unit, a design generation unit, an optimization unit, an error prediction unit, and a document generation unit. The requirements understanding unit understands the user's requirements. The design generation unit automatically generates a circuit design based on the requirements understood by the requirements understanding unit. The optimization unit optimizes the circuit design generated by the design generation unit. The error prediction unit predicts errors based on the circuit design optimized by the optimization unit. The document generation unit generates a technical document based on the errors predicted by the error prediction unit.

The invention discloses a ship building project management method. The method is divided into the following eight stages according to the project implementation sequence: pre-research, contract effectiveness, overall structure design, detailed structure design, production construction design, start-up implementation, shaped ship delivery, protection delay and scrapping. A complete system covering a plurality of standard deliverables is formed, and automatic connection of design, process and production data is realized through a standardized data link in the whole process. By adopting the technical scheme, a set of new refined design process management system is established; a clear and standard design development process model is established, invalid work and redundant links in the design execution process are eliminated, and the design process is more coherent and efficient; design developers are guided to carry out research and development design work according to a correct path, manpower resource waste, design errors and deviation in the design process are reduced, the standardization of the design process is improved, and then the design efficiency is improved.

The invention provides a multi-objective optimization design method and system for a liquid helium low-temperature subcooler, and the method comprises the steps: selecting initial design parameters from structure parameters which affect the performance of the low-temperature subcooler according to determined design working conditions and design indexes, and synchronously determining target parameters which need to be optimized from the initial design parameters; determining a corresponding constraint condition according to the parameter range of the initial design parameter, and synchronously creating a corresponding target calculation process according to the target parameter based on the constraint condition; based on a target calculation process, performing multi-target optimization design according to the defined optimization problem and a non-dominated sorting genetic algorithm NSGA-II to output a corresponding Pareto solution set; and selecting a corresponding decision-making method according to the optimization expectation, and synchronously performing decision-making processing on the Pareto solution set according to the decision-making method so as to correspondingly output a target scheme conforming to the design expectation. According to the method, design errors caused by improper selection of physical property parameters can be effectively avoided.

The present invention relates to the technical field of mold manufacturing management. Specifically, it relates to a mold manufacturing management system for reducing the design cycle. It includes a historical mold design data storage module, a route planning module, and a mold design error analysis module. The present invention obtains the processing items of the entire design cycle through the historical mold design data storage module. During the design process, the route planning module combines the processing items to plan the design route and error verification route of the current mold, and cooperates with the mold design error analysis module to determine the current error verification route, and updates the error verification route according to the determination result, realizing the automatic update of the error verification route, improving the efficiency of mold secondary design. At the same time, the data after the update of the error verification route is used as a reference for the design of later molds of the same type, improving the design effect of molds of the same type.

The invention discloses a method for correcting design errors of a CMOS (complementary metal oxide semiconductor) operational amplifier, which comprises the following steps: firstly, according to preset performance indexes, the performance indexes mainly comprise unity gain bandwidth, phase margin and slew rate; the method comprises the following steps: performing initial design on a CMOS operational amplifier by adopting a conventional design process to obtain initial circuit parameters; performing circuit simulation on the initial circuit, and obtaining an actual unit gain frequency, an actual phase margin and an actual slew rate obtained by simulation; calculating an error factor according to the performance index and the simulation result; and correcting the design parameters by using the error factors, and finally recalculating the size of each MOS tube according to the corrected design parameters to complete design error correction. According to the method, performance errors caused by process deviation, model inaccuracy or manual design simplification are identified and corrected in a mode of combining simulation and theoretical calculation, so that the final circuit performance meets or is superior to a preset index.

A non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to acquire a plurality of graphs that model results of a plurality of bug hunting searches for a register transfer level design, wherein the plurality of bug hunting searches determines a design error in the register transfer level design, construct a composite graph using the plurality of graphs, wherein the composite graph models a plurality of causal relationships between a plurality of detected bugs and a plurality of helper properties covered by the plurality of bug hunting searches, and execute an additional bug hunting search whose parameters are configured based on the composite graph.

The present invention discloses a multi-level system interface design and management method based on the SysML language, wherein the interface design method comprises: step 1, in the conceptual design stage, using the SysML language to design the use scenario of the system operation, and defining the external interface of the system based on the interactive behavior between the system and the external environment in the use scenario; step 2, in the logical design stage, using the SysML language to define the components in the system, the logical interface between the components, and the interface transmission from the system external interface to the components; step 3, in the physical design stage, defining the physical interface between the components in the device layer to express the physical implementation of the logical interface between the devices. The technical solution of the present invention solves the problem of the document-based interface definition method in traditional system engineering, which may lead to design errors introduced by inconsistent interface definitions because the consistency of the interface can only be guaranteed by manpower, and the interface management method, which requires the establishment of corresponding N 2 This is not conducive to the unified management of interfaces and is prone to introducing errors during the transmission process.

The application discloses a kind of secondary circuit design information's checking method, device, equipment and storage medium.Therein, secondary circuit design information's checking method includes: obtaining primary circuit design information, secondary circuit design information, secondary circuit equipment list and checking standard information;Extract equipment information and circuit information in secondary circuit design information;Determine whether equipment information is consistent with standard equipment information, determine whether circuit information is consistent with standard circuit information;If not, output inconsistent equipment information and inconsistent circuit information.The technical scheme of the application realizes the checking of secondary circuit design drawing, helps drawing designer to check whether the design drawing exists design error or name is not changed, improves the quality of design drawing;Auxiliary drawing reviewer carries out drawing review work, improves drawing review efficiency.

The embodiment of the invention discloses a file verification method and device, equipment, a medium and a program product. Comprising the steps of obtaining a to-be-verified file and a verification rule set corresponding to the to-be-verified file; when a process verification trigger instruction is received, analyzing a to-be-verified file, and determining a to-be-verified instance set; and verifying each to-be-verified instance in the to-be-verified instance set through the verification rule set, and generating a file verification report according to the verification result of each to-be-verified instance. According to the method, the to-be-verified file can be verified in a design stage without configuring an environment and an engine, rework and modification caused by the fact that design errors can only be found in a test stage are reduced, the design time and the labor cost are saved, meanwhile, the adaptability of a rule for verification and a business process during verification of the to-be-verified file is improved, and the verification efficiency of the to-be-verified file is improved. Therefore, the verification accuracy and coverage are improved, and the verification efficiency is improved.

A non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to acquire a plurality of graphs that model results of a plurality of bug hunting searches for a register transfer level design, wherein the plurality of bug hunting searches determines a design error in the register transfer level design, construct a composite graph using the plurality of graphs, wherein the composite graph models a plurality of causal relationships between a plurality of detected bugs and a plurality of helper properties covered by the plurality of bug hunting searches, and execute an additional bug hunting search whose parameters are configured based on the composite graph.

An object of a system according to an embodiment is to detect and notify a design error through analysis of an architectural drawing.SOLUTION: A system includes an architectural drawing analysis part, a design error detection part, and a notification part. The building drawing analysis unit analyzes a building drawing. The design error detection part detects a design error from the result analyzed by the construction drawing analysis part. The notification unit notifies the designer of the design error detected by the design error detection unit.SELECTED DRAWING: Figure 1

This application provides a method for designing ship piping system models. A control system diagram template is selected based on the system type. Each component in the control system diagram template is matched with a corresponding standard model block, and each standard model block is matched with a configuration table and parameter constraints. The parameter constraints of the ship piping system are obtained, and the parameter constraints of the standard model blocks are adjusted according to these constraints. The configuration table is reset, and each standard model block is adjusted accordingly. The geometric information of the adjusted model blocks is then obtained. A three-dimensional model of the ship piping system is obtained based on the geometric information of multiple model blocks. This application can be used in the design of piping systems for most civil ships, reducing the number of times designers need to modify layout schemes, improving design efficiency and quality, and avoiding design errors caused by lack of experience. The combination of parameter constraints and templates completes the standardized design of three-dimensional models for ship management, facilitating widespread use.

This invention discloses a visual modeling method based on the PML language in ship design software. Through a natural language interface, it eliminates the need for users to deeply understand the complex operations of professional ship modeling software, significantly reducing technical training costs and lowering the skill threshold for personnel. Using the system developed by this invention, designers can clearly view the complete process logic of model generation and modification, enhancing their understanding of the model construction mechanism, reducing errors caused by unfamiliarity with operations, and effectively improving the accuracy and reliability of the design. By combining parametric models with natural language processing, it achieves automated model generation and intelligent modification, significantly reducing manual operation and improving overall design efficiency. It also shortens model design and modification time, reduces reliance on highly skilled operators, lowers rework costs for design errors, and achieves cost savings and efficiency improvements from multiple dimensions, making it suitable for modern engineering design environments requiring frequent iteration and collaboration.

The invention discloses a material BOM information and system library consistency proofreading method, and belongs to the technical field of electronic design, and the method comprises the steps: exporting a BOM file containing to-be-proofreading attributes from schematic diagram design software, and opening the BOM file in an editable table format; the to-be-corrected attributes at least comprise material codes and material characteristic attributes; comparing material information in the BOM file with material information in a system library, matching characteristic attributes of corresponding materials in the BOM file and the system library through a table function according to the material codes, and identifying materials with inconsistent characteristic attributes; and verifying and modifying the inconsistent material characteristic attributes based on the identification result. According to the invention, problems caused by design errors and artificial modification are reduced. A comparison reference is established by taking a material code as a unique identifier, so that matching deviation caused by attribute name difference is avoided, the BOM is ensured to be accurately checked with characteristic attributes of a system library, and hidden dangers caused by model selection errors or parameter input deviation during design are intercepted from the source.

The invention discloses a crane trolley steel structure parameterization design method. The crane trolley steel structure parameterization design method comprises the following steps that S1, design parameters are input; s2, generating a parameterized model; s3, carrying out load spectrum analysis and structure strengthening; s4, performing multi-objective optimization; s5, carrying out standard load verification; s6, outputting a design result; according to the method, a parameterized template of components such as a roller box is established, and a three-dimensional model is automatically generated through various core design parameters; structure strengthening is automatically triggered based on a working condition load spectrum, and plates are thickened or rib plates are added in a stress concentration area; the weight, the rigidity and the manufacturing cost are synchronously optimized through multi-objective collaborative optimization; a checking engine is standardized in real time, and key indexes such as wheel pressure distribution and local buckling are automatically checked; the method is suitable for rapid customization development of various bridge type and portal crane trolley structures, the design period is remarkably shortened, the design error rate is reduced, and the product competitiveness is improved.

This invention discloses a method for correcting design errors in a CMOS operational amplifier. First, based on predetermined performance indicators, primarily including unity-gain bandwidth, phase margin, and slew rate, an initial design of the CMOS operational amplifier is performed using a conventional design process to obtain initial circuit parameters. The initial circuit is then simulated to obtain the simulated actual unity-gain frequency, actual phase margin, and actual slew rate. Based on the performance indicators and simulation results, an error factor is calculated. The design parameters are then corrected using the error factor. Finally, based on the corrected design parameters, the dimensions of each MOSFET are recalculated to complete the design error correction. This method, combining simulation and theoretical calculation, identifies and corrects performance errors caused by process deviations, inaccurate models, or simplifications in manual design, thereby ensuring that the final circuit performance meets or exceeds the predetermined indicators.

The application discloses a metal part performance optimization method and system based on stress parameters and a storage medium, relates to the technical field of metal structure optimization, and comprises the following steps: stress detection is performed on a metal part to obtain test stress points of the metal part; all the test stress points are tested respectively to obtain pressure bearing values, target pressure values and other partial pressure values of the test stress points; the pressure bearing values, the target pressure values and the other partial pressure values are analyzed to obtain pressure bearing strengths of all the test stress points; and based on the pressure bearing strengths of all the test stress points, an optimization point is obtained through analysis and optimization. The application is used to solve the problem that, in the prior art, when a metal part is optimized, the structure design of the metal part is not verified based on stress parameters, which may lead to the problem that, due to design errors, the structure strength of the metal part is insufficient in the use process.

A method, apparatus and product comprising: obtaining alternative quantum circuits implementing a quantum program, each having a respective design error; identifying, for each quantum circuit, respective quantum resources that are used by the quantum circuit and are associated with respective hardware errors of a quantum computer; determining a total hardware error bound for the quantum circuit; determining a total error bound for the quantum circuit; applying a search algorithm over a plurality of total error bounds of the plurality of alternative quantum circuits, to identify an optimal total error bound that is associated with an optimal quantum circuit; and providing the optimal quantum circuit for execution on the quantum computer.