Triplication redundancy D trigger capable of realizing self error detection and single event upset prevention

An anti-single event, three-mode redundancy technology, applied in the direction of pulse generation, electrical components, electric pulse generation, etc., can solve the problem of low anti-single event reversal ability

Active Publication Date: 2016-07-20
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The technical problem to be solved by the present invention is to provide a three-mode redundant D flip-flop with self-correcting and error detection for the problem that the anti-single event ...

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  • Triplication redundancy D trigger capable of realizing self error detection and single event upset prevention
  • Triplication redundancy D trigger capable of realizing self error detection and single event upset prevention
  • Triplication redundancy D trigger capable of realizing self error detection and single event upset prevention

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Embodiment Construction

[0057] figure 1 It is a schematic diagram of the logic structure of the anti-single event reversal triple-mode redundant D flip-flop with self-correction and error detection in the present invention. The present invention consists of the first clock circuit (such as figure 2 shown), the first master latch (as image 3 shown), the first slave latch (as Figure 4 shown); the second clock circuit (such as Figure 5 shown), the second master latch (as Figure 6 shown), the second slave latch (as Figure 7 shown); the third clock circuit (such as Figure 8 shown), the third master latch (as Figure 9 shown), the third slave latch (as Figure 10 shown); selector circuit (such as Figure 11 shown), the first inverter circuit (such as Figure 12 shown), the second inverter circuit (such as Figure 13 shown); and error detection control circuit (such as Figure 14 shown) composition.

[0058] The anti-single-event reversal triple-mode redundant D flip-flop with self-correc...

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Abstract

The invention discloses a triplication redundancy D trigger capable of realizing self error detection and single event upset prevention. The trigger comprises a first clock circuit, a first main latch register, a first secondary latch register, a second clock circuit, a second main latch register, a second secondary latch register, a third clock circuit, a third main latch register, a third secondary latch register, a selector circuit, a first inverter circuit, a second inverter circuit and an error detection control circuit. The trigger is on the basis of a traditional reinforced triplication redundancy D trigger, output of three basic triggers in the triplication redundancy structure is controlled through the designed error detection control circuit, that correct output can be determined by a selector at any time is guaranteed; when output upset occurs in one of the three basic triggers, the one with output upset is instantly recovered through the error detection control circuit, upset accumulation can be avoided, and single event upset caused upset accumulation can be avoided, and single event upset prevention capability is further improved.

Description

technical field [0001] The invention relates to a triple-mode redundant D flip-flop, in particular to a single-event flip-resistant triple-mode redundant D flip-flop with self-correction and error detection. Background technique [0002] In cosmic space, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called a single event upset (Signal Event Upset, SEU). The higher the linear energy transfer (LinearEnergyTransfer, LET) value of the single-particle bombardment integrated circuit, the stronger the electronic pulse generated. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits w...

Claims

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Application Information

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IPC IPC(8): H03K3/3562
CPCH03K3/3562
Inventor 梁斌孙永节向文超陈建军池雅庆
Owner NAT UNIV OF DEFENSE TECH
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