27results about How to "Reduce dynamic power consumption" patented technology

The invention discloses a branch prediction unit power consumption management method and device, and the method comprises the steps: setting a multi-stage branch predictor and a low-power-consumption control logic coupled with the multi-stage branch predictor in a processor core micro-architecture, and enabling the multi-stage branch predictor to comprise three stages of predictors which are sequentially accessed in an assembly line, the hardware resource consumption and the prediction accuracy of each predictor are gradually increased from front to back; monitoring the prediction condition of each predictor in real time through low-power-consumption control logic, and closing all predictors behind the first predictor meeting the prediction requirement within a first preset time according to a front-to-back sequence; branch jump addresses are divided into high-order address fields and low-order address fields by BTBs in the multiple levels of predictors except the first-level predictor to be stored in different storage blocks, and label registers used for taking the high-order addresses as label indexes are arranged. The power consumption unit of each predictor can be finely controlled, the energy consumption is greatly reduced, system-level cooperation is not needed, and the universality is high.

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

This invention belongs to the technical field of integrated circuit manufacturing, and discloses a SAR-assisted pipelined analog-to-digital converter and its control method. The analog-to-digital converter includes a two-stage SAR ADC module, and the first stage capacitor array includes C 1 1 ~C 1 M‑1 C 1 2 ~C 1 M‑1 The reference voltage is V ref C 1 1 The reference voltage is V cm =V ref / 2, an improved monotonic switching scheme using redundant capacitors can perform successive approximation comparisons to obtain an M-bit digital code. After completing the first-stage conversion, a passive residual transfer scheme is used, along with inter-stage bit transfer, to enter the second-stage conversion. This second-stage conversion employs the same improved monotonic switching scheme as the first stage, performing successive approximation comparisons to obtain an N-bit digital code. Finally, through timing alignment, an M+N-bit digital code is obtained. This design saves device area and improves conversion efficiency.

The invention belongs to the technical field of deep space exploration, and particularly relates to a multispectral image displacement depth adaptive mapping method and system based on radiometric calibration, and the method comprises the steps: obtaining original black field data with the input bit depth being N and original flat field data with the input bit depth being N; after bad pixels are shielded according to the original black field data and the original flat field data, row offset and row response are calculated; sequentially determining a global scale according to the row offset and the row response, calculating an integration slope, and generating a lookup table according to the integration slope; and acquiring real-time monitoring input, reading the M-bit output value corresponding to the real-time monitoring input according to the lookup table, and correcting and updating the lookup table according to the M-bit output value. Based on a parameterized calculation process (derivation from row bias and row response to a global scale and an integrated slope), different input bit depth and output bit depth requirements can be met by modifying input parameters, inherent limitation caused by hard coding is avoided, and the configurability of cross-platform tasks is improved.

The invention discloses a multi-bit trigger design method for a standard cell library and a scan chain, and belongs to the technical field of integrated circuits, the multi-bit trigger design method for the standard cell library comprises the following steps: providing a plurality of single-bit triggers, and setting the flipping rate of each single-bit trigger; arranging the single-bit triggers, and placing the single-bit trigger with the lowest flipping rate at the last position; the single-bit triggers are serially connected into a scan chain according to the sequence, the first single-bit trigger is used for accessing input data and a scan chain control signal, and the output end of the last single-bit trigger is used for outputting data. By arranging the triggers with the lowest flipping rate at the output end, the DFT dynamic power consumption can be reduced, and the Power signoff can be optimized.

A method for accelerating finite-field modular arithmetic on RISC-V processors is disclosed. The method includes: 1. Constructing a non-saturated multi-limb representation model of finite-field elements in the processor's 64-bit general-purpose registers; 2. Designing an instruction scheduling strategy that interleaves computation and memory access based on the execution latency characteristics of multiplication instructions in the RISC-V processor; 3. Employing a latency correction mechanism within the general-purpose registers to decouple carry propagation and modular reduction path scheduling; 4. For modular square operations, constructing an instruction-level reduction path within the processor's instruction set environment, and implementing cross-limb carry processing through logical shift instructions and unsigned comparison instructions; 5. Utilizing the redundant bit width of the non-saturated representation, implementing a latency accumulation and mask correction mechanism for modular addition and subtraction operations at the register level. This invention achieves a computational speedup several times greater than existing implementations by optimizing processor register resources and instruction scheduling without altering the original mathematical structure of cryptographic algorithms.

This invention discloses an efficient QR matrix decomposition method based on FPGA for implementing systolic matrices, belonging to the field of software-defined radio signal transmission technology for airborne networks. It is based on the design of a multi-channel digital front-end implemented on an FPGA chip. The method includes: designing a general handshake coordination mechanism, designing a timing flow for systolic matrix multiplication, performing fast QR matrix decomposition single-loop operations by calculating the Householder mirror transformation matrix, designing a top-level loop pipeline for QR matrix decomposition, and finally verifying the hardware scheme of the fast QR decomposition algorithm. This invention converts resource consumption into timing consumption by designing the overall pipeline logic and loop operations, enabling fast processing and accurate decomposition of digital information in a multi-channel digital front-end on an FPGA, effectively saving on-chip resources. In addition, this invention has excellent scalability, supporting 64 to 128-bit high-precision fixed-point number formats, and the data matrix order can reach up to 128.

A shift register (100), a gate drive circuit (10), a display panel (1), and a driving method. The shift register (100) comprises: an input circuit (110), which is connected to a pull-up node (PU) and an input signal terminal (INPUT) respectively; an output circuit (120), which is connected to the pull-up node (PU), a clock signal terminal (CLK), a direct current signal terminal (GCH) and an input terminal (OUTPUT) respectively, wherein the clock signal terminal (CLK) provides a clock signal, the direct current signal terminal (GCH) provides a direct current signal, and the output circuit (120) outputs a scanning signal from the output terminal (OUTPUT); and an output pull-down circuit (130), which is connected to the output circuit (120). The output circuit (120) is configured to output a scanning signal from the output terminal (OUTPUT) as one from among the direct current signal and the clock signal when a first output condition is satisfied; the output pull-down circuit (130) is configured to pull down the scanning signal when a second output condition is satisfied.

The invention relates to the technical field of artificial intelligence chip data transmission, and provides a dynamic multi-modal packaging method and device and a chip, and the method comprises the steps: a data transmitting end receives an input data stream, analyzes the semantic features of multiple dimensions of the input data stream in real time, and transmits the semantic features to a server; dynamically deciding a target packaging strategy and an effective data count from a plurality of predefined packaging modes according to the multi-dimensional feature information obtained through analysis; packaging effective data in the input data stream according to the target packaging strategy and the effective data count to generate a packaged data block, and adding a packaging information header in front of the packaged data block to obtain a compressed data packet; and the data receiving end receives the compressed data packet, selects a corresponding unpacking mode according to the target packing strategy identifier, and recovers the packed data block to the original data stream. According to the method, the semantic features of the data can be sensed in real time, the optimal packaging strategy is dynamically selected, and the data transmission bandwidth utilization rate and the transmission efficiency are remarkably improved.

The application is suitable for the field of radio frequency technology, and particularly relates to a phase comparison circuit and a radio frequency chip. The phase comparison circuit comprises a first amplifier, a second amplifier, a first frequency divider, a second frequency divider, a first Schmitt trigger, a second Schmitt trigger, a first flip-flop, a second flip-flop, an AND gate unit, a first filter unit and a second filter unit; an input end of the first amplifier is used for receiving a first radio frequency signal, an output end of the first amplifier is connected with an input end of the first frequency divider, an input end of the second amplifier is used for receiving a second radio frequency signal, and an output end of the second amplifier is connected with an input end of the second frequency divider; the first frequency divider and the second frequency divider are respectively used for reducing the frequency of the amplified first radio frequency signal and the amplified second radio frequency signal; compared with the prior art, the phase comparison circuit provided by the application has the advantages of simple structure, wide phase detection range, stable output and the ability to effectively reduce the complexity of radio frequency front-end power control.

The application discloses a register allocation method, device, equipment, medium and product, and the method comprises the steps of obtaining an operation instruction to be allocated, determining an operation width identifier of the operation instruction to be allocated; determining a register allocation mode of the operation instruction to be allocated according to the operation width identifier and a register sharing condition, wherein the register allocation mode comprises a shared register allocation mode and a separate allocation mode; performing physical register allocation on the operation instruction to be allocated based on the register allocation mode, and generating an enhanced renaming table, and each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register. By splitting a single 64-bit physical register into two independent 32-bit sub-registers and realizing shared use, the shared or separate allocation mode is dynamically selected based on the instruction width, space waste caused by using only 32 bits but occupying a complete 64-bit register can be avoided, dynamic power consumption is reduced, and the register utilization rate is significantly improved.

The invention relates to an operational circuit, an accelerator, a chip and a board card. The operational circuitry may be implemented as a computing device included in a combined processing device, which may include one or more data processing devices. The combined processing device can also comprise an interface device and other processing devices. And the computing device interacts with other processing devices to jointly complete the computing operation specified by the user. The combined processing device can further comprise a storage device, and the storage device is connected with the equipment and the other processing devices and used for storing data of the equipment and the other processing devices. Through the scheme of the invention, the repeated multiplication operation in the matrix multiplication operation can be simplified into unary operation accumulation based on the counter, so that the dynamic power consumption of hardware can be saved.

The invention relates to the field of microcontrollers, in particular to the field of industrial control, and specifically relates to an MCU device with portability and low power consumption. The MCU device with portability and low power consumption comprises an instruction architecture, a storage architecture and a pipeline architecture in the aspect of a kernel; an instruction architecture, a storage architecture and a pipeline architecture are simplified; in the aspect of peripherals, design is carried out according to requirements in current industrial scenes, modules such as a UART (Universal Asynchronous Receiver / Transmitter), an SPI (Serial Peripheral Interface) and a TMR0 are modularized, and implementation is carried out based on an SFR bus protocol; a simplified instruction system structure is used, and a PIC16F8X series instruction system is compatible; classifying the instruction into a file register byte-oriented operation type instruction, a file register bit-oriented operation type instruction, an immediate operand operation type instruction and a fixed coding format control type instruction according to different instruction types; in all the operation instructions, the operation code field is located in the highest bit field, and information report instruction types and function information are contained in the operation code field.

This invention discloses a power amplifier and electronic device employing a thin-gate device. The power amplifier uses a fully thin-gate low-threshold voltage transistor architecture, amplifying signals through multiple parallel cascode amplification units. The gate of the input stage transistor is coupled to the input signal via a DC-blocking capacitor, and the drain of the cascode transistor is connected to the power supply via an inductor. By introducing a segmented complementary gain control strategy—selectively turning off the input stage transistor while keeping the cascode transistor on in the high-power output range, and selectively turning off the cascode transistor while keeping the input stage transistor on in the low-power output range—this invention overcomes the performance limitations of traditional hybrid gate oxide schemes, significantly reducing parasitic capacitance and dynamic power consumption, and improving conversion efficiency. It simultaneously resolves the contradiction between the withstand voltage safety and deep turn-off of thin-gate devices, ensuring reliability across the entire power range; and simplifies the manufacturing process and optimizes current efficiency.

The invention relates to a rectangular coordinate-to-polar coordinate conversion method and device based on an LUT and CORDIC hybrid architecture. The method comprises the following steps: S1, sector folding preprocessing; s2, performing coarse rotation iteration; s3, generating a dynamic address; s4, a compression lookup table is queried; and S5, data compensation and reconstruction. According to the method, a small amount of CORDIC iteration is introduced to rotate the input vector to a very small angle range, so that the input space required to be covered by a subsequent lookup table is greatly compressed; meanwhile, the bit width and the address depth of a storage value in the LUT are remarkably reduced by combining module value residual storage and a dynamic truncation technology, so that the storage resources of the LUT are greatly reduced on the premise of ensuring the precision, and the hardware implementation cost is lower.

The invention provides a configurable down-sampling multiple filtering method, circuit and system for a sinc3 filter, and the method comprises the steps: receiving a single-bit data stream from a sigma-delta modulator, carrying out the first-stage integration, the second-stage integration and the third-stage integration in sequence, carrying out the sampling of the third-stage integration value at a (D + 3) th clock, a (2D + 3) th clock and a (3D + 3) th clock, and carrying out the sampling of a (D + 3) th clock, a (2D + 3) th clock and a (3D + 3) th clock; three sampling values are obtained, two-stage differential operation is carried out on the three sampling values, and a final filtering output result is obtained; in the third-level integration process, when the input clock counts to D + 4 and 2D + 4, the second-level integration results of the (D + 3) th clock and the 2D + 3 th clock are used as third-level integration values of the D + 4 moment and the 2D + 4 moment respectively, and D is the set downsampling multiple. According to the method, the downsampling multiple is configurable, the problem that a traditional sinc3 filter with the fixed downsampling multiple lacks flexibility in the BMS field is solved, and the register bit width under the large downsampling multiple is reduced.

This application provides a GNSS-based LSTM state freezing and update control method and apparatus, belonging to the field of LSTM state calculation technology. The method includes: acquiring a GNSS input sequence; calculating the sliding window rate of change using a sliding window rate of change algorithm based on the feature sequence of the GNSS input sequence within a sliding window; freezing the internal state of the LSTM and controlling the LSTM inference process to skip the current state update when the sliding window rate of change continuously satisfies the steady-state condition; and triggering a defreezing mechanism to restore the normal LSTM inference process and update the internal state of the LSTM when the frozen LSTM meets the defreezing condition. This application's solution can reduce state update redundancy and lower dynamic power consumption.

The application relates to the technical field of chip circuits, in particular to a special chip ADC circuit for a retinal prosthesis, which comprises a sampling switch module, a capacitor array module, a dynamic comparator, a digital control logic module and a digital correction module; the capacitor array module comprises a P-end capacitor array and an N-end capacitor array, the P-end capacitor array comprises a plurality of first capacitors connected in parallel, and each first capacitor is connected with a first control switch; the N-end capacitor array comprises a plurality of second capacitors connected in parallel, and each second capacitor is connected with a second control switch; the same direction end of the dynamic comparator is connected with the end capacitor of the P-end capacitor array, and the reverse end of the dynamic comparator is connected with the end capacitor of the N-end capacitor array; the digital control logic module is connected with the output end of the dynamic comparator; and the digital correction module is connected with the output end of the digital control logic module. The ADC circuit provided by the application is used for converting a sensor analog signal into a digital signal and realizes low power consumption and high resolution.

The invention relates to a unified memory architecture supporting a multi-post quantum algorithm and a near memory mapping method thereof. The invention relates to the technical field of post quantum cryptography. The architecture comprises a program controller, an instruction ROM, a Keccak module, a sampler and a polynomial arithmetic unit, the program controller decodes an instruction from the ROM, wherein the instruction specifies an operation type, a source / target operand and a control signal; a Hash function mode is selected through a control signal of the Keccak controller; the sampler is tightly coupled with Keccak output and comprises a parallel logic unit of each mode, and an internal arbiter selects sampling variants according to a current instruction and activates corresponding sub-modules; the polynomial arithmetic unit supports high throughput polynomial operation. According to the method, multiple post quantum cryptography algorithms can be efficiently supported on a single hardware platform, and flexible switching among the algorithms can be realized on the premise of not sacrificing performance.

The utility model provides a storage device with low delay characteristic, include: a plurality of selection transistor, a plurality of floating gate transistor, a plurality of floating gate transistor respectively with bit line and word line electric nature connection, wherein a plurality of floating gate transistor respectively with corresponding selection transistor electric nature connection, and with the form of storage unit integrated in same flash memory chip, and floating gate transistor includes control grid, source electrode and drain electrode, wherein control grid and word line electric nature connection, any electrode in source electrode or drain electrode is in floating state, and another electrode electric nature connection is in bit line, and main controller is electrically connected with host computer and flash memory chip, and according to the instruction random access any storage unit of host computer. The utility model can provide high density and high reliability storage space under the premise of not using error correction related technology.

The application relates to an ultra-low-power nanometer floating gate 3D NAND structure, which comprises a substrate, a stack structure arranged on the substrate, the stack structure comprising a plurality of first insulating medium layers and nanometer floating gate storage structures which are alternately stacked, a plurality of through holes penetrating through the stack structure, a tunneling medium layer and a center channel layer being sequentially arranged on the sidewall of each through hole, and a center insulating medium layer being filled in the center channel layer; the nanometer floating gate storage structure is vertically arranged with the tunneling medium layer of the sidewall of the through hole, a second insulating medium layer and a blocking medium layer are sequentially arranged in the direction from the tunneling medium layer to the outside of the through hole, a gate word line metal is embedded on the outside of the blocking medium layer, and a nanometer floating gate layer is arranged below the second insulating medium layer and part of the blocking medium layer. The structure can effectively inhibit charge coupling interference and reduce working voltage and power consumption while further reducing the word line spacing to realize high-density size miniaturization.

This invention belongs to the field of integrated circuit design and microarchitecture technology, and provides a high-bandwidth AI computing chip based on the Chiplet chip architecture and its acceleration method. The method constructs a hardware-enforced data closed loop including read and adaptive prefetching steps, data format rearrangement and inversion steps, systolic tensor calculation triggering steps, bandwidth prediction and allocation steps, dynamic data stream scheduling steps, full-reduce parallel communication steps, and pipeline bubble elimination steps. The memory access acceleration engine outputs prefetched key-value cache data blocks and unformatted weight data blocks through an adaptive prefetching algorithm; the tensor rearrangement engine performs address mapping inversion operations to output column-major weight tensors; the systolic array performs point accumulation and addition operations to generate transmission request trigger signals; and the dynamic bandwidth allocation module outputs predicted bandwidth allocation instructions based on an exponentially weighted moving average algorithm. This invention significantly reduces communication latency, eliminates pipeline bubbles, and improves energy efficiency at the physical level.

The application belongs to the technical field of edge computing and integrated circuit, and particularly relates to a low-power reconfigurable electronic component chip scheduling system for edge computing, which comprises a task semantic perception module, a resource state monitoring module, a power consumption trajectory prediction and voltage compensation module, a reconfiguration granularity control module and an integrated scheduling core module. The system extracts a task feature vector, combines a real-time monitored logic array state, predicts power consumption by using a configuration jump Hamming distance, and implements voltage pre-compensation. Local fine-grained reconfiguration is realized by cooperating with bit stream compression and shielding mask. The scheduling core performs resource mapping and strategy generation based on multi-objective optimization logic, realizes efficient and accurate scheduling of reconfigurable resources, and significantly improves the system energy efficiency ratio and operation stability.

The invention discloses an RISC-V processor-oriented finite field modular operation acceleration implementation method. Comprising the following steps: 1, constructing an unsaturated multi-limb representation model of finite field elements in a 64-bit general register of a processor; 2, based on a multiplication instruction execution delay characteristic of the RISC-V processor, designing a calculation and memory access interleaved instruction scheduling strategy; 3, carrying out decoupling scheduling on carry propagation and a modular reduction path by adopting a delay correction mechanism in the general register; 4, aiming at modular square operation, constructing an instruction level reduction path in a processor instruction set environment, and realizing cross-limb carry processing through a logic shift instruction and an unsigned comparison instruction; and 5, realizing a delay accumulation and mask correction mechanism of modular addition and subtraction operation on a register level by using a redundant bit width represented by unsaturation. According to the method, on the premise of not changing the mathematical structure of the original cryptographic algorithm, the operation acceleration which is several times of the existing implementation is realized by optimizing the register resources and instruction scheduling of the processor.

This invention discloses a wafer stacking structure and its fabrication method. The wafer stacking structure includes two stacking units and a wafer interconnect structure disposed on the stacking units. Each stacking unit includes a wafer and a first metal interconnect layer formed on the front side of the wafer. The two stacking units are connected through their respective first metal interconnect layers. The first metal interconnect layer includes a metal layer, a first via, and a first pad stacked sequentially from the front side of the wafer. The wafer interconnect structure is formed on any stacking unit and includes a TSV via formed within the wafer and a second via and a second pad stacked sequentially from the back side of the wafer. The second via corresponds one-to-one with the TSV via and is coaxially aligned and connected. The second pad is disposed one-to-one above the second via. The wafer stacking structure of this invention eliminates the additional interconnect path of the RDL, shortens the signal transmission path, significantly reduces RC delay, improves signal transmission speed, and reduces dynamic power consumption.

The application discloses a kind of based on built-in bypass window algorithm's analog-digital converter, it is related to integrated circuit technical field, digital-analog converter includes DAC structure, clocked dynamic comparator and bypass window logic detection circuit;The highest significant bit capacitor of DAC structure is divided into first sub-capacitor and second sub-capacitor based on physical split structure, and clocked dynamic comparator generates first comparison result and second comparison result based on first sub-capacitor and second sub-capacitor;Bypass window logic detection circuit generates mode control signal based on first comparison result and second comparison result, enters bypass operating mode based on mode control signal, or enters normal operating mode based on mode control signal.The highest significant bit capacitor of the capacitor array of DAC structure is split and the first sub-capacitor is reused with main comparator to realize bypass window detection, can skip part high bit capacitor switching when input signal changes little, reduce dynamic power consumption caused by capacitor array flip.

The application discloses a level conversion circuit with adjustable output swing, and relates to the technical field of integrated circuits, comprising an input inverting buffer module, a level conversion control module and an output driving module. The input inverting buffer module is connected with a signal input end and is used for outputting two internal driving signals with opposite logic; the level conversion control module is used for resetting the level of a gate control voltage by capacitive coupling and a switch tube; and the output driving module comprises a first transmission gate connected between a first level VDDH and a signal output end, and a second transmission gate connected between a second level VDDL and the signal output end. By controlling the opening and closing of the first and second transmission gates, the application realizes flexible and adjustable output swing according to VDDH and VDDL. Without increasing the chip area, the application shortens the switching time of the subsequent circuit, improves the switching rate of the circuit, reduces the power consumption, and is suitable for high-speed and low-power consumption circuits.