46results about How to "Reduce dynamic power consumption" patented technology

The invention provides a PCIe clock gating circuit and a PCIe clock control method. The PCIe clock gating circuit comprises a link width control circuit, a link rate control circuit and a link state control circuit, the link width control circuit is used for outputting a control signal for closing a clock of a module not related to the current width when the current link width is smaller than the maximum width; the link rate control circuit is used for outputting a control signal for closing a clock of a non-current rate related module, and the link state control circuit is used for outputting a control signal for closing a clock of an abnormal working state related module when the current link state is an abnormal working state. The abnormal working state related modules comprise related modules corresponding to other link states except the current link state; and the link state control circuit is also used for outputting a control signal for closing clocks of the training code stream sending module, the training code stream receiving module and the link training related module in a normal working state.

The invention discloses a branch prediction unit power consumption management method and device, and the method comprises the steps: setting a multi-stage branch predictor and a low-power-consumption control logic coupled with the multi-stage branch predictor in a processor core micro-architecture, and enabling the multi-stage branch predictor to comprise three stages of predictors which are sequentially accessed in an assembly line, the hardware resource consumption and the prediction accuracy of each predictor are gradually increased from front to back; monitoring the prediction condition of each predictor in real time through low-power-consumption control logic, and closing all predictors behind the first predictor meeting the prediction requirement within a first preset time according to a front-to-back sequence; branch jump addresses are divided into high-order address fields and low-order address fields by BTBs in the multiple levels of predictors except the first-level predictor to be stored in different storage blocks, and label registers used for taking the high-order addresses as label indexes are arranged. The power consumption unit of each predictor can be finely controlled, the energy consumption is greatly reduced, system-level cooperation is not needed, and the universality is high.

The invention discloses a redundancy-based hardware failure time division multiplexing detection circuit and method, and the method comprises the steps: enabling the counting of an input selection counter to be connected with a first input completion mark outputted by an upstream circuit, and enabling the counting of an output selection counter to be connected with a second input completion mark outputted by a downstream circuit; the output end of the input selection counter is connected with the enabling end of the input selector muxin, and the output end of the output selection counter is connected with the enabling end of the output selector muxout; the input end of the input selector muxin is connected with the output of the upstream circuit, the output end of the input selector muxin is connected with the input end of the redundant circuit, the input end of the output selector muxout is connected with the output of the hardware circuit, and the output end of the output selector muxout is connected with one input end of the comparator; the input end of the redundant circuit is connected with the output end of the input selector muxin, the output end of the redundant circuit is connected with the other input end of the comparator, and the output end of the comparator is connected with the control register.

The invention provides a standard cell memory and a chip, and the memory comprises an input latch module which carries out the latch output of a source enable signal, an address signal and a data signal; the address decoding control module is used for generating a write-in enable signal and a read-out enable signal based on the source enable signal and the address signal; the data storage module comprises a first storage unit and a second storage unit, the first storage unit and the second storage unit are arranged into a storage array based on a checkerboard pattern, enabling ends of the storage units in the same row are cascaded through an external phase inverter and receive selective writing enabling bits of the corresponding row, and data ends of the storage units in the same column are cascaded through an internal phase inverter and receive corresponding data bits; storing each data bit into each storage unit of the corresponding row based on the corresponding row write selection enabling bit; and the data reading module comprises a column reading unit and is used for reading the data bits in the storage units of the corresponding rows in a layered reading manner. According to the invention, the problem that the dynamic power consumption of the existing standard cell memory is increased along with the increase of the design capacity is solved.

The invention discloses an asynchronous FIFO (First In First Out) based on an event-driven circuit and a data processing method thereof, and the asynchronous FIFO comprises a dual-port RAM (Random Access Memory) module, a writing pointer / reading pointer self-increasing module, a writing pointer / reading pointer Gray code conversion module, a full writing or empty reading judgment module, a two-stage register and a writing / reading control path, a starting signal of the write / read control access is a write / read request event, generates a pulse signal to drive a register to sample after being started, and transmits data to a full-write or empty-read judgment module; and a corresponding writing / reading response signal is generated after one-time data writing / reading is completed. When write operation is carried out, input data and write request event signals are bound and input into the FIFO together, and when read operation is carried out, only read request events are input into the FIFO. The event-driven circuit design method is adopted, the circuit does not depend on clock signals, the circuit is driven to work through handshake signals of requests and responses, and the problem of adaptation of asynchronous FIFO to the event-driven circuit is solved.

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

This invention belongs to the technical field of integrated circuit manufacturing, and discloses a SAR-assisted pipelined analog-to-digital converter and its control method. The analog-to-digital converter includes a two-stage SAR ADC module, and the first stage capacitor array includes C 1 1 ~C 1 M‑1 C 1 2 ~C 1 M‑1 The reference voltage is V ref C 1 1 The reference voltage is V cm =V ref / 2, an improved monotonic switching scheme using redundant capacitors can perform successive approximation comparisons to obtain an M-bit digital code. After completing the first-stage conversion, a passive residual transfer scheme is used, along with inter-stage bit transfer, to enter the second-stage conversion. This second-stage conversion employs the same improved monotonic switching scheme as the first stage, performing successive approximation comparisons to obtain an N-bit digital code. Finally, through timing alignment, an M+N-bit digital code is obtained. This design saves device area and improves conversion efficiency.

The invention belongs to the technical field of deep space exploration, and particularly relates to a multispectral image displacement depth adaptive mapping method and system based on radiometric calibration, and the method comprises the steps: obtaining original black field data with the input bit depth being N and original flat field data with the input bit depth being N; after bad pixels are shielded according to the original black field data and the original flat field data, row offset and row response are calculated; sequentially determining a global scale according to the row offset and the row response, calculating an integration slope, and generating a lookup table according to the integration slope; and acquiring real-time monitoring input, reading the M-bit output value corresponding to the real-time monitoring input according to the lookup table, and correcting and updating the lookup table according to the M-bit output value. Based on a parameterized calculation process (derivation from row bias and row response to a global scale and an integrated slope), different input bit depth and output bit depth requirements can be met by modifying input parameters, inherent limitation caused by hard coding is avoided, and the configurability of cross-platform tasks is improved.

The invention discloses a multi-bit trigger design method for a standard cell library and a scan chain, and belongs to the technical field of integrated circuits, the multi-bit trigger design method for the standard cell library comprises the following steps: providing a plurality of single-bit triggers, and setting the flipping rate of each single-bit trigger; arranging the single-bit triggers, and placing the single-bit trigger with the lowest flipping rate at the last position; the single-bit triggers are serially connected into a scan chain according to the sequence, the first single-bit trigger is used for accessing input data and a scan chain control signal, and the output end of the last single-bit trigger is used for outputting data. By arranging the triggers with the lowest flipping rate at the output end, the DFT dynamic power consumption can be reduced, and the Power signoff can be optimized.

A method for accelerating finite-field modular arithmetic on RISC-V processors is disclosed. The method includes: 1. Constructing a non-saturated multi-limb representation model of finite-field elements in the processor's 64-bit general-purpose registers; 2. Designing an instruction scheduling strategy that interleaves computation and memory access based on the execution latency characteristics of multiplication instructions in the RISC-V processor; 3. Employing a latency correction mechanism within the general-purpose registers to decouple carry propagation and modular reduction path scheduling; 4. For modular square operations, constructing an instruction-level reduction path within the processor's instruction set environment, and implementing cross-limb carry processing through logical shift instructions and unsigned comparison instructions; 5. Utilizing the redundant bit width of the non-saturated representation, implementing a latency accumulation and mask correction mechanism for modular addition and subtraction operations at the register level. This invention achieves a computational speedup several times greater than existing implementations by optimizing processor register resources and instruction scheduling without altering the original mathematical structure of cryptographic algorithms.

The invention relates to a synchronous circuit and a chip. The synchronous circuit comprises a cache module; a storage module; the write control module is used for determining write address information according to the write command and generating a trigger signal under the condition that the write address information is an address in the cache module; the synchronous control module is used for determining a current count value according to the trigger signal and the write address information, and adding one to the current count value and generating a first synchronous enable signal under the condition that the current count value is smaller than a time threshold value, resetting the current count value and generating a second synchronization enable signal under the condition that the current count value is equal to the time threshold value; and the write control module is also used for writing the write data into an address corresponding to the cache module according to the first synchronous enable signal and the write address information and / or writing the write data into the storage module according to the second synchronous enable signal and the write address information. The dynamic power consumption can be reduced, and the bandwidth utilization rate and the data access efficiency can be improved.

This invention discloses an efficient QR matrix decomposition method based on FPGA for implementing systolic matrices, belonging to the field of software-defined radio signal transmission technology for airborne networks. It is based on the design of a multi-channel digital front-end implemented on an FPGA chip. The method includes: designing a general handshake coordination mechanism, designing a timing flow for systolic matrix multiplication, performing fast QR matrix decomposition single-loop operations by calculating the Householder mirror transformation matrix, designing a top-level loop pipeline for QR matrix decomposition, and finally verifying the hardware scheme of the fast QR decomposition algorithm. This invention converts resource consumption into timing consumption by designing the overall pipeline logic and loop operations, enabling fast processing and accurate decomposition of digital information in a multi-channel digital front-end on an FPGA, effectively saving on-chip resources. In addition, this invention has excellent scalability, supporting 64 to 128-bit high-precision fixed-point number formats, and the data matrix order can reach up to 128.

The present invention discloses a testability architecture of a chip, and relates to the technical field of integrated circuits. The testability architecture provided by the present invention includes a test logic module and a functional logic module, wherein the test logic module includes an independent test unit and a mixed test unit, wherein the independent test unit and the functional logic module are separated from each other; the testability architecture has a functional mode and a test mode, wherein in the functional mode, the power supply of the independent test unit is disconnected; in the test mode, the power supply of the independent test unit, the mixed test unit, and the functional logic module is in an on state. Based on the use of clock gating to reduce the dynamic power consumption of a testable design chip, the present invention uses a multi-power domain method to power off the test logic module, thereby achieving the purpose of significantly reducing static power consumption, so that the overall power consumption of the chip during operation is lower.

A shift register (100), a gate drive circuit (10), a display panel (1), and a driving method. The shift register (100) comprises: an input circuit (110), which is connected to a pull-up node (PU) and an input signal terminal (INPUT) respectively; an output circuit (120), which is connected to the pull-up node (PU), a clock signal terminal (CLK), a direct current signal terminal (GCH) and an input terminal (OUTPUT) respectively, wherein the clock signal terminal (CLK) provides a clock signal, the direct current signal terminal (GCH) provides a direct current signal, and the output circuit (120) outputs a scanning signal from the output terminal (OUTPUT); and an output pull-down circuit (130), which is connected to the output circuit (120). The output circuit (120) is configured to output a scanning signal from the output terminal (OUTPUT) as one from among the direct current signal and the clock signal when a first output condition is satisfied; the output pull-down circuit (130) is configured to pull down the scanning signal when a second output condition is satisfied.

The invention relates to the technical field of artificial intelligence chip data transmission, and provides a dynamic multi-modal packaging method and device and a chip, and the method comprises the steps: a data transmitting end receives an input data stream, analyzes the semantic features of multiple dimensions of the input data stream in real time, and transmits the semantic features to a server; dynamically deciding a target packaging strategy and an effective data count from a plurality of predefined packaging modes according to the multi-dimensional feature information obtained through analysis; packaging effective data in the input data stream according to the target packaging strategy and the effective data count to generate a packaged data block, and adding a packaging information header in front of the packaged data block to obtain a compressed data packet; and the data receiving end receives the compressed data packet, selects a corresponding unpacking mode according to the target packing strategy identifier, and recovers the packed data block to the original data stream. According to the method, the semantic features of the data can be sensed in real time, the optimal packaging strategy is dynamically selected, and the data transmission bandwidth utilization rate and the transmission efficiency are remarkably improved.

The application is suitable for the field of radio frequency technology, and particularly relates to a phase comparison circuit and a radio frequency chip. The phase comparison circuit comprises a first amplifier, a second amplifier, a first frequency divider, a second frequency divider, a first Schmitt trigger, a second Schmitt trigger, a first flip-flop, a second flip-flop, an AND gate unit, a first filter unit and a second filter unit; an input end of the first amplifier is used for receiving a first radio frequency signal, an output end of the first amplifier is connected with an input end of the first frequency divider, an input end of the second amplifier is used for receiving a second radio frequency signal, and an output end of the second amplifier is connected with an input end of the second frequency divider; the first frequency divider and the second frequency divider are respectively used for reducing the frequency of the amplified first radio frequency signal and the amplified second radio frequency signal; compared with the prior art, the phase comparison circuit provided by the application has the advantages of simple structure, wide phase detection range, stable output and the ability to effectively reduce the complexity of radio frequency front-end power control.

The application discloses a register allocation method, device, equipment, medium and product, and the method comprises the steps of obtaining an operation instruction to be allocated, determining an operation width identifier of the operation instruction to be allocated; determining a register allocation mode of the operation instruction to be allocated according to the operation width identifier and a register sharing condition, wherein the register allocation mode comprises a shared register allocation mode and a separate allocation mode; performing physical register allocation on the operation instruction to be allocated based on the register allocation mode, and generating an enhanced renaming table, and each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register. By splitting a single 64-bit physical register into two independent 32-bit sub-registers and realizing shared use, the shared or separate allocation mode is dynamically selected based on the instruction width, space waste caused by using only 32 bits but occupying a complete 64-bit register can be avoided, dynamic power consumption is reduced, and the register utilization rate is significantly improved.

The invention provides a low dropout linear regulator with low power consumption and fast transient response and a microprocessor. A main loop circuit is configured to receive a reference voltage and a feedback voltage and adjust an output voltage to enable the output voltage to be constant at an expected value; the first loop circuit is configured to be connected with the main loop in parallel, receive the reference voltage and the feedback voltage and are used for adjusting the transient condition that the output load current is changed from small to large; the second loop circuit is configured to be connected in parallel with the main loop and receive the feedback voltage for adjusting the transient condition of the output load current from large to small. When the output is stable, the first loop circuit and the second loop circuit are in a closed state, the first loop circuit enhances the adjustment of the system on the suddenly dropped output voltage, and the second loop circuit enhances the adjustment of the system on the suddenly raised output voltage. The first loop circuit and the second loop circuit work together, opening or closing of the loop is selected according to the condition of the load, and energy consumption is saved.

The invention relates to an operational circuit, an accelerator, a chip and a board card. The operational circuitry may be implemented as a computing device included in a combined processing device, which may include one or more data processing devices. The combined processing device can also comprise an interface device and other processing devices. And the computing device interacts with other processing devices to jointly complete the computing operation specified by the user. The combined processing device can further comprise a storage device, and the storage device is connected with the equipment and the other processing devices and used for storing data of the equipment and the other processing devices. Through the scheme of the invention, the repeated multiplication operation in the matrix multiplication operation can be simplified into unary operation accumulation based on the counter, so that the dynamic power consumption of hardware can be saved.

The invention relates to the field of microcontrollers, in particular to the field of industrial control, and specifically relates to an MCU device with portability and low power consumption. The MCU device with portability and low power consumption comprises an instruction architecture, a storage architecture and a pipeline architecture in the aspect of a kernel; an instruction architecture, a storage architecture and a pipeline architecture are simplified; in the aspect of peripherals, design is carried out according to requirements in current industrial scenes, modules such as a UART (Universal Asynchronous Receiver / Transmitter), an SPI (Serial Peripheral Interface) and a TMR0 are modularized, and implementation is carried out based on an SFR bus protocol; a simplified instruction system structure is used, and a PIC16F8X series instruction system is compatible; classifying the instruction into a file register byte-oriented operation type instruction, a file register bit-oriented operation type instruction, an immediate operand operation type instruction and a fixed coding format control type instruction according to different instruction types; in all the operation instructions, the operation code field is located in the highest bit field, and information report instruction types and function information are contained in the operation code field.

This invention discloses a power amplifier and electronic device employing a thin-gate device. The power amplifier uses a fully thin-gate low-threshold voltage transistor architecture, amplifying signals through multiple parallel cascode amplification units. The gate of the input stage transistor is coupled to the input signal via a DC-blocking capacitor, and the drain of the cascode transistor is connected to the power supply via an inductor. By introducing a segmented complementary gain control strategy—selectively turning off the input stage transistor while keeping the cascode transistor on in the high-power output range, and selectively turning off the cascode transistor while keeping the input stage transistor on in the low-power output range—this invention overcomes the performance limitations of traditional hybrid gate oxide schemes, significantly reducing parasitic capacitance and dynamic power consumption, and improving conversion efficiency. It simultaneously resolves the contradiction between the withstand voltage safety and deep turn-off of thin-gate devices, ensuring reliability across the entire power range; and simplifies the manufacturing process and optimizes current efficiency.

The utility model relates to a low-power-consumption control circuit, a chip and electronic equipment. The low-power-consumption control circuit comprises a sequential logic circuit used for controlling output of data signals according to clock signals and a combinational logic circuit used for receiving the data signals and outputting the data signals in a combined mode. One end of the sequential logic circuit is electrically connected with external data signal output equipment, and the other end of the sequential logic circuit is electrically connected with the combinational logic circuit; the sequential logic circuit comprises a gated clock and at least one trigger; the gated clock is used for controlling an output clock signal; and the trigger is connected with the gated clock and is used for outputting a data signal when receiving the clock signal and temporarily storing the data signal when not receiving the clock signal. According to the scheme provided by the invention, when the circuit module is not in use, the flip rate of the internal signal can be reduced, so that the dynamic power consumption of the chip is reduced.

The invention relates to a rectangular coordinate-to-polar coordinate conversion method and device based on an LUT and CORDIC hybrid architecture. The method comprises the following steps: S1, sector folding preprocessing; s2, performing coarse rotation iteration; s3, generating a dynamic address; s4, a compression lookup table is queried; and S5, data compensation and reconstruction. According to the method, a small amount of CORDIC iteration is introduced to rotate the input vector to a very small angle range, so that the input space required to be covered by a subsequent lookup table is greatly compressed; meanwhile, the bit width and the address depth of a storage value in the LUT are remarkably reduced by combining module value residual storage and a dynamic truncation technology, so that the storage resources of the LUT are greatly reduced on the premise of ensuring the precision, and the hardware implementation cost is lower.

The invention provides a configurable down-sampling multiple filtering method, circuit and system for a sinc3 filter, and the method comprises the steps: receiving a single-bit data stream from a sigma-delta modulator, carrying out the first-stage integration, the second-stage integration and the third-stage integration in sequence, carrying out the sampling of the third-stage integration value at a (D + 3) th clock, a (2D + 3) th clock and a (3D + 3) th clock, and carrying out the sampling of a (D + 3) th clock, a (2D + 3) th clock and a (3D + 3) th clock; three sampling values are obtained, two-stage differential operation is carried out on the three sampling values, and a final filtering output result is obtained; in the third-level integration process, when the input clock counts to D + 4 and 2D + 4, the second-level integration results of the (D + 3) th clock and the 2D + 3 th clock are used as third-level integration values of the D + 4 moment and the 2D + 4 moment respectively, and D is the set downsampling multiple. According to the method, the downsampling multiple is configurable, the problem that a traditional sinc3 filter with the fixed downsampling multiple lacks flexibility in the BMS field is solved, and the register bit width under the large downsampling multiple is reduced.

This application provides a GNSS-based LSTM state freezing and update control method and apparatus, belonging to the field of LSTM state calculation technology. The method includes: acquiring a GNSS input sequence; calculating the sliding window rate of change using a sliding window rate of change algorithm based on the feature sequence of the GNSS input sequence within a sliding window; freezing the internal state of the LSTM and controlling the LSTM inference process to skip the current state update when the sliding window rate of change continuously satisfies the steady-state condition; and triggering a defreezing mechanism to restore the normal LSTM inference process and update the internal state of the LSTM when the frozen LSTM meets the defreezing condition. This application's solution can reduce state update redundancy and lower dynamic power consumption.

The application relates to the technical field of chip circuits, in particular to a special chip ADC circuit for a retinal prosthesis, which comprises a sampling switch module, a capacitor array module, a dynamic comparator, a digital control logic module and a digital correction module; the capacitor array module comprises a P-end capacitor array and an N-end capacitor array, the P-end capacitor array comprises a plurality of first capacitors connected in parallel, and each first capacitor is connected with a first control switch; the N-end capacitor array comprises a plurality of second capacitors connected in parallel, and each second capacitor is connected with a second control switch; the same direction end of the dynamic comparator is connected with the end capacitor of the P-end capacitor array, and the reverse end of the dynamic comparator is connected with the end capacitor of the N-end capacitor array; the digital control logic module is connected with the output end of the dynamic comparator; and the digital correction module is connected with the output end of the digital control logic module. The ADC circuit provided by the application is used for converting a sensor analog signal into a digital signal and realizes low power consumption and high resolution.

The invention discloses a source electrode driving chip, a mode control method and a display device. The source electrode driving chip is connected with the time schedule controller and comprises a state detection module, a logic control module and a first mode control module. The state detection module is used for detecting whether a locking signal output by the source electrode driving chip to the time schedule controller is switched from a first level to a second level. The logic control module is used for controlling the first mode control module to start a first recognition mode when a locking signal is switched from a first level to a second level, and performing first correctness verification on driving information of an image frame; and after the target condition is met, the first mode control module is controlled to close the first recognition mode. Through the working state control of the first identification mode, the dynamic power consumption of the source electrode driving chip is reduced, so that the energy consumption of the display device is reduced.

The present invention discloses a Start and Stop identification circuit and method of an I2C bus, comprising a first register F1, a second register F2, a latch SR, a NAND gate A1, a NAND gate A2, a NAND gate I1, a NAND gate I2, a NAND gate I3 and a delay device Delay. When a signal SCL is at a low level, the circuit does not identify Start and Stop, and uses the signal SCL as an output signal for resetting the two registers Start and Stop. The present invention can realize the identification of Start and Stop by using only two signals SDC and SCL, without using a high-speed clock, and the dynamic power consumption of the circuit is extremely low when working. Compared with the prior art, the present invention adopts a different solution to realize a similar solution of realizing the identification of Start and Stop without using a high-speed clock, and the present invention has fewer registers and logic gates, and a simpler circuit structure.

The invention relates to a unified memory architecture supporting a multi-post quantum algorithm and a near memory mapping method thereof. The invention relates to the technical field of post quantum cryptography. The architecture comprises a program controller, an instruction ROM, a Keccak module, a sampler and a polynomial arithmetic unit, the program controller decodes an instruction from the ROM, wherein the instruction specifies an operation type, a source / target operand and a control signal; a Hash function mode is selected through a control signal of the Keccak controller; the sampler is tightly coupled with Keccak output and comprises a parallel logic unit of each mode, and an internal arbiter selects sampling variants according to a current instruction and activates corresponding sub-modules; the polynomial arithmetic unit supports high throughput polynomial operation. According to the method, multiple post quantum cryptography algorithms can be efficiently supported on a single hardware platform, and flexible switching among the algorithms can be realized on the premise of not sacrificing performance.

The utility model provides a storage device with low delay characteristic, include: a plurality of selection transistor, a plurality of floating gate transistor, a plurality of floating gate transistor respectively with bit line and word line electric nature connection, wherein a plurality of floating gate transistor respectively with corresponding selection transistor electric nature connection, and with the form of storage unit integrated in same flash memory chip, and floating gate transistor includes control grid, source electrode and drain electrode, wherein control grid and word line electric nature connection, any electrode in source electrode or drain electrode is in floating state, and another electrode electric nature connection is in bit line, and main controller is electrically connected with host computer and flash memory chip, and according to the instruction random access any storage unit of host computer. The utility model can provide high density and high reliability storage space under the premise of not using error correction related technology.