10results about How to "Reduce dynamic power consumption" patented technology

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

The invention belongs to the technical field of deep space exploration, and particularly relates to a multispectral image displacement depth adaptive mapping method and system based on radiometric calibration, and the method comprises the steps: obtaining original black field data with the input bit depth being N and original flat field data with the input bit depth being N; after bad pixels are shielded according to the original black field data and the original flat field data, row offset and row response are calculated; sequentially determining a global scale according to the row offset and the row response, calculating an integration slope, and generating a lookup table according to the integration slope; and acquiring real-time monitoring input, reading the M-bit output value corresponding to the real-time monitoring input according to the lookup table, and correcting and updating the lookup table according to the M-bit output value. Based on a parameterized calculation process (derivation from row bias and row response to a global scale and an integrated slope), different input bit depth and output bit depth requirements can be met by modifying input parameters, inherent limitation caused by hard coding is avoided, and the configurability of cross-platform tasks is improved.

A method for accelerating finite-field modular arithmetic on RISC-V processors is disclosed. The method includes: 1. Constructing a non-saturated multi-limb representation model of finite-field elements in the processor's 64-bit general-purpose registers; 2. Designing an instruction scheduling strategy that interleaves computation and memory access based on the execution latency characteristics of multiplication instructions in the RISC-V processor; 3. Employing a latency correction mechanism within the general-purpose registers to decouple carry propagation and modular reduction path scheduling; 4. For modular square operations, constructing an instruction-level reduction path within the processor's instruction set environment, and implementing cross-limb carry processing through logical shift instructions and unsigned comparison instructions; 5. Utilizing the redundant bit width of the non-saturated representation, implementing a latency accumulation and mask correction mechanism for modular addition and subtraction operations at the register level. This invention achieves a computational speedup several times greater than existing implementations by optimizing processor register resources and instruction scheduling without altering the original mathematical structure of cryptographic algorithms.

This invention discloses an efficient QR matrix decomposition method based on FPGA for implementing systolic matrices, belonging to the field of software-defined radio signal transmission technology for airborne networks. It is based on the design of a multi-channel digital front-end implemented on an FPGA chip. The method includes: designing a general handshake coordination mechanism, designing a timing flow for systolic matrix multiplication, performing fast QR matrix decomposition single-loop operations by calculating the Householder mirror transformation matrix, designing a top-level loop pipeline for QR matrix decomposition, and finally verifying the hardware scheme of the fast QR decomposition algorithm. This invention converts resource consumption into timing consumption by designing the overall pipeline logic and loop operations, enabling fast processing and accurate decomposition of digital information in a multi-channel digital front-end on an FPGA, effectively saving on-chip resources. In addition, this invention has excellent scalability, supporting 64 to 128-bit high-precision fixed-point number formats, and the data matrix order can reach up to 128.

The application is suitable for the field of radio frequency technology, and particularly relates to a phase comparison circuit and a radio frequency chip. The phase comparison circuit comprises a first amplifier, a second amplifier, a first frequency divider, a second frequency divider, a first Schmitt trigger, a second Schmitt trigger, a first flip-flop, a second flip-flop, an AND gate unit, a first filter unit and a second filter unit; an input end of the first amplifier is used for receiving a first radio frequency signal, an output end of the first amplifier is connected with an input end of the first frequency divider, an input end of the second amplifier is used for receiving a second radio frequency signal, and an output end of the second amplifier is connected with an input end of the second frequency divider; the first frequency divider and the second frequency divider are respectively used for reducing the frequency of the amplified first radio frequency signal and the amplified second radio frequency signal; compared with the prior art, the phase comparison circuit provided by the application has the advantages of simple structure, wide phase detection range, stable output and the ability to effectively reduce the complexity of radio frequency front-end power control.

This invention discloses a power amplifier and electronic device employing a thin-gate device. The power amplifier uses a fully thin-gate low-threshold voltage transistor architecture, amplifying signals through multiple parallel cascode amplification units. The gate of the input stage transistor is coupled to the input signal via a DC-blocking capacitor, and the drain of the cascode transistor is connected to the power supply via an inductor. By introducing a segmented complementary gain control strategy—selectively turning off the input stage transistor while keeping the cascode transistor on in the high-power output range, and selectively turning off the cascode transistor while keeping the input stage transistor on in the low-power output range—this invention overcomes the performance limitations of traditional hybrid gate oxide schemes, significantly reducing parasitic capacitance and dynamic power consumption, and improving conversion efficiency. It simultaneously resolves the contradiction between the withstand voltage safety and deep turn-off of thin-gate devices, ensuring reliability across the entire power range; and simplifies the manufacturing process and optimizes current efficiency.

The invention relates to a rectangular coordinate-to-polar coordinate conversion method and device based on an LUT and CORDIC hybrid architecture. The method comprises the following steps: S1, sector folding preprocessing; s2, performing coarse rotation iteration; s3, generating a dynamic address; s4, a compression lookup table is queried; and S5, data compensation and reconstruction. According to the method, a small amount of CORDIC iteration is introduced to rotate the input vector to a very small angle range, so that the input space required to be covered by a subsequent lookup table is greatly compressed; meanwhile, the bit width and the address depth of a storage value in the LUT are remarkably reduced by combining module value residual storage and a dynamic truncation technology, so that the storage resources of the LUT are greatly reduced on the premise of ensuring the precision, and the hardware implementation cost is lower.

The utility model provides a storage device with low delay characteristic, include: a plurality of selection transistor, a plurality of floating gate transistor, a plurality of floating gate transistor respectively with bit line and word line electric nature connection, wherein a plurality of floating gate transistor respectively with corresponding selection transistor electric nature connection, and with the form of storage unit integrated in same flash memory chip, and floating gate transistor includes control grid, source electrode and drain electrode, wherein control grid and word line electric nature connection, any electrode in source electrode or drain electrode is in floating state, and another electrode electric nature connection is in bit line, and main controller is electrically connected with host computer and flash memory chip, and according to the instruction random access any storage unit of host computer. The utility model can provide high density and high reliability storage space under the premise of not using error correction related technology.

The application belongs to the technical field of edge computing and integrated circuit, and particularly relates to a low-power reconfigurable electronic component chip scheduling system for edge computing, which comprises a task semantic perception module, a resource state monitoring module, a power consumption trajectory prediction and voltage compensation module, a reconfiguration granularity control module and an integrated scheduling core module. The system extracts a task feature vector, combines a real-time monitored logic array state, predicts power consumption by using a configuration jump Hamming distance, and implements voltage pre-compensation. Local fine-grained reconfiguration is realized by cooperating with bit stream compression and shielding mask. The scheduling core performs resource mapping and strategy generation based on multi-objective optimization logic, realizes efficient and accurate scheduling of reconfigurable resources, and significantly improves the system energy efficiency ratio and operation stability.

The application discloses a kind of based on built-in bypass window algorithm's analog-digital converter, it is related to integrated circuit technical field, digital-analog converter includes DAC structure, clocked dynamic comparator and bypass window logic detection circuit;The highest significant bit capacitor of DAC structure is divided into first sub-capacitor and second sub-capacitor based on physical split structure, and clocked dynamic comparator generates first comparison result and second comparison result based on first sub-capacitor and second sub-capacitor;Bypass window logic detection circuit generates mode control signal based on first comparison result and second comparison result, enters bypass operating mode based on mode control signal, or enters normal operating mode based on mode control signal.The highest significant bit capacitor of the capacitor array of DAC structure is split and the first sub-capacitor is reused with main comparator to realize bypass window detection, can skip part high bit capacitor switching when input signal changes little, reduce dynamic power consumption caused by capacitor array flip.