32 results about "Clock feedthrough" patented technology

The invention belongs to the field of integrated circuits, and particularly relates to a charge pump circuit for a phase-locked loop, a charge pump module, the phase-locked loop and a communication chip. The charge pump circuit adopts a source switch single-end topology, and a numerical control current source DAC with an adaptive compensation circuit and two rail-to-rail operational amplifiers are applied. According to the source electrode switch single-end topology, the switch time sequence is dynamically optimized through a three-state working mode, and the charge injection effect and clock feed-through interference are remarkably reduced; the numerical control current source realizes multi-stage high-precision programmable current output according to a control code, responds to the change of output voltage in real time by utilizing a self-adaptive compensation mechanism, and maintains the stability of charging and discharging current; the rail-to-rail operational amplifier eliminates the common-mode constraint in a full-swing input range by connecting an NMOS-PMOS differential pair structure in parallel. The charge pump circuit overcomes the defects of a charge pump circuit adopted in an existing phase-locked loop in the aspects of output swing, stability and the like, static power consumption can be reduced to the microampere level, and the advantages are obvious.

Photon or electron detectors may include polycrystalline silicon resistive gates with voltage gradients applied to reduce lag and improve operating speeds. The polycrystalline silicon resistive gates may be doped polycrystalline silicon which is heavily doped with donor atoms or acceptor atoms and ion-implanted with an electrically inactive species. The electrically inactive species may be implanted in a pattern to form multiple ion-implanted regions with different resistivities. The ion-implanted regions are formed in select patterns to control the resistivity of the polycrystalline silicon resistive gates and to modify the lateral electric field across the differentially-biased polycrystalline silicon resistive gate. The X-ray detectors may also include a circuit element with a current-mode differential connection to improve clock feedthrough and power dissipation characteristics.

The invention provides a driving circuit of a chopping switch circuit and electronic equipment, the driving circuit of the chopping switch circuit comprises a floating power supply generation circuit and a level shift circuit which are electrically connected with the chopping switch circuit, and the driving circuit provides port voltage bias for the chopping switch circuit through the floating power supply generation circuit. The floating power supply and the floating ground change along with the common-mode change of an input signal, so that the conduction impedance change and the threshold voltage change caused by the common-mode level change can be reduced; meanwhile, a power supply and a reference ground are provided for the level shift circuit, so that the level shift circuit can convert an originally constant high-amplitude clock signal into a clock signal changing along with the input common-mode level, and the amplitude of the clock signal can be kept at a constant and low value; therefore, low noise injection and clock feed-through can be realized under the condition that the conduction impedance and the threshold voltage are relatively stable, so that the precision and the stability of the circuit are improved, and the signal quality is improved.

The invention belongs to the technical field of gate voltage bootstrapped switches, and discloses a high-performance gate voltage bootstrapped switch for a Sigma-Delta ADC, a PMOS switch circuit is introduced into an NMOS type gate voltage bootstrapped switch circuit to form a complementary switch, and the complementary switch is used for counteracting an output error caused by a clock feed-through effect of an NMOS switch and the PMOS switch; virtual tubes are added to the input and output ends of the NMOS switch and the PMOS switch by using an inverter chain and are used for absorbing channel charges of the switch tubes; the substrate potential of the NMOS switch and the substrate potential of the PMOS switch are connected into the switching circuit, so that the substrate potential of the switching tube is switched between GND and input voltage Vin, and on the premise that sampling / maintaining precision is guaranteed, interference of clock feed-through and charge injection in the switching tube on output signals is restrained, and the linearity of the grid voltage bootstrapped switch is improved.

The invention discloses a reading circuit, an image sensor, a chip and a control method, and relates to the field of integrated circuits. The readout circuit includes: a capacitive feedback transimpedance amplifier circuit; and the signal conversion circuit comprises a phase inverter, is arranged at the input end, used for receiving a reset signal, in the capacitance feedback transimpedance amplifier circuit, and reduces the first voltage value and / or improves the second voltage value by adjusting the internal source end voltage of the phase inverter. Wherein the first voltage value represents a voltage value of a high level in the reset signal, and the second voltage value represents a voltage value of a low level in the reset signal. Based on the circuit design, the signal conversion circuit is arranged at the input end of the reset signal to reduce the first voltage value and / or improve the second voltage value, namely, the voltage difference between the high level and the low voltage in the reset signal is reduced, the noise caused by clock feed-through and charge injection effect in the CTIA circuit is reduced, and the reliability of the CTIA circuit is improved. And the reset noise is further reduced.

The invention relates to the technical field of integrated circuits, and discloses a clock feed-through elimination circuit applied to a decision feedback equalizer, which comprises a latch and an amplifier, the latch comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, a first inverter, a second inverter, a third inverter and a fourth inverter, drain electrodes of the second and fourth transistors and the second capacitor are connected to a second node, a grid electrode of the first transistor and a second inverter input are connected with a first comparison signal, and a grid electrode of the second transistor and a first inverter input are connected with a second comparison signal; the amplifier comprises a first resistor, a second resistor, a fifth transistor, a sixth transistor and a first current source, the first resistor is connected with a drain electrode of the fifth transistor and outputs a first amplification signal, a grid electrode of the fifth transistor is connected with a first node, and the second resistor is connected with a drain electrode of the sixth transistor and outputs a second amplification signal; the grid electrode of the sixth transistor is connected to the second node, and the source electrode of the fifth transistor and the source electrode of the sixth transistor are connected to the first current source. According to the invention, the clock feed-through interference of the latch can be reduced.

Described is a high-speed digital-to-analog converter (DAC) with an interleaver and misalignment detector. The interleaver has a first pair of differential pair ports to receive a first data stream from a first sub-DAC and a second pair of differential pair ports to receive a second data stream from a second sub-DAC. Each of the first and second pair of differential pair ports are alternately selected or alternately selected identically clocked by a differential sampling frequency (FS) / 2 (FS / 2) frequency clock to generate output signals. A set of transmission wires combine certain output signals from the first pair of differential pair ports with certain output signals from the second pair of differential pair ports to generate a device output signal. A first transmission wire and a second transmission wire have a defined degree of crossover to reduce differential FS / 2 frequency clock feedthrough with minimal change on a device output signal.

A photon or electron detector may include a polysilicon resistive gate having a voltage gradient applied to reduce hysteresis and improve operating speed. The polysilicon resistive gate may be doped polysilicon heavily doped with donor atoms or acceptor atoms and ion implanted with non-electroactive species. The non-electroactive species may be implanted in a pattern to form a plurality of ion implantation regions having different electrical resistivity. The ion implantation region is formed in a selected pattern to control the resistivity of the polysilicon resistive gate and modify a lateral electric field across the differentially biased polysilicon resistive gate. The X-ray detector may also include circuit elements with current mode differential connections to improve clock feedthrough and power dissipation characteristics.

A clock tree synthesis method comprises obtaining information of a source node and information of N leaf nodes, N being a positive integer greater than 1, performing a Steiner tree algorithm according to the information of the source node and the information of the N leaf nodes to determine information of a set of branch nodes, and creating a clock feedthrough according to the information of the source node, the information of the N leaf nodes, and the information of the set of branch nodes.

The invention discloses a high-linearity grid voltage bootstrap switch capable of reducing a clock feed-through effect, which comprises a grid voltage bootstrap module, a charge pump boosting module, an MOS (Metal Oxide Semiconductor) sampling switch and a compensation circuit module, and is characterized in that the compensation circuit module is used for compensating an error of the MOS sampling switch caused by the clock feed-through effect. According to the invention, the compensation circuit module is added on the basis of a traditional grid voltage bootstrapped switch to counteract a nonlinear error generated by a clock feed-through effect, so that the nonlinear error is reduced. In addition, the structure of a traditional grid voltage bootstrap switch is not changed, and the overall work of the sampling system is not affected while the transistor overhead is saved.

Disclosed is a harmonic suppression circuit for tunneling magnetoresistance sensors, which restrains even-order harmonic distortion by means of a fully differential interface circuit topological structure, restrains the charge injection and clock feedthrough effect of transistors by means of a virtual geminate transistor parallel structure and reduces the on resistance by means of a complementary switch structure to effectively restrain harmonic distortion. The harmonic suppression circuit for tunneling magnetoresistance sensors has a high linearity and has a high reading accuracy when used for reading sensing data of tunneling magnetoresistance sensors.

The invention relates to a pseudo-differential lower polar plate sampling circuit and a sampling method, which are used for designing an ADC (Analog to Digital Converter) sampling capacitor circuit, matching with a specifically designed common-mode level generation circuit and efficiently realizing signal sampling through switching of different stages under the control of each switch, and have the characteristic of direct comparison after sampling of an upper polar plate of a sampling capacitor. The conversion rate same as that of upper pole plate sampling can be achieved, the defects of upper pole plate charge injection, clock feed-through and other traditional upper pole plate sampling can be overcome, and the SDNR and SFDR performance is improved; and aiming at a high-swing input signal, the sampling capacitor array can perform level shift on the input signal, so that the function of processing the high-swing signal by a low-voltage device is realized, and the conversion rate of the SAR is effectively improved.

The invention discloses a method for improving the frame rate of an image sensor and the image sensor, and relates to the technical field of image sensors. The core of the method is that before a transistor executes a starting action, a selection transistor in a pixel is turned off, a clamping circuit is started, and the voltage of a column output line is clamped to a preset voltage; and after the transistor executes the turn-off action and the clock feed-through disturbance effect period caused by the transistor is ended, the selection transistor is turned on and the clamping circuit is forbidden, so that the voltage of the column output line recovers to follow the voltage of the floating diffusion node. Through the time sequence control, the influence of clock feed-through on the voltage establishment process is effectively shielded, and the single analog-to-digital conversion time is shortened, so that the frame rate is improved.

This invention discloses a gate voltage bootstrap sampling switch circuit, PCB board, and controller, including a clock inverting unit, a bootstrap charging / discharging unit, a sampling switch unit, and an isolation unit. The input terminal of the clock inverting unit is connected to an external clock signal terminal. The output terminal of the clock inverting unit is connected to the enable terminals of the bootstrap charging / discharging unit and the isolation unit. The input terminal of the bootstrap charging / discharging unit is connected to an external power supply terminal VDD, and its output terminal is connected to the enable terminal of the sampling switch unit. The input terminal of the sampling switch unit is connected to an external input signal terminal, and its output terminal is connected to the sampling signal output terminal. The output terminal of the isolation unit is connected to the sampling switch unit. The bootstrap charging / discharging unit and the sampling switch unit achieve a constant gate-source voltage, reducing the dependence of the sampling switch's on-resistance on the input signal. The isolation unit ensures effective shutdown of the signal path during non-sampling phases and utilizes charge discharge to reduce charge injection and clock feedthrough effects generated during the switching on and off of the sampling switch.

The invention discloses a switched capacitor type common-mode feedback circuit, and relates to the field of common-mode feedback circuits, the switched capacitor type common-mode feedback circuit with higher linearity and lower power consumption is adopted to detect and correct an output common-mode level, and stable and accurate common-mode feedback voltage is output along with an effective clock; adverse effects caused by common charge injection and clock feed-through in the switched capacitor circuit are fully considered, and errors caused by clock feed-through and charge injection in the switched capacitor circuit structure are reduced by adopting a partially complementary switch structure; in addition, a virtual switch is adopted at a related position, channel residual charges caused by a clock are released, and the detection and calibration precision of the circuit is improved. According to the invention, the adverse influence of clock feed-through and charge injection on the existing circuit during the clock conversion period is reduced, so that the problem that the working frequency, clock frequency and dynamic range of the circuit are limited is solved to a certain extent.

The invention discloses a pulse latch flip-flop circuit with scanning, and the circuit comprises a data selection unit which is used for receiving a data input signal, a scanning input signal, and an enable signal, and selecting one signal from the data input signal and the scanning input signal as a first output signal in response to the enable signal; the pulse generation unit is used for receiving the clock signal and generating a pulse signal according to the clock signal, and the pulse signal is generated after the rising edge of the clock signal; the latch unit comprises a clock feed-through unit which is used for charging or discharging according to different signals of the input end and the output end of the latch unit, and the latch unit is used for receiving the first output signal and the pulse signal and latching the first output signal synchronously with the pulse signal; and generating and outputting a second output signal of the current period in response to the first output signal and a reverse signal of the second output signal of the previous period. The invention has the advantages of high speed, low time delay, low power consumption and high charging and discharging speed.

Voltage generators with relatively low clock feedthrough are disclosed. A voltage generator can include a charge pump with a first set of two switches arranged between two voltages, a second set of two switches arranged between one of the two voltages and an output node, and a fly capacitor connected to the first and second sets of two switches. The voltage generator can include a clock generation circuit to provide clock signals such that the two switches of the first set transition state and the two switches of the second set transition state at different times. In certain embodiments, the charge pump includes a p-type fly capacitor connected to an output node by way of an n-type transistor. In some embodiments, a level shifter can generate a level shifted clock signal for the charge pump and includes cross coupled transistors to receive a regulated voltage provided to the voltage generator.

A track and hold (TAH) system includes a complementary source follower circuit and a first TAH path. The complementary source follower circuit receives an input signal of the TAH system. The first TAH path includes a first TAH switch circuit, a first TAH output buffer circuit, and a first TAH clock-feedthrough cancellation circuit. The first TAH switch circuit is controlled by a first switch clock to sample a signal derived from an output signal of the complementary source follower circuit to obtain a first sampled signal. The first TAH output buffer circuit generates an output signal of the first TAH path according to the first sampled signal. The first TAH clock-feedthrough cancellation circuit applies clock-feedthrough cancellation to the first sampled signal according to the first switch clock.

The invention relates to the technical field of integrated circuits, in particular to a charge pump with low current mismatch and high output voltage swing, which comprises a current bias circuit used for copying bias current provided by a reference current source IREF and providing the copied bias current for a charging current source and a current absorber to provide accurate bias current; the charging current source is used for providing a charging path for a loop filter of a post-stage circuit; the current absorber is used for providing a discharge path for a loop filter of a post-stage circuit; and the charge pump core module is used for providing stable output voltage Vctrl for a loop filter of a post-stage circuit. According to the invention, the reverse jump voltage is used to reduce the influence of the clock feed-through effect on the output voltage; current mismatch can be effectively reduced; the output voltage swing is relatively high; and the operation speed of the charge pump circuit is greatly improved.

The application discloses a high-precision differential sample-and-hold circuit, which comprises a differential input voltage translation circuit, an auxiliary differential input buffer stage, auxiliary sample-and-hold switches SWX3 and SWX4, a differential gate voltage bootstrap sample-and-hold switch circuit and a high input impedance buffer output stage; when the circuit is in a sampling state, the sampling switches SW1 and SW2, the isolation switches SWX1 and SWX2, the auxiliary sample-and-hold switches SWX3 and SWX4 are all closed, and an input signal charges an anti-aliasing filter capacitor; when the circuit enters a holding state, the differential gate voltage bootstrap sample-and-hold switch circuit first turns off the sampling switches, and then the auxiliary sample-and-hold switches and the isolation switches are simultaneously turned off, so that the voltage signal at the end of the sampling state is held on the filter capacitor and is output to a subsequent stage through the buffer output stage; the circuit has high input impedance and can accept a higher signal source output impedance; the differential gate voltage bootstrap sample-and-hold circuit does not have significant clock feedthrough and charge injection errors, and the holding precision is ensured.

The application discloses a method for improving frame rate of an image sensor and the image sensor, and relates to the technical field of image sensors. The core of the method is that before a transistor performs an opening operation, a selection transistor in a pixel is turned off, a clamping circuit is enabled, and the voltage of a column output line is clamped to a preset voltage; after the transistor performs a turning-off operation and the clock feedthrough disturbance effect period caused by the turning-off operation ends, the selection transistor is turned on again and the clamping circuit is disabled, so that the voltage of the column output line is restored to follow the voltage of a floating diffusion node. Through the above timing control, the influence of clock feedthrough on the voltage establishment process is effectively shielded, the single analog-to-digital conversion time is shortened, and thus the frame rate is improved.

The application discloses a method for optimizing phase-locked loop spur by using additional random delay and a phase-locked loop. A long-time average fixed and short-time size random delay generator is added to a suitable position of the phase-locked loop, so that the fluctuation of a tuning voltage of the phase-locked loop due to non-ideal effects such as limited loop gain, system mismatch and clock feedthrough is randomized in time in each cycle, thereby distributing the energy originally gathered near the fluctuation frequency and harmonic frequencies to the full frequency spectrum, and effectively reducing the phase-locked loop spur. The application can simply and effectively reduce the phase-locked loop spur, and has universality in different architecture phase-locked loops.

The invention relates to a parallel switch capacitor integrator insensitive to parasitic capacitance, which realizes high-precision signal integration processing through four steps: firstly, controlling switch logic by using a two-phase non-overlapping clock, ensuring that control signals are not overlapped, and reducing charging injection and clock feed-through; secondly, a resistor in the continuous time integrator is replaced by a switched capacitor simulation resistor, and current flow is simulated by utilizing a periodic charging and discharging process so as to control charge quantity transfer; then, a virtual switch is introduced to compensate the influence of charge injection, and the circuit performance is improved. And finally, a shunt capacitor integrator circuit is constructed, and the shunt capacitor integrator circuit is insensitive to parasitic capacitance through a specific circuit layout, so that high precision and linearity of an integrator are ensured.

Photon or electron detectors may include polycrystalline silicon resistive gates with voltage gradients applied to reduce lag and improve operating speeds. The polycrystalline silicon resistive gates may be doped polycrystalline silicon which is heavily doped with donor atoms or acceptor atoms and ion-implanted with an electrically inactive species. The electrically inactive species may be implanted in a pattern to form multiple ion-implanted regions with different resistivities. The ion-implanted regions are formed in select patterns to control the resistivity of the polycrystalline silicon resistive gates and to modify the lateral electric field across the differentially-biased polycrystalline silicon resistive gate. The X-ray detectors may also include a circuit element with a current-mode differential connection to improve clock feedthrough and power dissipation characteristics.

The invention discloses a low-noise low-mismatch charge pump circuit applied to a frequency synthesizer circuit, and belongs to the field of integrated circuits. The charge pump core part suppresses current mismatch and reduces noise of an output signal through various optimized circuit structures; the rail-to-rail operational amplifier ensures the stability of an output direct current point of the charge pump circuit and is used for weakening the charge sharing effect of the charge pump; the transmission gate switch circuit part can reduce static and dynamic mismatch of upper and lower paths of current and weaken clock feed-through and charge injection effects of the charge pump circuit; and the Power-Down circuit part can cut off the input current when the circuit does not work, so that the power consumption of the system is reduced. By applying the charge pump technology, low output noise and low current mismatch of the charge pump circuit can be realized, the switching speed of the charge pump is improved, and the charge pump circuit has better interference resistance to power supply noise, so that the stray and noise performance of a frequency synthesizer is improved.

The application provides a bias sampling circuit, an image sensor, an isolation switch control method and a storage medium. The bias sampling circuit of the image sensor comprises a bias circuit, a current steering circuit and an isolation switch, the isolation switch is connected between the bias circuit and the current steering circuit, the isolation switch comprises a first isolation switch and a second isolation switch in parallel, the switch area of the first isolation switch is larger than that of the second isolation switch, and the turn-off time of the second isolation switch is later than that of the first isolation switch. The bias sampling circuit, the image sensor, the isolation switch control method and the storage medium provided by the application can not only ensure signal processing time efficiency, but also eliminate the influence of large-size switch charge injection and clock feedthrough through the use of the first isolation switch and the second isolation switch with different sizes and appropriate timing control.

The application discloses a charge pump phase-locked loop and relates to the field of phase-locked loops. In order to solve the problem that a traditional charge pump phase-locked loop cannot effectively reduce VCO output phase noise while ensuring normal operation of the charge pump, the application provides a charge pump phase-locked loop. The charge pump phase-locked loop is structured by a new type of analog phase detector + charge pump, and the difference between mirror currents of the charge pump generated by a reference clock signal and a feedback clock signal in different phase stages is used to charge / discharge a loop filter. The charge pump phase-locked loop can meet stable control of a control voltage of the loop filter, and CMOS switches are not needed. Therefore, the adverse effects caused by clock feedthrough and charge injection can be obviously reduced, and the normal operation of the charge pump phase-locked loop is not affected.

Photon or electron detectors may include polycrystalline silicon resistive gates with voltage gradients applied to reduce lag and improve operating speeds. The polycrystalline silicon resistive gates may be doped polycrystalline silicon which is heavily doped with donor atoms or acceptor atoms and ion-implanted with an electrically inactive species. The electrically inactive species may be implanted in a pattern to form multiple ion-implanted regions with different resistivities. The ion-implanted regions are formed in select patterns to control the resistivity of the polycrystalline silicon resistive gates and to modify the lateral electric field across the differentially-biased polycrystalline silicon resistive gate. The X-ray detectors may also include a circuit element with a current-mode differential connection to improve clock feedthrough and power dissipation characteristics.

The present invention discloses a switched capacitor type common mode feedback circuit, and relates to the field of common mode feedback circuits. The present invention uses a switched capacitor type common mode feedback circuit with higher linearity and lower power consumption to detect and correct the output common mode level, and outputs a stable and accurate common mode feedback voltage with an effective clock; and fully considers the adverse effects caused by common charge injection and clock feedthrough in switched capacitor circuits, adopts a partially complementary switch structure, and reduces the error caused by clock feedthrough and charge injection in the switched capacitor circuit structure; and adopts a virtual switch at a relevant position to release the residual charge in the channel caused by the clock, thereby improving the accuracy of circuit detection and calibration. The present invention reduces the adverse effects of clock feedthrough and charge injection on the existing circuit during clock conversion, thereby solving the problem of limiting the operating frequency, clock frequency and dynamic range of the circuit to a certain extent.