9 results about "Clock feedthrough" patented technology

Described is a high-speed digital-to-analog converter (DAC) with an interleaver and misalignment detector. The interleaver has a first pair of differential pair ports to receive a first data stream from a first sub-DAC and a second pair of differential pair ports to receive a second data stream from a second sub-DAC. Each of the first and second pair of differential pair ports are alternately selected or alternately selected identically clocked by a differential sampling frequency (FS) / 2 (FS / 2) frequency clock to generate output signals. A set of transmission wires combine certain output signals from the first pair of differential pair ports with certain output signals from the second pair of differential pair ports to generate a device output signal. A first transmission wire and a second transmission wire have a defined degree of crossover to reduce differential FS / 2 frequency clock feedthrough with minimal change on a device output signal.

The invention discloses a method for improving the frame rate of an image sensor and the image sensor, and relates to the technical field of image sensors. The core of the method is that before a transistor executes a starting action, a selection transistor in a pixel is turned off, a clamping circuit is started, and the voltage of a column output line is clamped to a preset voltage; and after the transistor executes the turn-off action and the clock feed-through disturbance effect period caused by the transistor is ended, the selection transistor is turned on and the clamping circuit is forbidden, so that the voltage of the column output line recovers to follow the voltage of the floating diffusion node. Through the time sequence control, the influence of clock feed-through on the voltage establishment process is effectively shielded, and the single analog-to-digital conversion time is shortened, so that the frame rate is improved.

This invention discloses a gate voltage bootstrap sampling switch circuit, PCB board, and controller, including a clock inverting unit, a bootstrap charging / discharging unit, a sampling switch unit, and an isolation unit. The input terminal of the clock inverting unit is connected to an external clock signal terminal. The output terminal of the clock inverting unit is connected to the enable terminals of the bootstrap charging / discharging unit and the isolation unit. The input terminal of the bootstrap charging / discharging unit is connected to an external power supply terminal VDD, and its output terminal is connected to the enable terminal of the sampling switch unit. The input terminal of the sampling switch unit is connected to an external input signal terminal, and its output terminal is connected to the sampling signal output terminal. The output terminal of the isolation unit is connected to the sampling switch unit. The bootstrap charging / discharging unit and the sampling switch unit achieve a constant gate-source voltage, reducing the dependence of the sampling switch's on-resistance on the input signal. The isolation unit ensures effective shutdown of the signal path during non-sampling phases and utilizes charge discharge to reduce charge injection and clock feedthrough effects generated during the switching on and off of the sampling switch.

The application discloses a high-precision differential sample-and-hold circuit, which comprises a differential input voltage translation circuit, an auxiliary differential input buffer stage, auxiliary sample-and-hold switches SWX3 and SWX4, a differential gate voltage bootstrap sample-and-hold switch circuit and a high input impedance buffer output stage; when the circuit is in a sampling state, the sampling switches SW1 and SW2, the isolation switches SWX1 and SWX2, the auxiliary sample-and-hold switches SWX3 and SWX4 are all closed, and an input signal charges an anti-aliasing filter capacitor; when the circuit enters a holding state, the differential gate voltage bootstrap sample-and-hold switch circuit first turns off the sampling switches, and then the auxiliary sample-and-hold switches and the isolation switches are simultaneously turned off, so that the voltage signal at the end of the sampling state is held on the filter capacitor and is output to a subsequent stage through the buffer output stage; the circuit has high input impedance and can accept a higher signal source output impedance; the differential gate voltage bootstrap sample-and-hold circuit does not have significant clock feedthrough and charge injection errors, and the holding precision is ensured.

The application discloses a method for improving frame rate of an image sensor and the image sensor, and relates to the technical field of image sensors. The core of the method is that before a transistor performs an opening operation, a selection transistor in a pixel is turned off, a clamping circuit is enabled, and the voltage of a column output line is clamped to a preset voltage; after the transistor performs a turning-off operation and the clock feedthrough disturbance effect period caused by the turning-off operation ends, the selection transistor is turned on again and the clamping circuit is disabled, so that the voltage of the column output line is restored to follow the voltage of a floating diffusion node. Through the above timing control, the influence of clock feedthrough on the voltage establishment process is effectively shielded, the single analog-to-digital conversion time is shortened, and thus the frame rate is improved.

The application discloses a method for optimizing phase-locked loop spur by using additional random delay and a phase-locked loop. A long-time average fixed and short-time size random delay generator is added to a suitable position of the phase-locked loop, so that the fluctuation of a tuning voltage of the phase-locked loop due to non-ideal effects such as limited loop gain, system mismatch and clock feedthrough is randomized in time in each cycle, thereby distributing the energy originally gathered near the fluctuation frequency and harmonic frequencies to the full frequency spectrum, and effectively reducing the phase-locked loop spur. The application can simply and effectively reduce the phase-locked loop spur, and has universality in different architecture phase-locked loops.

Photon or electron detectors may include polycrystalline silicon resistive gates with voltage gradients applied to reduce lag and improve operating speeds. The polycrystalline silicon resistive gates may be doped polycrystalline silicon which is heavily doped with donor atoms or acceptor atoms and ion-implanted with an electrically inactive species. The electrically inactive species may be implanted in a pattern to form multiple ion-implanted regions with different resistivities. The ion-implanted regions are formed in select patterns to control the resistivity of the polycrystalline silicon resistive gates and to modify the lateral electric field across the differentially-biased polycrystalline silicon resistive gate. The X-ray detectors may also include a circuit element with a current-mode differential connection to improve clock feedthrough and power dissipation characteristics.

The application discloses a charge pump phase-locked loop and relates to the field of phase-locked loops. In order to solve the problem that a traditional charge pump phase-locked loop cannot effectively reduce VCO output phase noise while ensuring normal operation of the charge pump, the application provides a charge pump phase-locked loop. The charge pump phase-locked loop is structured by a new type of analog phase detector + charge pump, and the difference between mirror currents of the charge pump generated by a reference clock signal and a feedback clock signal in different phase stages is used to charge / discharge a loop filter. The charge pump phase-locked loop can meet stable control of a control voltage of the loop filter, and CMOS switches are not needed. Therefore, the adverse effects caused by clock feedthrough and charge injection can be obviously reduced, and the normal operation of the charge pump phase-locked loop is not affected.