78results about How to "Improve output swing" patented technology

The invention relates to the technical field of design of complementary metal oxide semiconductor transistor (CMOS) operational amplifiers and in particular discloses a two-stage fully-differential low-noise low-offset chopping operational amplifier, which comprises choppers S1, S2 and S3 and a two-stage folded cascade operational amplifier, wherein the chopper S1 modulates an input signal to a chopping frequency; the two-stage folded cascade operational amplifier amplifies the signal which is modulated by the chopper S1; the chopper S2 demodulates the signal to a base band; and the chopper S3 is used for dynamically switching a differential pair tube of a current source in the amplifier, so that the current mismatching of the current source and an offset voltage of the amplifier are further reduced. An output offset voltage and an equivalent input noise of the operational amplifier are effectively reduced, output amplitude is improved, a capacitor of an output end and operational amplification output impedance form a low-pass filter, an additional low-pass filter is not required to be designed, and the two-stage fully-differential low-noise low-offset chopping operational amplifier is quite applicable to a sensor detection circuit.

A CMOS active pixel sensor (APS) imager cell is provided on a silicon-on-insulator (SOI) substrate. The APS imager cell is made from a SOI substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A pixel sensor cell including a photodiode is formed in the Si top layer of the SOI substrate. A pixel transistor set is formed in the SOI top Si layer and connected to the pixel sensor cell. The pixel transistor set includes at least one p-channel MOS (PMOS) transistor and at least one n-channel MOS (NMOS) transistor. In the case of a three-transistor (3T) pixel transistor set, the selected transistor is NMOS, the reset transistor is PMOS, and the source follower may be either NMOS or PMOS.

The invention discloses a sampling holding circuit applied to a high-speed high-precision circuit. The sampling holding circuit comprises a full-differential type operational amplifier, two sampling capacitors Cs, two sampling switches S1 and five selective switches and a low-pass filter circuit formed by a resistor R1 and a capacitor C1. The full-differential type operational amplifier is a gain enhancement folding cascade full-differential type operational amplifier, a sampling switch S1 is a grid voltage bootstrap switch, connected structures of the positive end and the negative end of the full-differential type operational amplifier are completely same, and a signal input end passes through the low-pass filter circuit to be connected with a lower pole plate of the sampling capacitors Cs through the sampling switches S1. A selective switch S3 is connected with the lower pole plate of the sampling capacitors Cs and the output end of the full-differential type operational amplifier. An upper pole plate of the sampling capacitors Cs is connected with the input end of the full-differential type operational amplifier, a selective switch S4 is connected with upper pole plates of the two sampling capacitors Cs, and a selective switch S2 is connected with the input end and the output end of the full-differential type operational amplifier. The sampling holding circuit can achieve sampling holding of the input signals in the high-speed high-precision circuit.

The invention discloses a simulation reference level buffer for a pipelined analog-digital converter. Output levels of a sub-analog-digital converter of the pipelined analog-digital converter include a high simulation reference level, an intermediate simulation reference level and a low simulation reference level, and the simulation reference level buffer comprises three buffer bodies which are used for providing buffering for the three simulation reference levels respectively. Each buffer body is composed of a folded-cascode amplifier and a source follower, one input end of the folded-cascode amplifier is connected with the corresponding simulation reference level, an output end of the folded-cascode amplifier is connected to an input end of the source follower, and an output end of the source follower is fed back to the other input end of the folded-cascode amplifier. The capacity for driving switch of the three simulation reference levels of the sub-analog-digital converter of the pipelined analog-digital converter can be improved while voltages of the three simulation reference levels are kept unchanged fundamentally.

The invention discloses an analog signal link circuit for a high-frame frequency reading-out integrated circuit system for collecting and processing weak signals of a short wave infrared detector and belongs to the technical field of integrated circuit design. The analog signal link circuit is characterized in that a reading-out circuit adopts an analog signal link structure. The analog signal link circuit has the concrete scheme that a current source loaded CTIA (capacitance trans-impedance amplifier) structure input stage in a cascade structure is adopted in a unit structure, a CDS (correlated double sampling) module and a charge amplifying module are arranged in a row public structure, and a public output stage adopts a complementary output stage. The CDS structure is integrated in the analog signal link, the serious low-frequency noise of a reading-out circuit of the infrared detector is filtered out, and the technical support is provided for the short wave infrared detector in applications of high resolution ratio and the like.

The invention discloses a narrowband switching millimeter wave voltage-controlled oscillator with a wide tuning range, and the narrowband switching millimeter wave voltage-controlled oscillator comprises a negative resistance unit which provides energy for maintaining oscillation for a resonant cavity, and a main oscillation circuit which employs an improved pi-type differential circuit structureand is used for achieving the oscillation and improving the quality factor of a resonant circuit; the filter capacitor and the tail current source MOS tube form a low-pass filter, so that the phase noise of the oscillator is reduced; the narrowband switching circuit comprises four basic LC VCOs. The output buffer circuit connects the four narrow-band VCOs in a common-drain manner, outputs the selected narrow-band VCO, and provides driving for subsequent circuits. According to the invention, based on the 65nm CMOS process design, good noise performance is realized.

An embodiment of the invention discloses a high-rate high-swing-amplitude driver circuit suitable for a silicon photo-modulator. The driver circuit is connected with a driver pre-stage circuit and a modulator load respectively and comprises at least one output circuit, each output circuit comprises a first phase inverter, a first voltage bias module, a second phase inverter, a second voltage bias module and an inductor, an input end of each first phase inverter is connected with an output end of the driver pre-stage circuit while an output end of the same is connected with an input end of the corresponding first voltage bias module, an output end of each first voltage bias module is connected with an input end of the corresponding second phase inverter, an output end of each second phase inverter is connected with an input end of the corresponding second voltage bias module, an output end of each second voltage bias module is connected with an input end of the corresponding inductor, and an output end of each inductor is connected with an input end of the modulator load. Through the driver circuit formed by circuit connection, high rate is guaranteed while output swing amplitude of a driver is increased.

The invention discloses a comparator and a D-class audio power amplifier comprising the comparator; the comparator comprises an input circuit used for receiving a differential signal and generating an amplified output signal, a delay adjusting circuit used for setting a delay window and adjusting the output signal of the input circuit, and an output circuit used for receiving the output signal of the input circuit and generating an output signal with wide amplitude. The comparator and the D-class audio power amplifier provide the comparator which can work normally in a wide voltage range from a power voltage to a ground voltage; with the adjustment of the delay adjusting circuit, the delay window can be set precisely, thereby suppressing noise well; and the output circuit can response quickly and is characterized by large output swing amplitude.

The invention relates to a high-gain large-broadband three-level operational amplifier applicable to a pipelined analogdigital converter. The operational amplifier comprises a first-level amplification module 201, a second-level amplification module 202, a third-level amplification module 203, a first compensation module 204, a second compensation module 205, a first loading capacitor CL1 and a second loading capacitor CL2, wherein the second-level amplification module 202 comprises a first amplification unit 2021 and a second amplification unit 2022. According to the high-gain large-broadbandthree-level operational amplifier applicable to the pipelined analogdigital converter, a current offset technology is adopted, on one hand, the gain of a first-level amplifier can be increased, on the other hand, common-mode feedback circuits can be reduced, and the area and power dissipation are reduced; meanwhile, a current mirror circuit is adopted, on one hand, the gain of the circuit can beincreased, on the other hand, transconductance of a second-level amplifier is positive, and a simple five-pipe total-differential operational amplifier is adopted as a third-level amplifier, and the output oscillation amplitude can be increased.

The invention discloses a push-push injection-locking-type frequency multiplier circuit. The circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOStransistor and an LC circuit or a transformer. The drain of the first NMOS transistor is connected with the drain of the second NMOS transistor. The source of the first NMOS transistor is connected with the source of the second NMOS transistor, and the common source end is grounded. The gate of the first NMOS transistor and the gate of the second NMOS transistor are connected with a pair of differential input signals. A cross-coupled pair transistor is formed by the third NMOS transistor and the fourth NMOS transistor. The gate of the third NMOS transistor is connected with the drain of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected with the drain of the third NMOS transistor. The source of the third NMOS transistor is connected with the source of the fourth NMOS transistor. The push-push injection-locking-type frequency multiplier circuit realized in the invention has large output power, and a requirement on input power is also not high, that is, the circuit has the advantages of low power consumption and high efficiency as compared with the prior art.

The invention relates to a fully-differential amplifier. The fully-differential amplifier comprises first and second complementary differential input pairs, and further comprises a positive feedback system; the positive feedback system is connected with the first and second complementary differential input pairs, and used for providing positive feedback to the first complementary differential input pair and the second complementary differential input pair; the positive feedback system comprises a third complementary differential input pair; the third complementary differential input pair comprises a first PMOS transistor and a second PMOS transistor; the grids of the first PMOS transistor and the second PMOS transistor are separately connected with the output ends of the first complementary differential input pair and the second complementary differential input pair; and the drains of the first PMOS transistor and the second PMOS transistor are separately connected with the output ends of the second complementary differential input pair and the first complementary differential input pair. On the basis of the fully-differential amplifier, the invention further provides a residual gain circuit adopting a related level shift method. The fully-differential amplifier disclosed by the invention has the advantages of being low in power consumption, rapid in speed, high in conversion rate and simple in circuit structure; and, with the help of the related level shift technology, the high-speed and high-precision residual gain circuit can be realized.

The invention provides a switched capacitor common mode feedback structure, and belongs to the technical field of analog integrated circuits. The switched capacitor common mode feedback structure is applicable to a fully differential operational amplifier, and comprises an output level scaling switched capacitor module and a common mode level detection and amplification module, two input ends of the output level scaling switched capacitor module are connected with two output ends of the fully differential operational amplifier for scaling an output voltage of the fully differential operationalamplifier, so that the scaled voltage satisfies the input range of the common mode level detection and amplification module, an output end of the output level scaling switched capacitor module is connected with the input end of the common mode level detection and amplification module, the common mode level detection and amplification module detects the scaled voltage, and the output end of the common mode level detection and amplification module outputs a common mode feedback current source bias voltage to feed back a current source bias point of the fully differential operational amplifier,so that the output common mode level of the fully differential operational amplifier is stabilized at an ideal common mode level. The switched capacitor common mode feedback structure provided by theinvention not only has the advantages of higher speed and higher precision of the common mode feedback structure within a continuous time, but also has the advantages of large output amplitude and good linearity of the switched capacitor common mode feedback structure.

The invention relates to a control method for a low-power two-stage amplifier STT-RAM (spin transfer torque-random access memory) reading circuit. The low-power STT-RAM reading circuit is provided and comprises a control circuit, a parallel magnetic tunnel junction, an open-loop amplifier, a control logic circuit, a first phase inverter, a first D trigger, a second D trigger and a clock output module; the low-power STT-RAM reading circuit is controlled to enter a working or standby state through the control circuit, so that data stored in the parallel magnetic tunnel junction is read. A tree-type reading scheme is adopted, so that the reading speed is relatively high; the control circuit is introduced and the power consumption is generated only when the reading circuit enters the working state, so that the power consumption of the reading circuit is reduced.

The invention relates to a low-power-consumption readout circuit based on a folding comparator and a control method. The readout circuit comprises a folding cascade comparator, and a control circuit, a parallel magnetic tunnel junction, a control logic circuit and a phase inverter which are connected with the folding cascade comparator, wherein the control circuit is connected with the parallel magnetic tunnel junction; the phase inverter is further connected with the a first D trigger and a second D trigger; the readout circuit further comprises a time output module; the first clock signal output terminal and the second clock signal output terminal of the time output module are respectively connected with the clock control input terminals of the first D trigger and the second D trigger. The readout circuit can effectively improve the readout speed, reduces the power consumption of operating circuit during stand-by time by adding the control circuit, increases the output range and gain, and improves the reliability of the whole readout circuit when the readout circuit is butted with a digital system.

The invention discloses an operational amplifier for a pipeline analog to digital converter. The operational amplifier comprises a first main operational amplifier and a second main operational amplifier; the first main operational amplifier comprises a first common source common gate P type transistor pair, a second common source common gate P type transistor pair, a first common source common gate N type transistor pair and a first common source N type transistor pair, which are connected in sequence, and the source electrode of the first common source N type transistor pair is connected with a first tail current N type transistor; the second main operational amplifier comprises a third common source common gate P type transistor pair and a second common source N type transistor pair, which are connected in sequence, and the source electrode of the second common source N type transistor pair is connected with a second tail current N type transistor, wherein the drain electrode of thefirst common source common gate P type transistor pair is connected with the drain electrode of the third common source common gate P type transistor pair through a compensation capacitor. Compared with the prior art, the operational amplifier can greatly improve the gain and the precision of the operational amplifier in the case of low voltage.

A delay cell architecture is provided herein with improved noise performance and increased output swing, while consuming less power and area than conventional delay cell architectures. In one embodiment, the delay cell described herein may include a pair of input transistors, a pair of cross-coupled transistors, a pair of current source transistors, at least one swing limiting transistor and an RC filter. The at least one swing limiting transistor is coupled between the output nodes of the delay cell for controlling the output swing and keeping the current source transistors in saturation. Phase-induced jitter is reduced by connecting the RC filter directly to the mutually-coupled source terminals of the current source transistors. Deterministic jitter is reduced by using a relatively large resistor and relatively small capacitor within the RC filter design. Such a design reduces the amount of area consumed by the delay cell without sacrificing noise performance. Current consumption is reduced by requiring only one bias voltage to be supplied to the delay cell.

The invention discloses a ring oscillator. The ring oscillator comprises an N-stage pseudo CMOS bootstrap inverter, wherein the pseudo CMOS bootstrap inverter is composed of a first transistor, a second transistor, a third transistor, a fourth transistor and a bootstrap capacitor, and includes four ports: a non-inverting input port, an inverting input port, a first output port and a second output port; the first transistor and the second transistor form a second inverter, and the third transistor and the fourth transistor form a first inverter; and due to the output voltage of the second inverter, the pseudo CMOS bootstrap inverter can turn off a pull-up tube of the first inverter, so that the pseudo CMOS bootstrap inverter has lower power consumption, and the output swing is increased by adding the bootstrap capacitor. The ring oscillator provided by the invention can improve the normally open state of a pull-up tube of the second inverter via a new interconnecting way, so as to further reduce the power consumption of the second inverter, reduce the power consumption delay product of the ring oscillator, and reduce the full-swing output.

The invention discloses a radio frequency receiver module based on electric wave environment testing, and belongs to the technical field of radio frequency receivers. The radio frequency receiver module comprises a barrel body; an end cover is arranged at left and right sides of the barrel body respectively; an input port is arranged at a central position of the end cover on the left; an output end of an A/D converter is electrically connected to an input end of a first digital gainer; and an output end of the first digital gainer is respectively and electrically connected to output ends of a power statistic module and a baseband filter. The output swing can be increased, the output linearity is improved, the noise of signal transmission is reduced, the stability of the signal transmission is guaranteed, and the signal transmission efficiency is improved; and thus, the stability of a testing result can be improved, and the resting requirement under an electric wave environment is met; by air vents on the end covers, the air inside the barrel body can be circulated, so the heat dissipation performance is improved and the service life of the radio frequency receiver is improved; and a water absorption layer can absorb water vapor in the barrel body, so that the occurrence of an unexpected condition is avoided.

The invention discloses an annular voltage-controlled oscillator with a self-biased structure. The annular voltage-controlled oscillator comprises a self-biased unit and an oscillator core unit, wherein the self-biased unit comprises an input biasing circuit, an operational amplifier and a half-replica delay circuit, the oscillator core unit comprises a feedback oscillation loop formed by cascading multiple stages of differential delay circuits with the same structure, and the structure of the half-replica delay circuit is the same as that of a half-side circuit of the differential delay circuit. The input biasing circuit provides a reference voltage VREF for the operational amplifier, a constant biasing voltage irrelevant to the power supply voltage is established; the output frequency ischanged by adjusting the tail current of the differential delay circuit, so that the output common-mode level is equal to the reference voltage, the problems that the working frequency of the ring oscillator fluctuates greatly along with the voltage of the power supply and the common-mode level of the core output of the oscillator is changed are solved, and the inhibition capability of the voltage-controlled oscillator on the noise of the power supply and the stable output swing are improved.