Wide output swing CMOS imager

Abstract

A CMOS active pixel sensor (APS) imager cell is provided on a silicon-on-insulator (SOI) substrate. The APS imager cell is made from a SOI substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A pixel sensor cell including a photodiode is formed in the Si top layer of the SOI substrate. A pixel transistor set is formed in the SOI top Si layer and connected to the pixel sensor cell. The pixel transistor set includes at least one p-channel MOS (PMOS) transistor and at least one n-channel MOS (NMOS) transistor. In the case of a three-transistor (3T) pixel transistor set, the selected transistor is NMOS, the reset transistor is PMOS, and the source follower may be either NMOS or PMOS.

Description

RELATED APPLICATIONS [0001] This application is a Continuation-in-Part of a pending patent application entitled, A REAL-TIME CMOS IMAGER HAVING STACKED PHOTODIODES FABRICATED ON SOI WAFER, invented by Lee et al., Ser. No. 11 / 384,110, filed Mar. 17, 2006, Attorney Docket No. SLA8033, which is incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention generally relates complementary metal / oxide / semiconductor (CMOS) imaging sensors and, more particularly, to an imager pixel sensor cell made from a combination of n-channel MOS devices, p-channel MOS devices, and photodiodes on a silicon-on-insulator (SOI) substrate. [0004] 2. Description of the Related Art [0005]FIG. 1 is a schematic diagram depicting an active pixel sensor (APS) imager cell made with n-channel MOS (NMOS) transistors (prior art). The APS cell includes a reset transistor, source follower transistor, select transistor, and a photodiode. All three transistors in the ...

AI Technical Summary

Benefits of technology

[0015] The present invention describes an APS imager cell made from a Si-on-insulator (SOI) substrate, using PMOS reset and source follower transistors. The use of PMOS transistors increases the output swing, without increasing supply voltage VDD. Since the pixel transistors are fabricated on the Si layer of the SOI wafer, separate n-wells and p-wells are not needed. The isolation between the NMOS and PMOS transistors is accomplished with a trench etch in the top Si layer. As a result, the size of the improved voltage swing imager cell is similar to an APS imager cell made from all NMOS transistors.

Problems solved by technology

Thus, the active pixel sensor of the prior art has poor performance under low power supply conditions.

However, as mentioned above in the description of FIG. 1, an NMOS transistor with VDD on both the gate and drain can only reach a source voltage of VDD−VT, thereby decreasing the dynamic range of the pixel.

The use of such a voltage is detrimental to device operation, however, as the higher voltage can damage the transistor.

This is especially true with advanced IC technologies that use a very thin gate oxide thickness, which is more easily damaged when using a higher reset voltage.

However, even with this solution, the operating range is limited at the low-end by leakage current in the reset transistor.

That is, with a low VTN, the transistor is leaky when off, and the VDark voltage can drop with time (between resets).

However, if fabricated in bulk Si, this solution would require that the imager to be fabricated in adjacent p and n-wells, which would significantly increase the size of the imager.

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