58 results about "Cascode amplifier" patented technology

A current comparator includes: a first capacitor having a first end coupled to a first input signal; a second capacitor having a first end coupled to a second input signal; a first transistor having a control electrode coupled to the second end of the first capacitor; and a third transistor having a control electrode coupled to the second end of the second capacitor. The first current electrodes of the first and second transistors are coupled, and the second current electrodes of the first and second transistors are coupled to the first and second circuit nodes, respectively. A single-ended cascode amplifier has an input coupled to the second circuit node via a third capacitor. A set of auto-zero switches selectively shorts the control electrode of the first transistor and the second current electrode in response to an auto-zero control signal, and selectively shorts the control electrode of the second transistor and the second current electrode.

The embodiment of the invention provides a cascode amplifier, a power supply and a server. The cascode amplifier comprises a substrate, a GaN transistor and an S transistor. The substrate comprises a plate, a control pin, a first pole pin and a second pole pin. The GaN transistor is arranged on the plate, the GaN transistor comprises a first electrode, a second electrode and a control electrode, the GaN transistor comprises a first surface, the first surface deviates from the plate, the first electrode, the second electrode and the control electrode of the GaN transistor are arranged on the first surface, and the first electrode of the GaN transistor is connected to the first electrode pin. The S transistor comprises a first electrode, a second electrode and a control electrode; the first electrode of the S transistor is connected to the second electrode of the GaN transistor, and the second electrode of the S transistor is connected to the control electrode and the second electrode pin of the GaN transistor. The control electrode of the S transistor comprises a plurality of first connection points, and the control electrode of the S transistor is connected to the control pin through the plurality of first connection points.

The invention provides a ClassAB output stage control and compensation circuit, which relates to the technical field of analog integrated circuits and comprises a folded cascode amplifier module, a ClassAB output stage bias module, a ClassAB output stage control module and a ClassAB output stage compensation module. The folded cascode amplifier module is used for providing gain for a loop and ensuring the loop gain of a negative feedback system and the accuracy of output voltage; the ClassAB output stage bias module is used for generating bias reference voltage of an output power tube and providing a reference value of quiescent current; the ClassAB output stage control module generates grid voltage of an output power tube through a differential amplifier and controls static and dynamic current of the output power tube; and the ClassAB output stage compensation module is used for compensating the stability of the loop and ensuring the stability of the loop under the condition of large-range output current.

Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage comprising a first field effect transistor (FET) and a second FET in a stacked configuration. The cascode gate bias circuit may be further configured to adaptively convert the first signal into a bias signal for a gate of the first FET. The power amplifier stage may be configured to generate an amplified signal based on the intermediate output.

The invention discloses an operational amplifier for an operational amplifier sharing high-speed pipeline analog-to-digital converter. The operational amplifier comprises a first main operational amplifier, a second main operational amplifier and a self-adaptive biasing circuit, wherein the input end of the first main operational amplifier receives an input signal, and the output end of the first main operational amplifier is connected with the input end of the second main operational amplifier; the output end of the second main operational amplifier outputs an amplification signal and is connected with a Cascode node of the first main operational amplifier through a pair of compensation capacitors; the first main operational amplifier is a folded cascode amplifier, and the self-adaptive bias circuit provides direct current bias for a tail current source and a cascode tube of the first main operational amplifier. The operational amplifier provided by the invention has relatively high speed and precision.

The present invention discloses a broadband high-gain low-noise amplifier, comprising: an amplifier stage circuit, a buffer stage circuit, an output stage circuit, and a feedback circuit. The amplifier stage circuit sequentially generates an output signal through the buffer stage circuit and the output stage circuit. The amplifier stage circuit adopts a cascode resistor feedback amplifier structure, which includes a cascode amplifier, a field-effect transistor M1, and a feedback resistor Rf. The gate of the field-effect transistor M1 is used to connect to the input signal, the source of the field-effect transistor M1 is grounded, and the drain of the field-effect transistor M1 is connected to the cascode amplifier. The present invention can achieve broadband matching while meeting high gain and low noise coefficient, and simultaneously achieves input and output matching. The input and output do not require a matching network structure, are simple to use, and adopt a design without inductance components to reduce cost and chip area.

A cascode amplifier includes a first field-effect transistor with a gate coupled to a first radio frequency input corresponding to a first receive band, a second field-effect transistor with a gate coupled to a second radio frequency input corresponding to a second receive band, and a third field-effect transistor. A source of the third field-effect transistor is connected to a drain of the first field-effect transistor and to a drain of the second field-effect transistor. A first tunable resistor is connected in series between a supply node and the first radio frequency input. A second tunable resistor is connected between the supply node and the second radio frequency input. The first and second tunable resistors controllable to increase an input impedance of the radio frequency amplifier.

A power amplifier circuit includes a first transistor, a second transistor, and a biasing circuit. The first transistor has a base configured to receive a first signal. The second transistor has an emitter connected to a collector of the first transistor, and a collector configured to output a second signal. The biasing circuit is coupled to the first transistor and the second transistor. The biasing circuit is configured to provide a direct current (DC) voltage at the collector of the second transistor that is about twice a DC voltage at the collector of the first transistor. The biasing circuit is configured to provide an alternating current (AC) or radio frequency (RF) voltage at the collector of the second transistor that is about twice an AC or RF voltage at the collector of the first transistor.

In the present invention, a high-frequency signal is input into a first transistor. A plurality of second transistors are cascode-connected to the first transistor. A bias circuit supplies a bias to each of the plurality of second transistors. A power supply wiring applies a voltage-variable power supply voltage to a cascode connection circuit including the first transistor and the plurality of second transistors. The bias circuit includes at least one voltage regulator, and supplies a bias voltage, which is generated on the basis of the voltage of the power supply wiring and the voltage of a voltage control node of which the voltage is controlled by the voltage regulator, to at least one of the plurality of second transistors.

The present invention discloses a bias method, device and bias circuit for a cascode amplifier. The bias method includes: obtaining a first minimum saturation drain-source voltage corresponding to the drain-source voltage of an input transistor in the cascode amplifier, and a second minimum saturation drain-source voltage corresponding to the drain-source voltage of the cascode transistor; setting the gate bias voltage of the cascode transistor according to the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, so that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage. According to the values of the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, the present invention sets the gate bias voltage of the cascode transistor, so that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage, thereby enabling the cascode amplifier to obtain stable gain.

The application discloses a microwave wideband differential variable gain amplifier and relates to the technical field of electronic circuits.The amplifier comprises a differential structure variable gain amplification circuit, an additional phase shift phase offset numerical control bias circuit and a power consumption control bias circuit.The application is applicable to BiCMOS and other processes, the differential variable gain amplification circuit adopts a current steering type Cascode amplifier structure to realize gain adjustment, two control voltages which make the phase change trends opposite when the VGA gain is reduced (increased) are designed, and a phase compensation resistor is designed to realize the low additional phase shift characteristic of the VGA.The two control voltages are generated by the additional phase shift phase offset numerical control bias circuit, and a plurality of digital control bits are set to select a target gain state from the two control voltages to reduce the gain error of the VGA.

The invention relates to a spliced amplifier with dynamic matrix bias and a signal amplification method thereof. A cascode amplifier includes a cascode amplifier, a cascode amplifier, a dynamic matrix voltage generator, and a load. The common source amplifier includes a first metal oxide semiconductor transistor (MOST) of a first type to receive a first input signal and output a first current to a first drain node according to a substrate voltage applied to a substrate of the first MOST. The common-gate amplifier includes a second MOST of the first type for receiving the first current from the first drain node and outputting a second current to the second drain node according to the first gate voltage. The dynamic matrix voltage generator is configured to receive a first input signal and output a matrix voltage. The load is to establish a third drain voltage at the third drain node in response to a second current through the DC path between the second drain node and the third drain node.

A cascode amplifier includes a first common-source amplifier (CSA) having a first MOST (metal oxide semiconductor transistor) of a first type configured to receive a first input signal and output a first current to a first node; a first common-gate amplifier (CGA) having a second MOST of the first type and configured to receive the first current from the first node and output a second current to a second node in accordance with a first bias voltage; a first source-follower (SF) having a third MOST of a second type configured to receive a second input signal and output a first voltage at the first node; and a load configured to establish a third voltage at a third node in response to the second current through a DC (direct current) path between the second node and the third node.

A system includes a radio frequency (RF) receiver having a low noise trans-impedance amplifier (LNTA). The LNTA is configured to receive a single-ended RF voltage signal and convert the RF voltage signal to a differential current mode signal. The LNTA is configured for adjustable gain by controllable circuits.

A cascode amplifier including a first field-effect transistor with a gate coupled to a first radio frequency input, and a second field-effect transistor disposed between the first field-effect transistor and a radio frequency output. A source of the second field-effect transistor connected to a drain of the first field-effect transistor. A first neutralization circuit has a first tunable capacitor and is connected at one end to a drain of the first field-effect transistor. A feedback circuit includes a first tunable resistor and is connected in series between the supply node and the first radio frequency input. The first tunable capacitor and the first tunable resistor are controllable to increase an input impedance of the radio frequency amplifier.

Disclosed in the present invention is a two-stage cascaded high-gain amplifier based on adaptive biasing and cascode compensation. Said amplifier uses the basic structure of a two-stage cascaded amplifier, where a first stage uses an adaptively biased cascode floating inverting amplifier structure, which significantly improves the gain by means of cross-coupled biasing while obtaining a larger current to increase the bandwidth and slew rate, and eliminates the need for an external biasing circuit and an additional common-mode feedback circuit, and a second stage uses a current-source-biased inverting amplifier structure, which achieves a higher current efficiency by means of current reuse, and obtains a larger output swing. In addition, the present invention uses a cascode compensation circuit to eliminate the need for a nulling resistor required for Miller compensation, and offers overall advantages of high gain and high speed.

The invention discloses a multimode dual-frequency low-noise amplifier, chip and equipment, the amplifier adopts a three-stage cascade amplifier topological structure design, and the amplifier comprises a first-stage cascode amplifier, the input of the first-stage cascode amplifier adopts broadband input matching, and the output end of the first-stage cascode amplifier adopts an inductance switching module as a load; the inductance switching module is controlled to switch different inductance values through the bias voltage; a load of the second-stage cascode amplifier adopts an inductively coupled reconfigurable double-frequency load; frequency response switching of the reconfigurable double-frequency load is controlled through the bias voltage; a switch notch module is arranged between the third stage cascode amplifier and the cascode amplifier; and the working state of the switch notch module is controlled through the bias voltage. According to the invention, by controlling corresponding bias in the variable inductor, the reconfigurable dual-frequency load and the switch inductor-capacitor trap module, multi-mode dual-frequency switching is realized, namely switching among broadband, parallel and reconfigurable dual frequencies is realized. The method can be widely applied to the technical field of mobile communication.

The invention discloses an ultra-wideband low-noise-coefficient amplifier and communication equipment, the ultra-wideband low-noise-coefficient amplifier comprises a first-stage inverting amplifier, a second-stage cascode amplifier and a third-stage inverting amplifier which are connected in sequence, and the first-stage inverting amplifier adopts a Gm-boost resistance feedback structure. The second-stage cascode amplifier and the third-stage inverting amplifier are in cascade connection to achieve the working capacity of high gain and large bandwidth of the circuit, and meanwhile the third-stage inverting amplifier is connected with a signal output end. The ultra-wide-band low-noise ultra-wide-band antenna has the characteristics of ultra-wide bandwidth, low noise coefficient and high gain in a working frequency band.

The application provides a folded cascode amplifier, an integrated circuit, a chip and an electronic device. The folded cascode amplifier comprises a bias circuit configured to provide a bias current according to a bias voltage, a first input differential unit and a second input differential unit arranged symmetrically, a folded cascode unit, and a fifth group of current mirrors connected to the folded cascode unit. The folded cascode unit comprises a first group of cascode tubes and a second group of cascode tubes, and a first group of current mirrors to a fourth group of current mirrors. The first group of cascode tubes comprises a first output transistor and a first load current tube connected in series, the second group of cascode tubes comprises a second output transistor and a second load current tube connected in series, and the first group of current mirrors multiplexes the first load current tube, and the fourth group of current mirrors multiplexes the second load current tube. The folded cascode amplifier improves the transconductance, the slew rate, the conversion rate and the gain-bandwidth product through the proportional cooperation of the several groups of current mirrors.

Various methods and circuital arrangements for reducing a turn ON time of a cascode amplifier are presented. According to one aspect, a configurable switching arrangement coupled to a cascode transistor of the amplifier shorts a gate of the cascode transistor to a reference ground during an inactive mode of operation of the amplifier. During an active mode of operation of the amplifier, the configurable switching arrangement couples a gate capacitor to the gate of the cascode transistor that is pre-charged to a voltage that is higher than a gate biasing voltage to the cascode transistor, which ensures that cascode transistor turns ON much quicker than the traditional method of grounding the cap, hence provide a final current flow through the cascode amplifier in a shorter time by not limiting the turn ON time of the input transistor. The gate biasing voltage is coupled to the gate capacitor via a resistor. A relationship between the pre-charged voltage, and minimum saturation voltages and threshold voltages of the transistors of the cascode amplifier is also provided.

A power amplifier system is presented that includes a cascode amplifier circuit configured to amplify a radio frequency signal when powered by a supply voltage and biased by a cascode driving voltage, a supply source configured to provide the supply voltage, and a cascode driving circuit configured to generate the cascode driving voltage based on the supply voltage, the cascode driving circuit including a first stage configured to provide a DC voltage, and a second stage configured to generate the cascode driving voltage that is tracking a level of the supply voltage based on the DC voltage.

Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit (202) configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage (204) comprising a first field effect transistor (Mi) and a second field effect transistor (M2) in a stacked configuration. The cascode gate bias circuit (202) may be further configured to adaptively convert the first signal into a bias signal for a gate of the first field effect transistor (Mi).

The invention discloses an adjustable threshold comparator based on offset compensation, and belongs to the technical field of analog integrated circuits. Comprising a bias module, and the bias module is connected with a V2I type inherent imbalance generation module, a two-stage amplifier and an active clamping circuit. The bias module is used for providing bias for the whole circuit; the two-stage amplifier comprises a first-stage fully differential folding type cascode amplifier and a second-stage cascode amplifier; the V2I type inherent imbalance generation module comprises a secondary comparator composed of a bipolar transistor and a PMOS tube, and a resistor is connected between the positive input end and the negative input end of the secondary comparator and used for adjusting the overturning threshold value of the secondary comparator. By improving the voltage comparator circuit, the voltage comparator circuit has the characteristics of high gain and common-mode interference resistance, and meanwhile, the active clamping circuit is used for limiting the voltage change range of an intermediate node, so that a device is effectively prevented from entering deep saturation, and the working speed of the circuit is greatly improved.

A cascode amplifier circuit includes a first transistor connected in a common-source configuration, and a second transistor connected in a common-gate configuration. The first transistor includes a gate for receiving a radio frequency (RF) input signal. The second transistor includes a first source / drain for delivering an RF output signal of the cascode amplifier circuit, a second source / drain connected to a first source / drain of the first transistor, and a gate for receiving a portion of the RF input signal.

A cascode amplifier with stability compensation network for removing instabilities of the amplifier due to cascode gate inductance is presented. The stability compensation network is a LC resonator with a resonance that targets a frequency of instability of the cascode amplifier. At the frequency of instability, the LC resonator is a short. The LC resonator is coupled in parallel to the gate inductance and a corresponding gate capacitance. According to one aspect, the gate inductance is a parasitic inductance. According to another aspect, the gate inductance further includes a gain boosting gate inductance. The gate boosting inductance provides a gain boost at a frequency of operation of the cascode amplifier. According to one aspect, values of an inductor and / or capacitor of the LC resonator are iteratively derived based on an optimization routine with criteria that includes a magnitude of a k- or μ-factor.

This invention discloses a low-noise amplifier for suppressing switching glitches, belonging to the field of communication technology. It mainly consists of a bias circuit, an input matching circuit, a Cascode amplifier, an output matching circuit, an RF switch, a transmit / receive switching control network, and an output switch logic control network. During TDD transmit / receive switching, the amplifier generates glitches. By adding an RF switch at the amplifier output, this invention achieves suppression of amplifier switching glitches through timing control via transmit / receive switching control logic and RF switch control.

This utility model discloses a high-power, low-phase-noise cascaded amplifier, including a low-noise amplifier PA5 disposed at the input end and a high-power amplifier PA6 disposed at the final stage; a first attenuation unit is disposed between the low-noise amplifier PA5 and the input end, and a second attenuation unit is disposed between the low-noise amplifier PA5 and the high-power amplifier PA6, and a connection circuit corresponding to the attenuation unit is also included; this solution cascades the low-noise amplifier and the high-power amplifier to form a cascaded amplification link that satisfies both low phase-noise performance and high power performance, thereby achieving better performance indicators while meeting performance requirements.

This invention discloses an operational amplifier based on a cyclic folded cascode architecture, relating to the field of analog circuit technology, to address the problems of low energy efficiency in existing folded cascode amplifiers and limited energy efficiency improvement in cyclic folded cascode structures. It includes a differential input transistor, a current mirror, an adaptive bias circuit, and an output stage. The adaptive bias circuit is connected to the differential input transistor, and the current mirror is connected to both the differential input transistor and the output stage. The adaptive bias circuit includes a flip-flop voltage follower. The current mirror is used for current recycling and zero-point compensation, and the output stage is used to output amplified signals. The adaptive bias circuit includes a flip-flop voltage follower to improve the dynamic performance of the amplifier. Zero-point compensation can improve the phase margin of the circuit, further improving the gain-bandwidth product. Compared to traditional operational amplifiers, the operational amplifier of this invention can achieve higher bandwidth and higher energy efficiency with lower power consumption.

A method operates by receiving an input signal; transforming the input signal into a first transformed signal of a common-mode voltage equal to a first bias voltage; transforming the input signal into a second transformed signal of a common-mode voltage equal to a second bias voltage; detecting a peak of the first transformed signal and making the first bias voltage equal to a sum of a first DC (direct current) voltage and a first dynamic voltage; detecting a valley of the second transformed signal and making the second bias voltage equal to a sum of a second DC voltage and a second dynamic voltage; amplifying the first transformed signal into a first output signal across a first load using a N-type cascode amplifier; and amplifying the second transformed signal into a second output signal across a second load using a P-type cascode amplifier.

The application relates to a millimeter wave reconfigurable common-source common-gate amplifier and a reconfigurable method thereof, which comprises an input reconfigurable matching network, a common-source common-gate transistor and an output reconfigurable matching network. The millimeter wave reconfigurable common-source common-gate amplifier of the application realizes impedance and noise matching of different frequency bands by reconfiguring the capacitance value of the input matching network and the inductance value of the output matching network, and simultaneously combines a transformer coupling gain promotion structure to make different frequency bands have larger amplification gains. The millimeter wave reconfigurable common-source common-gate amplifier circuit structure and the reconfigurable method of the application are simple and suitable for use in a multi-frequency band millimeter wave transceiver system. A conventional millimeter wave amplifier works at a fixed frequency, which limits the application in a multi-frequency communication system.