43 results about "Cascode amplifier" patented technology

Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage comprising a first field effect transistor (FET) and a second FET in a stacked configuration. The cascode gate bias circuit may be further configured to adaptively convert the first signal into a bias signal for a gate of the first FET. The power amplifier stage may be configured to generate an amplified signal based on the intermediate output.

The invention discloses an operational amplifier for an operational amplifier sharing high-speed pipeline analog-to-digital converter. The operational amplifier comprises a first main operational amplifier, a second main operational amplifier and a self-adaptive biasing circuit, wherein the input end of the first main operational amplifier receives an input signal, and the output end of the first main operational amplifier is connected with the input end of the second main operational amplifier; the output end of the second main operational amplifier outputs an amplification signal and is connected with a Cascode node of the first main operational amplifier through a pair of compensation capacitors; the first main operational amplifier is a folded cascode amplifier, and the self-adaptive bias circuit provides direct current bias for a tail current source and a cascode tube of the first main operational amplifier. The operational amplifier provided by the invention has relatively high speed and precision.

The present invention discloses a broadband high-gain low-noise amplifier, comprising: an amplifier stage circuit, a buffer stage circuit, an output stage circuit, and a feedback circuit. The amplifier stage circuit sequentially generates an output signal through the buffer stage circuit and the output stage circuit. The amplifier stage circuit adopts a cascode resistor feedback amplifier structure, which includes a cascode amplifier, a field-effect transistor M1, and a feedback resistor Rf. The gate of the field-effect transistor M1 is used to connect to the input signal, the source of the field-effect transistor M1 is grounded, and the drain of the field-effect transistor M1 is connected to the cascode amplifier. The present invention can achieve broadband matching while meeting high gain and low noise coefficient, and simultaneously achieves input and output matching. The input and output do not require a matching network structure, are simple to use, and adopt a design without inductance components to reduce cost and chip area.

A cascode amplifier includes a first field-effect transistor with a gate coupled to a first radio frequency input corresponding to a first receive band, a second field-effect transistor with a gate coupled to a second radio frequency input corresponding to a second receive band, and a third field-effect transistor. A source of the third field-effect transistor is connected to a drain of the first field-effect transistor and to a drain of the second field-effect transistor. A first tunable resistor is connected in series between a supply node and the first radio frequency input. A second tunable resistor is connected between the supply node and the second radio frequency input. The first and second tunable resistors controllable to increase an input impedance of the radio frequency amplifier.

A power amplifier circuit includes a first transistor, a second transistor, and a biasing circuit. The first transistor has a base configured to receive a first signal. The second transistor has an emitter connected to a collector of the first transistor, and a collector configured to output a second signal. The biasing circuit is coupled to the first transistor and the second transistor. The biasing circuit is configured to provide a direct current (DC) voltage at the collector of the second transistor that is about twice a DC voltage at the collector of the first transistor. The biasing circuit is configured to provide an alternating current (AC) or radio frequency (RF) voltage at the collector of the second transistor that is about twice an AC or RF voltage at the collector of the first transistor.

In the present invention, a high-frequency signal is input into a first transistor. A plurality of second transistors are cascode-connected to the first transistor. A bias circuit supplies a bias to each of the plurality of second transistors. A power supply wiring applies a voltage-variable power supply voltage to a cascode connection circuit including the first transistor and the plurality of second transistors. The bias circuit includes at least one voltage regulator, and supplies a bias voltage, which is generated on the basis of the voltage of the power supply wiring and the voltage of a voltage control node of which the voltage is controlled by the voltage regulator, to at least one of the plurality of second transistors.

The application discloses a microwave wideband differential variable gain amplifier and relates to the technical field of electronic circuits.The amplifier comprises a differential structure variable gain amplification circuit, an additional phase shift phase offset numerical control bias circuit and a power consumption control bias circuit.The application is applicable to BiCMOS and other processes, the differential variable gain amplification circuit adopts a current steering type Cascode amplifier structure to realize gain adjustment, two control voltages which make the phase change trends opposite when the VGA gain is reduced (increased) are designed, and a phase compensation resistor is designed to realize the low additional phase shift characteristic of the VGA.The two control voltages are generated by the additional phase shift phase offset numerical control bias circuit, and a plurality of digital control bits are set to select a target gain state from the two control voltages to reduce the gain error of the VGA.

A cascode amplifier includes a first common-source amplifier (CSA) having a first MOST (metal oxide semiconductor transistor) of a first type configured to receive a first input signal and output a first current to a first node; a first common-gate amplifier (CGA) having a second MOST of the first type and configured to receive the first current from the first node and output a second current to a second node in accordance with a first bias voltage; a first source-follower (SF) having a third MOST of a second type configured to receive a second input signal and output a first voltage at the first node; and a load configured to establish a third voltage at a third node in response to the second current through a DC (direct current) path between the second node and the third node.

A system includes a radio frequency (RF) receiver having a low noise trans-impedance amplifier (LNTA). The LNTA is configured to receive a single-ended RF voltage signal and convert the RF voltage signal to a differential current mode signal. The LNTA is configured for adjustable gain by controllable circuits.

A cascode amplifier including a first field-effect transistor with a gate coupled to a first radio frequency input, and a second field-effect transistor disposed between the first field-effect transistor and a radio frequency output. A source of the second field-effect transistor connected to a drain of the first field-effect transistor. A first neutralization circuit has a first tunable capacitor and is connected at one end to a drain of the first field-effect transistor. A feedback circuit includes a first tunable resistor and is connected in series between the supply node and the first radio frequency input. The first tunable capacitor and the first tunable resistor are controllable to increase an input impedance of the radio frequency amplifier.

Disclosed in the present invention is a two-stage cascaded high-gain amplifier based on adaptive biasing and cascode compensation. Said amplifier uses the basic structure of a two-stage cascaded amplifier, where a first stage uses an adaptively biased cascode floating inverting amplifier structure, which significantly improves the gain by means of cross-coupled biasing while obtaining a larger current to increase the bandwidth and slew rate, and eliminates the need for an external biasing circuit and an additional common-mode feedback circuit, and a second stage uses a current-source-biased inverting amplifier structure, which achieves a higher current efficiency by means of current reuse, and obtains a larger output swing. In addition, the present invention uses a cascode compensation circuit to eliminate the need for a nulling resistor required for Miller compensation, and offers overall advantages of high gain and high speed.

The invention discloses a multimode dual-frequency low-noise amplifier, chip and equipment, the amplifier adopts a three-stage cascade amplifier topological structure design, and the amplifier comprises a first-stage cascode amplifier, the input of the first-stage cascode amplifier adopts broadband input matching, and the output end of the first-stage cascode amplifier adopts an inductance switching module as a load; the inductance switching module is controlled to switch different inductance values through the bias voltage; a load of the second-stage cascode amplifier adopts an inductively coupled reconfigurable double-frequency load; frequency response switching of the reconfigurable double-frequency load is controlled through the bias voltage; a switch notch module is arranged between the third stage cascode amplifier and the cascode amplifier; and the working state of the switch notch module is controlled through the bias voltage. According to the invention, by controlling corresponding bias in the variable inductor, the reconfigurable dual-frequency load and the switch inductor-capacitor trap module, multi-mode dual-frequency switching is realized, namely switching among broadband, parallel and reconfigurable dual frequencies is realized. The method can be widely applied to the technical field of mobile communication.

The invention discloses an ultra-wideband low-noise-coefficient amplifier and communication equipment, the ultra-wideband low-noise-coefficient amplifier comprises a first-stage inverting amplifier, a second-stage cascode amplifier and a third-stage inverting amplifier which are connected in sequence, and the first-stage inverting amplifier adopts a Gm-boost resistance feedback structure. The second-stage cascode amplifier and the third-stage inverting amplifier are in cascade connection to achieve the working capacity of high gain and large bandwidth of the circuit, and meanwhile the third-stage inverting amplifier is connected with a signal output end. The ultra-wide-band low-noise ultra-wide-band antenna has the characteristics of ultra-wide bandwidth, low noise coefficient and high gain in a working frequency band.

The application provides a folded cascode amplifier, an integrated circuit, a chip and an electronic device. The folded cascode amplifier comprises a bias circuit configured to provide a bias current according to a bias voltage, a first input differential unit and a second input differential unit arranged symmetrically, a folded cascode unit, and a fifth group of current mirrors connected to the folded cascode unit. The folded cascode unit comprises a first group of cascode tubes and a second group of cascode tubes, and a first group of current mirrors to a fourth group of current mirrors. The first group of cascode tubes comprises a first output transistor and a first load current tube connected in series, the second group of cascode tubes comprises a second output transistor and a second load current tube connected in series, and the first group of current mirrors multiplexes the first load current tube, and the fourth group of current mirrors multiplexes the second load current tube. The folded cascode amplifier improves the transconductance, the slew rate, the conversion rate and the gain-bandwidth product through the proportional cooperation of the several groups of current mirrors.

Various methods and circuital arrangements for reducing a turn ON time of a cascode amplifier are presented. According to one aspect, a configurable switching arrangement coupled to a cascode transistor of the amplifier shorts a gate of the cascode transistor to a reference ground during an inactive mode of operation of the amplifier. During an active mode of operation of the amplifier, the configurable switching arrangement couples a gate capacitor to the gate of the cascode transistor that is pre-charged to a voltage that is higher than a gate biasing voltage to the cascode transistor, which ensures that cascode transistor turns ON much quicker than the traditional method of grounding the cap, hence provide a final current flow through the cascode amplifier in a shorter time by not limiting the turn ON time of the input transistor. The gate biasing voltage is coupled to the gate capacitor via a resistor. A relationship between the pre-charged voltage, and minimum saturation voltages and threshold voltages of the transistors of the cascode amplifier is also provided.

A power amplifier system is presented that includes a cascode amplifier circuit configured to amplify a radio frequency signal when powered by a supply voltage and biased by a cascode driving voltage, a supply source configured to provide the supply voltage, and a cascode driving circuit configured to generate the cascode driving voltage based on the supply voltage, the cascode driving circuit including a first stage configured to provide a DC voltage, and a second stage configured to generate the cascode driving voltage that is tracking a level of the supply voltage based on the DC voltage.

Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit (202) configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage (204) comprising a first field effect transistor (Mi) and a second field effect transistor (M2) in a stacked configuration. The cascode gate bias circuit (202) may be further configured to adaptively convert the first signal into a bias signal for a gate of the first field effect transistor (Mi).

A cascode amplifier circuit includes a first transistor connected in a common-source configuration, and a second transistor connected in a common-gate configuration. The first transistor includes a gate for receiving a radio frequency (RF) input signal. The second transistor includes a first source / drain for delivering an RF output signal of the cascode amplifier circuit, a second source / drain connected to a first source / drain of the first transistor, and a gate for receiving a portion of the RF input signal.

A cascode amplifier with stability compensation network for removing instabilities of the amplifier due to cascode gate inductance is presented. The stability compensation network is a LC resonator with a resonance that targets a frequency of instability of the cascode amplifier. At the frequency of instability, the LC resonator is a short. The LC resonator is coupled in parallel to the gate inductance and a corresponding gate capacitance. According to one aspect, the gate inductance is a parasitic inductance. According to another aspect, the gate inductance further includes a gain boosting gate inductance. The gate boosting inductance provides a gain boost at a frequency of operation of the cascode amplifier. According to one aspect, values of an inductor and / or capacitor of the LC resonator are iteratively derived based on an optimization routine with criteria that includes a magnitude of a k- or μ-factor.

This invention discloses a low-noise amplifier for suppressing switching glitches, belonging to the field of communication technology. It mainly consists of a bias circuit, an input matching circuit, a Cascode amplifier, an output matching circuit, an RF switch, a transmit / receive switching control network, and an output switch logic control network. During TDD transmit / receive switching, the amplifier generates glitches. By adding an RF switch at the amplifier output, this invention achieves suppression of amplifier switching glitches through timing control via transmit / receive switching control logic and RF switch control.

This utility model discloses a high-power, low-phase-noise cascaded amplifier, including a low-noise amplifier PA5 disposed at the input end and a high-power amplifier PA6 disposed at the final stage; a first attenuation unit is disposed between the low-noise amplifier PA5 and the input end, and a second attenuation unit is disposed between the low-noise amplifier PA5 and the high-power amplifier PA6, and a connection circuit corresponding to the attenuation unit is also included; this solution cascades the low-noise amplifier and the high-power amplifier to form a cascaded amplification link that satisfies both low phase-noise performance and high power performance, thereby achieving better performance indicators while meeting performance requirements.

This invention discloses an operational amplifier based on a cyclic folded cascode architecture, relating to the field of analog circuit technology, to address the problems of low energy efficiency in existing folded cascode amplifiers and limited energy efficiency improvement in cyclic folded cascode structures. It includes a differential input transistor, a current mirror, an adaptive bias circuit, and an output stage. The adaptive bias circuit is connected to the differential input transistor, and the current mirror is connected to both the differential input transistor and the output stage. The adaptive bias circuit includes a flip-flop voltage follower. The current mirror is used for current recycling and zero-point compensation, and the output stage is used to output amplified signals. The adaptive bias circuit includes a flip-flop voltage follower to improve the dynamic performance of the amplifier. Zero-point compensation can improve the phase margin of the circuit, further improving the gain-bandwidth product. Compared to traditional operational amplifiers, the operational amplifier of this invention can achieve higher bandwidth and higher energy efficiency with lower power consumption.

The application relates to a millimeter wave reconfigurable common-source common-gate amplifier and a reconfigurable method thereof, which comprises an input reconfigurable matching network, a common-source common-gate transistor and an output reconfigurable matching network. The millimeter wave reconfigurable common-source common-gate amplifier of the application realizes impedance and noise matching of different frequency bands by reconfiguring the capacitance value of the input matching network and the inductance value of the output matching network, and simultaneously combines a transformer coupling gain promotion structure to make different frequency bands have larger amplification gains. The millimeter wave reconfigurable common-source common-gate amplifier circuit structure and the reconfigurable method of the application are simple and suitable for use in a multi-frequency band millimeter wave transceiver system. A conventional millimeter wave amplifier works at a fixed frequency, which limits the application in a multi-frequency communication system.

The application discloses a chip design technical field and a method for improving power supply rejection capability of a linear voltage regulator, which comprises the following steps: step one, a double-loop feedback structure is used, the double-loop feedback structure comprises a high-speed loop and a low-speed loop, the high-speed loop is used for improving LDO transient response speed through a high-speed low-gain fast loop circuit, and the low-speed loop is used for improving overall loop gain through a low-speed high-gain slow loop circuit; step two, an auxiliary LDO is added at a node of LDO circuit structure power supply rejection; step three, a dynamic current impedance modulation technology is added; and step four, an NMOS transistor is used to make a folded cascode amplifier structure of an input pair to accurately amplify errors of reference voltage and feedback voltage, the method has extremely high power supply rejection ratio at low frequency, has good power supply rejection capability at high frequency, provides clean and ripple-free internal power supply for different load modules, and plays a good isolation role between power supply and noise sensitive modules.

The application discloses a two-stage cascade high-gain amplifier based on adaptive bias and common-source common-gate compensation, which adopts a basic structure of two-stage cascade amplifier, a first stage adopts a common-source common-gate floating inverting amplifier structure with adaptive bias, and through cross-coupling bias, the gain is obviously improved, meanwhile, larger current is obtained to improve bandwidth and swing rate, and external bias circuit and additional common-mode feedback circuit are saved; a second stage adopts an inverting amplifier structure with current source bias, higher current efficiency is realized through current multiplexing, and larger output swing is obtained. In addition, the application saves the zeroing resistor required by Miller compensation through a common-source common-gate compensation circuit, and has the advantages of high gain and high speed.

Various methods and circuital arrangements for reducing a turn ON time of a cascode amplifier are presented. According to one aspect, a configurable switching arrangement coupled to a cascode transistor of the amplifier shorts a gate of the cascode transistor to a reference ground during an inactive mode of operation of the amplifier. During an active mode of operation of the amplifier, the configurable switching arrangement couples a gate capacitor to the gate of the cascode transistor that is pre-charged to a voltage that is higher than a gate biasing voltage to the cascode transistor, which ensures that cascode transistor turns ON much quicker than the traditional method of grounding the cap, hence provide a final current flow through the cascode amplifier in a shorter time by not limiting the turn ON time of the input transistor. The gate biasing voltage is coupled to the gate capacitor via a resistor. A relationship between the pre-charged voltage, and minimum saturation voltages and threshold voltages of the transistors of the cascode amplifier is also provided.

A system includes a radio frequency (RF) receiver having a low noise trans-impedance amplifier (LNTA) (101). The LNTA is configured to receive a single-ended RF voltage signal and convert the RF voltage signal to a differential current mode signal. Further components in an RF signal chain are configured to receive the differential current mode signal. The LNTA includes cascode amplifiers (N1l, N2, N3, N4, P1, P2, P3, P4).

The invention provides a cloud and mist cooperative pressure monitoring method and device based on dynamic topology, and relates to the technical field of pressure monitoring, and the method comprises the steps: obtaining a cascade amplifier assembly; performing interference analysis on the real-time pressure monitoring signal output by the pressure monitoring instrument according to the self-adaptive encoder; the self-adaptive encoder analyzes the interference feature vector through a built-in self-adaptive encoding algorithm, and configures a primary amplifier and a secondary amplifier by using cooperative gain distribution coefficient encoding; wherein the first-stage amplifier analyzes the cooperative gain distribution coefficient to perform first-stage amplification on the real-time pressure monitoring signal to obtain a first-stage pressure amplification signal, the second-stage amplifier analyzes the cooperative gain distribution coefficient to perform second-stage amplification on the first-stage pressure amplification signal to obtain a second-stage pressure amplification signal, and the second-stage pressure amplification signal is sampled and stored. According to the invention, the technical problem of low pressure monitoring precision in the prior art can be solved, and the technical effect of improving the pressure monitoring precision is achieved.

The application discloses a single-stage differential cascode amplifier module applied to a W wave band, adopts a cascode structure and a differential amplification configuration, and comprises common-source transistors M1 and M2, common-gate transistors M3 and M4, common-gate transistor gate bias resistors R G , neutral capacitors C M1 , C M2 , transmission lines TL1, TL2, TL3 and TL4 and an interlayer matching inductor L. The application utilizes the characteristic that the midpoint of a symmetric point connection of a differential circuit is an AC ground, and the interlayer matching circuit does not need a grounding capacitor; the neutral capacitor structure is used to improve stability, the interlayer matching circuit is added at the same time, output power, efficiency and stability are improved, and the circuit structure is simple and convenient for system integration.

According to the present invention, a high-frequency signal is input to a first transistor. At least one second transistor is cascode-connected to the first transistor. A bias circuit supplies a bias to the second transistor. Power supply wiring applies a voltage-variable power supply voltage to a cascode connection circuit including the first transistor and the second transistor. The bias circuit includes a voltage regulator and a first resistor voltage divider circuit. The first resistor voltage divider circuit supplies a bias voltage, divided on the basis of the output voltage of a voltage control node of which the voltage is being controlled by the voltage regulator and the power supply voltage of the power supply wiring, to the second transistor.