31 results about "Cascode amplifier" patented technology

Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage comprising a first field effect transistor (FET) and a second FET in a stacked configuration. The cascode gate bias circuit may be further configured to adaptively convert the first signal into a bias signal for a gate of the first FET. The power amplifier stage may be configured to generate an amplified signal based on the intermediate output.

A power amplifier circuit includes a first transistor, a second transistor, and a biasing circuit. The first transistor has a base configured to receive a first signal. The second transistor has an emitter connected to a collector of the first transistor, and a collector configured to output a second signal. The biasing circuit is coupled to the first transistor and the second transistor. The biasing circuit is configured to provide a direct current (DC) voltage at the collector of the second transistor that is about twice a DC voltage at the collector of the first transistor. The biasing circuit is configured to provide an alternating current (AC) or radio frequency (RF) voltage at the collector of the second transistor that is about twice an AC or RF voltage at the collector of the first transistor.

In the present invention, a high-frequency signal is input into a first transistor. A plurality of second transistors are cascode-connected to the first transistor. A bias circuit supplies a bias to each of the plurality of second transistors. A power supply wiring applies a voltage-variable power supply voltage to a cascode connection circuit including the first transistor and the plurality of second transistors. The bias circuit includes at least one voltage regulator, and supplies a bias voltage, which is generated on the basis of the voltage of the power supply wiring and the voltage of a voltage control node of which the voltage is controlled by the voltage regulator, to at least one of the plurality of second transistors.

The application discloses a microwave wideband differential variable gain amplifier and relates to the technical field of electronic circuits.The amplifier comprises a differential structure variable gain amplification circuit, an additional phase shift phase offset numerical control bias circuit and a power consumption control bias circuit.The application is applicable to BiCMOS and other processes, the differential variable gain amplification circuit adopts a current steering type Cascode amplifier structure to realize gain adjustment, two control voltages which make the phase change trends opposite when the VGA gain is reduced (increased) are designed, and a phase compensation resistor is designed to realize the low additional phase shift characteristic of the VGA.The two control voltages are generated by the additional phase shift phase offset numerical control bias circuit, and a plurality of digital control bits are set to select a target gain state from the two control voltages to reduce the gain error of the VGA.

A cascode amplifier includes a first common-source amplifier (CSA) having a first MOST (metal oxide semiconductor transistor) of a first type configured to receive a first input signal and output a first current to a first node; a first common-gate amplifier (CGA) having a second MOST of the first type and configured to receive the first current from the first node and output a second current to a second node in accordance with a first bias voltage; a first source-follower (SF) having a third MOST of a second type configured to receive a second input signal and output a first voltage at the first node; and a load configured to establish a third voltage at a third node in response to the second current through a DC (direct current) path between the second node and the third node.

A system includes a radio frequency (RF) receiver having a low noise trans-impedance amplifier (LNTA). The LNTA is configured to receive a single-ended RF voltage signal and convert the RF voltage signal to a differential current mode signal. The LNTA is configured for adjustable gain by controllable circuits.

Disclosed in the present invention is a two-stage cascaded high-gain amplifier based on adaptive biasing and cascode compensation. Said amplifier uses the basic structure of a two-stage cascaded amplifier, where a first stage uses an adaptively biased cascode floating inverting amplifier structure, which significantly improves the gain by means of cross-coupled biasing while obtaining a larger current to increase the bandwidth and slew rate, and eliminates the need for an external biasing circuit and an additional common-mode feedback circuit, and a second stage uses a current-source-biased inverting amplifier structure, which achieves a higher current efficiency by means of current reuse, and obtains a larger output swing. In addition, the present invention uses a cascode compensation circuit to eliminate the need for a nulling resistor required for Miller compensation, and offers overall advantages of high gain and high speed.

The invention discloses an ultra-wideband low-noise-coefficient amplifier and communication equipment, the ultra-wideband low-noise-coefficient amplifier comprises a first-stage inverting amplifier, a second-stage cascode amplifier and a third-stage inverting amplifier which are connected in sequence, and the first-stage inverting amplifier adopts a Gm-boost resistance feedback structure. The second-stage cascode amplifier and the third-stage inverting amplifier are in cascade connection to achieve the working capacity of high gain and large bandwidth of the circuit, and meanwhile the third-stage inverting amplifier is connected with a signal output end. The ultra-wide-band low-noise ultra-wide-band antenna has the characteristics of ultra-wide bandwidth, low noise coefficient and high gain in a working frequency band.

The application provides a folded cascode amplifier, an integrated circuit, a chip and an electronic device. The folded cascode amplifier comprises a bias circuit configured to provide a bias current according to a bias voltage, a first input differential unit and a second input differential unit arranged symmetrically, a folded cascode unit, and a fifth group of current mirrors connected to the folded cascode unit. The folded cascode unit comprises a first group of cascode tubes and a second group of cascode tubes, and a first group of current mirrors to a fourth group of current mirrors. The first group of cascode tubes comprises a first output transistor and a first load current tube connected in series, the second group of cascode tubes comprises a second output transistor and a second load current tube connected in series, and the first group of current mirrors multiplexes the first load current tube, and the fourth group of current mirrors multiplexes the second load current tube. The folded cascode amplifier improves the transconductance, the slew rate, the conversion rate and the gain-bandwidth product through the proportional cooperation of the several groups of current mirrors.

Various methods and circuital arrangements for reducing a turn ON time of a cascode amplifier are presented. According to one aspect, a configurable switching arrangement coupled to a cascode transistor of the amplifier shorts a gate of the cascode transistor to a reference ground during an inactive mode of operation of the amplifier. During an active mode of operation of the amplifier, the configurable switching arrangement couples a gate capacitor to the gate of the cascode transistor that is pre-charged to a voltage that is higher than a gate biasing voltage to the cascode transistor, which ensures that cascode transistor turns ON much quicker than the traditional method of grounding the cap, hence provide a final current flow through the cascode amplifier in a shorter time by not limiting the turn ON time of the input transistor. The gate biasing voltage is coupled to the gate capacitor via a resistor. A relationship between the pre-charged voltage, and minimum saturation voltages and threshold voltages of the transistors of the cascode amplifier is also provided.

Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit (202) configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage (204) comprising a first field effect transistor (Mi) and a second field effect transistor (M2) in a stacked configuration. The cascode gate bias circuit (202) may be further configured to adaptively convert the first signal into a bias signal for a gate of the first field effect transistor (Mi).

A cascode amplifier circuit includes a first transistor connected in a common-source configuration, and a second transistor connected in a common-gate configuration. The first transistor includes a gate for receiving a radio frequency (RF) input signal. The second transistor includes a first source / drain for delivering an RF output signal of the cascode amplifier circuit, a second source / drain connected to a first source / drain of the first transistor, and a gate for receiving a portion of the RF input signal.

A cascode amplifier with stability compensation network for removing instabilities of the amplifier due to cascode gate inductance is presented. The stability compensation network is a LC resonator with a resonance that targets a frequency of instability of the cascode amplifier. At the frequency of instability, the LC resonator is a short. The LC resonator is coupled in parallel to the gate inductance and a corresponding gate capacitance. According to one aspect, the gate inductance is a parasitic inductance. According to another aspect, the gate inductance further includes a gain boosting gate inductance. The gate boosting inductance provides a gain boost at a frequency of operation of the cascode amplifier. According to one aspect, values of an inductor and / or capacitor of the LC resonator are iteratively derived based on an optimization routine with criteria that includes a magnitude of a k- or μ-factor.

This invention discloses a low-noise amplifier for suppressing switching glitches, belonging to the field of communication technology. It mainly consists of a bias circuit, an input matching circuit, a Cascode amplifier, an output matching circuit, an RF switch, a transmit / receive switching control network, and an output switch logic control network. During TDD transmit / receive switching, the amplifier generates glitches. By adding an RF switch at the amplifier output, this invention achieves suppression of amplifier switching glitches through timing control via transmit / receive switching control logic and RF switch control.

This utility model discloses a high-power, low-phase-noise cascaded amplifier, including a low-noise amplifier PA5 disposed at the input end and a high-power amplifier PA6 disposed at the final stage; a first attenuation unit is disposed between the low-noise amplifier PA5 and the input end, and a second attenuation unit is disposed between the low-noise amplifier PA5 and the high-power amplifier PA6, and a connection circuit corresponding to the attenuation unit is also included; this solution cascades the low-noise amplifier and the high-power amplifier to form a cascaded amplification link that satisfies both low phase-noise performance and high power performance, thereby achieving better performance indicators while meeting performance requirements.

This invention discloses an operational amplifier based on a cyclic folded cascode architecture, relating to the field of analog circuit technology, to address the problems of low energy efficiency in existing folded cascode amplifiers and limited energy efficiency improvement in cyclic folded cascode structures. It includes a differential input transistor, a current mirror, an adaptive bias circuit, and an output stage. The adaptive bias circuit is connected to the differential input transistor, and the current mirror is connected to both the differential input transistor and the output stage. The adaptive bias circuit includes a flip-flop voltage follower. The current mirror is used for current recycling and zero-point compensation, and the output stage is used to output amplified signals. The adaptive bias circuit includes a flip-flop voltage follower to improve the dynamic performance of the amplifier. Zero-point compensation can improve the phase margin of the circuit, further improving the gain-bandwidth product. Compared to traditional operational amplifiers, the operational amplifier of this invention can achieve higher bandwidth and higher energy efficiency with lower power consumption.

The application relates to a millimeter wave reconfigurable common-source common-gate amplifier and a reconfigurable method thereof, which comprises an input reconfigurable matching network, a common-source common-gate transistor and an output reconfigurable matching network. The millimeter wave reconfigurable common-source common-gate amplifier of the application realizes impedance and noise matching of different frequency bands by reconfiguring the capacitance value of the input matching network and the inductance value of the output matching network, and simultaneously combines a transformer coupling gain promotion structure to make different frequency bands have larger amplification gains. The millimeter wave reconfigurable common-source common-gate amplifier circuit structure and the reconfigurable method of the application are simple and suitable for use in a multi-frequency band millimeter wave transceiver system. A conventional millimeter wave amplifier works at a fixed frequency, which limits the application in a multi-frequency communication system.

The application discloses a chip design technical field and a method for improving power supply rejection capability of a linear voltage regulator, which comprises the following steps: step one, a double-loop feedback structure is used, the double-loop feedback structure comprises a high-speed loop and a low-speed loop, the high-speed loop is used for improving LDO transient response speed through a high-speed low-gain fast loop circuit, and the low-speed loop is used for improving overall loop gain through a low-speed high-gain slow loop circuit; step two, an auxiliary LDO is added at a node of LDO circuit structure power supply rejection; step three, a dynamic current impedance modulation technology is added; and step four, an NMOS transistor is used to make a folded cascode amplifier structure of an input pair to accurately amplify errors of reference voltage and feedback voltage, the method has extremely high power supply rejection ratio at low frequency, has good power supply rejection capability at high frequency, provides clean and ripple-free internal power supply for different load modules, and plays a good isolation role between power supply and noise sensitive modules.

A system includes a radio frequency (RF) receiver having a low noise trans-impedance amplifier (LNTA) (101). The LNTA is configured to receive a single-ended RF voltage signal and convert the RF voltage signal to a differential current mode signal. Further components in an RF signal chain are configured to receive the differential current mode signal. The LNTA includes cascode amplifiers (N1l, N2, N3, N4, P1, P2, P3, P4).

The application discloses a single-stage differential cascode amplifier module applied to a W wave band, adopts a cascode structure and a differential amplification configuration, and comprises common-source transistors M1 and M2, common-gate transistors M3 and M4, common-gate transistor gate bias resistors R G , neutral capacitors C M1 , C M2 , transmission lines TL1, TL2, TL3 and TL4 and an interlayer matching inductor L. The application utilizes the characteristic that the midpoint of a symmetric point connection of a differential circuit is an AC ground, and the interlayer matching circuit does not need a grounding capacitor; the neutral capacitor structure is used to improve stability, the interlayer matching circuit is added at the same time, output power, efficiency and stability are improved, and the circuit structure is simple and convenient for system integration.

According to the present invention, a high-frequency signal is input to a first transistor. At least one second transistor is cascode-connected to the first transistor. A bias circuit supplies a bias to the second transistor. Power supply wiring applies a voltage-variable power supply voltage to a cascode connection circuit including the first transistor and the second transistor. The bias circuit includes a voltage regulator and a first resistor voltage divider circuit. The first resistor voltage divider circuit supplies a bias voltage, divided on the basis of the output voltage of a voltage control node of which the voltage is being controlled by the voltage regulator and the power supply voltage of the power supply wiring, to the second transistor.

A system includes a radio frequency (RF) receiver having a low noise trans-impedance amplifier (LNTA). The LNTA is configured to receive a single-ended RF voltage signal and convert the RF voltage signal to a differential current mode signal. Further components in an RF signal chain are configured to receive the differential current mode signal. The LNTA includes cascode amplifiers.

Methods and apparatus for amplifying an input RF signal according to at least two gain states are described. According to one aspect, a multi-gain amplifier circuit including a low noise amplifier having a stack of transistors is used to amplify an input RF signal. When switching from a low gain state to a high gain state, the drain-source voltage of the output transistor of the stack is increased to affect the operating region of the output transistor, thereby reducing nonlinearity at the output of the amplifier. When switching from a high gain state to a low gain state, the drain-source voltage of the input transistor of the stack is increased to affect the operating region of the input transistor, thereby reducing nonlinearity at the output of the amplifier.

A system includes a radio frequency (RF) receiver having a low noise trans-impedance amplifier (LNTA) (400). The LNTA is configured to receive a single-ended RF voltage signal and convert the RF voltage signal to a differential current mode signal (OUTP, OUTM). The LNTA is configured for adjustable gain by controllable circuits (410, 420).

A tunable bandpass low-noise amplifier (LNA). The LNA includes a plurality of N-path filters and a plurality of cascode amplifiers. The cascode amplifiers are configured to amplify an input signal. Each N-path filter is coupled to a different one of the plurality of cascode amplifiers. The plurality of N-path filters are driven by local oscillator (LO) signals having different frequencies, and output nodes of the plurality of cascode amplifiers are coupled in parallel. The frequencies of the LO signals may be symmetrically spaced around a desired frequency (fLO). Each N-path filter may be coupled to a source of the common-gate device of the coupled cascode amplifier. The LO signals may be generated by a digital-to-time converter (DTC)-based frequency synthesizer. The frequencies of the LO signals supplied to the N-path filters may be adjusted to tune the bandwidth of the bandpass LNA.

This invention discloses a high-precision, wide-range two-stage Time-of-Flight (TOF) quantization circuit based on dual-slope complementarity. It employs a digital time-diode converter (TDC) for coarse time quantization and a slope-adaptive ramp circuit for fine time quantization. The dual-slope complementarity eliminates dead time while improving fine quantization accuracy. The ramp circuit is primarily composed of a capacitor-transimpedance amplifier, which utilizes a low-power, high-gain, and high-bandwidth improved cyclic reuse folded cascode amplifier structure. Slope adaptation uses error integral feedback technology to dynamically adjust the integral current based on the ramp final value error, achieving high-precision ramp slope calibration. Simultaneously, based on a closed-loop control system model, dynamic tracking compensation technology controls the loop gain, ensuring rapid convergence of the system across a wide measurement range. This invention overcomes the mutual constraint between time accuracy and time range in single-stage time-amplitude converters, achieving both higher time accuracy and a wider time range.

A cascode amplifier circuit includes a first transistor connected in a common-source configuration, and a second transistor connected in a common-gate configuration. The first transistor includes a gate for receiving a radio frequency (RF) input signal. The second transistor includes a first source / drain for delivering an RF output signal of the cascode amplifier circuit, a second source / drain connected to a first source / drain of the first transistor, and a gate for receiving a portion of the RF input signal.

This invention discloses a highly stable multi-stage low-noise amplifier architecture, belonging to the field of radio frequency integrated circuits. The architecture includes an input matching circuit, a first-stage Cascode amplifier circuit, an inter-stage matching circuit, a second-stage CS amplifier circuit, and an output matching circuit. The IN terminal of the input matching circuit receives the radio frequency signal and outputs it to the first common-source transistor M1 of the first-stage Cascode amplifier circuit. After being received by the gate of M1, the signal is output from its drain to the source of the second common-gate transistor M2. The signal is further amplified by M2 and output from its drain. It is then transmitted through the inter-stage matching circuit to the gate of the third common-source transistor M3 of the second-stage CS amplifier circuit. After two stages of amplification, the signal is output to the OUT terminal of the output matching circuit. M1 and M2 constitute the pre-stage common-source Cascode, and M3 is the post-stage common-source CS. Utilizing the extremely high reverse isolation of the pre-stage Cascode structure, i.e., the extremely low S12 parameter, the stability factor of the amplifier is significantly increased, enabling it to achieve unconditional stability across the entire frequency band.

A low noise amplifier includes a matching network for providing three-way coupling between an input node, a matching node, and a source node; a gate capacitor for providing AC coupling between the matching node and a gate node; a cascode amplifier for receiving a gate voltage at the gate node and outputting an output voltage at an output node in dependence on source degeneration at the source node; and a load network coupled to the output node. The matching network includes a shunt inductor, a series inductor, and a source degeneration inductor, the shunt inductor and the series inductor being stacked in a layout to have strong mutual coupling, the source degeneration inductor being disposed alongside the shunt inductor to have strong mutual coupling.

Methods and devices for amplifying an input RF signal according to at least two gain-states is described. According to one aspect, a multi gain amplifier circuit including a low noise amplifier having a stack of transistors is used for amplification of the input RF signal. When switching from a low gain-state to a high gain-state, the drain-to-source voltage of the output transistor of the stack is increased to affect region of operation of the output transistor, and thereby reduce non-linearity at the output of the amplifier. When switching from the high gain-state to the low gain-state, the drain-to-source voltage of the input transistor of the stack is increased to affect region of operation of the input transistor, and thereby reduce non-linearity at the output of the amplifier.