175results about "Multiple-port active networks" patented technology

An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

In one embodiment, a variable attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. In this manner, the control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the variable attenuation level of the variable attenuator.

An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a precisely controlled jitter pattern. The IC also measures periods between selected edges of the same or different ones of the DUT output signal, the DUT input signal, and a reference clock signal. Additionally, when the DUT input and output signals convey repetitive patterns, the IC can measure the voltage of the DUT input out output signal as selected points within the pattern by comparing it to an adjustable reference voltage. Processing circuits external to the IC program the IC to provide a specified amount of jitter to the test signal, control the measurements carried out by the measurement circuit, and process measurement data to determine the amount of jitter and other characteristics of the DUT output signal, and to calibrate the jitter in the DUT input signal.

The invention discloses a low-voltage difference voltage adjuster, belonging to the technical field of an electronic circuit. The low-voltage difference voltage adjuster comprises an error amplifier,an output amplifier and a frequency compensating circuit, wherein the error amplifier is a first-class folding cascode amplifier, the output amplifier is coupled with the error amplifier, receives control voltage and comprises a transistor and two divider resistors which are connected in series; the frequency compensating circuit is respectively coupled with the error amplifier and the output amplifier; and the frequency compensating circuit comprises a voltage-controlling current source circuit consisting of at least one transistor and at least one compensating capacitor coupled with the voltage-controlling current source circuit. The low-voltage difference voltage adjuster can solves the problems that the current voltage adjuster has larger compensating capacitance and can not carry outon-chip integration, can provide complete chip integration, has good voltage-suppression specific characteristic, reduce the number of the compensating capacitance and simplify the compensating circuit.

An object of the present invention is to lower the power dissipation of the image rejection mixer. The image rejection mixer includes distribution means supplied with local signals having a phase difference to distribute the local signals, first and second mixing means for mixing the distributed local signals and RF signals having a phase difference and outputting respective IF current signals, phase shift means for shifting in phase the respective mixed IF current signals so as to provide them with a relative phase difference of 90 degrees, and addition means for adding the respective phase shifted intermediate frequency current signals. The phase shift means shifts the phases of the respective IF current signals outputted from the first and second mixing means.

Aspects of the invention are related to a power semiconductor module applied to a multi-level converter circuit with three or more levels of voltage waveform. Aspects of the invention can include a first IGBT to which a diode is reverse parallel connected and a second IGBT having reverse blocking voltage whose emitter is connected to the emitter of the first IGBT are housed in one package, and each of the collector of the first IGBT, the collector of the second IGBT, and the connection points of the emitter of the first IGBT and the emitter of the second IGBT, is an external terminal.

Methods and apparatus are provided for programmable active inductance. The disclosed active inductor devices provide a tunable bandwidth with improved linearity. The disclosed active inductors have a variable frequency response corresponding to a variable inductance of the active inductor. The active inductor comprises a variable resistive circuit having an effective resistance, wherein the variable resistive circuit is comprised of at least one resistor that can be selectively bypassed in the variable resistive circuit to vary the effective resistive. The active inductor has an inductance that can be varied by varying the effective resistance.

An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.

A ruggedized analog front-end for interconnecting a network communicative device to a two-conductor based network operable in a train-like or other harsh environment. The front-end has a coupling circuit having first and second coupling channels providing isolation, impedance matching and energy transfer between a common mode filter circuit connectable to the two-conductor based network, and an amplifier and an attenuator respectively connectable to output and input of the network communicative device. The front-end has a power supply circuit for operative power supply of electronic components of the analog front-end.

The invention provides a VCO tuning curve compensation method. In the method, a negative resistance amplifier and an inductor are connected with both ends of a variable capacitor to form a parallel-connection structure, wherein the variable capacitor structure is a five-end AMOS capacitance network, and one end is a tuning curve compensation control end of the AMOS capacitance network, which changes the equivalent capacitance of the AMOS capacitance network by adjusting the DC voltage of a control end to obtain an approximate linearized change curve with respect to VCO output frequency and VCO control voltage, thereby realizing the VCO tuning curve compensation, improving the VCO stability and enabling a VCO circuit module to work in the area having a higher Q value. The invention also provides a VCO circuit module of a differential circuit structure formed by the method. The AMOS capacitance network comprises four AMOS varactors and one RC low-pass filter, wherein the four AMOS varactors are connected in series two by two and are symmetrically arranged, and the specific arrangement mode includes grid electrode series connection and substrate series connection. The VCO module performs voltage control on the AMOS varactors to change the oscillator frequency, and realizes the tuning curve compensation to enable the frequency tuning curve to be approximately linearized by changing the DC voltage of the compensation control end of the tuning curve, thereby realizing a larger frequency tuning range.

A digital signal gating method and apparatus of a preprocessor in a detection system wherein the detection system includes a central processing unit, a main memory and a receiver, whereby the apparatus and method bifurcate received digital signals, delays them along a first path while subjecting the digital signals along a second path to detection, delay, and thresholding and thereby generates a gating signal from the second path so that digital signals of the first path, including pre-threshold amplitudes, may be recorded.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesiser or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimised or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.

A PAM-4 data slicer includes first, second, and third comparators which provide first, second, and third thresholds, respectively. Each of the comparators has an offset. The first and third comparators have an offset generating arrangement at their outputs to provide the first and third comparator circuits with symmetrical offsets.

The invention discloses a network information analysis system, a weak signal, which is received by the regenerative receiving circuit and is in the network information transmission channel is treatedby the oscillator with transistor Q1 as the core to generate positive feedback, distortion compensation and primary amplification are performed, wherein an operational amplifier AR3 is used to feedback a primary amplified signal, the accuracy of distortion compensation is improved, at that same time, the signal meeting the post-stage circuit amplitude and frequency Requirement is output, and then enters the filter circuit, the noise interference is filtered by LC filter circuit, and other frequency signal interference is avoided by a bandpass filter, the signal enters a signal amplitude modulation circuit, and boosting second-order amplitude modulation is performed by a Boost circuit. When the output signal is abnormal, the thyristor is on, the signal enters the subtractor and outputs adifference signal, which is converted into a PWM signal to be coupled to the gate of the MOS transistor Q1 to control the on or off of the MOS transistor Q1, so as to control the accuracy of the second-order amplitude modulation. the problems that the signal in the network information transmission channel is distorted and the attenuation can not be effectively received by the terminal server canbe effectively solved.

An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves. Methods are provided for deskewing, equalizing, and boosting the differential signals in the embedded circuits that are mounted on a PCB.

The invention discloses an orthogonal signal frequency-multiplication phase-demodulation logic circuit with filter function, which mainly comprises a filter circuit module and a frequency-multiplication phase-demodulation circuit module, wherein the filter circuit module consists of eight D triggers, six phase inverters, four three-way AND gates and two JK triggers, an input end of the module receives two paths of orthogonal coding signals needing to be filtered respectively, and an output of the module has two paths of orthogonal signals filtered by the corresponding orthogonal coding signals; and the frequency-multiplication phase-demodulation circuit module consists of two XOR gates and five D triggers, an input end of the module receives two paths of signals needing phase demodulation respectively, and an output end of the module has phase-demodulation signals and fourfold frequency signals. The circuit combines filter and frequency-multiplication phase demodulation, is simple and reliable, can solve the problem of subsequent data processing error caused by signal interference, can be downloaded to a programmable chip such as CPLD or FPGA and the like, saves the space of a circuit board, is convenient to debug, and has reliable performance and utility value.

An interface circuit for a multi-differential embedded-clock channel for communicating data provides efficient utilization of the bandwidth of the channel. The interface circuit includes at least four first signals, at least four second signals, and a multi-differential amplifier. The multi-differential amplifier is coupled to the first and second signals. The multi-differential amplifier is adapted to generate the second signals by amplifying, for all combinations of two of the first signals, differential transitions between the two of the first signals. Each of a plurality of symbols of the data has a corresponding one of the differential transitions, and the differential transitions are serially communicated through the channel.

An inductor (1) includes an inductor (L11P) formed into the shape of a spiral on the outer circumference of an inductor region and having a start point connected to a terminal (N11P), an inductor (L12P) formed into the shape of a spiral on the inner circumference of the inductor region and having a start point at the end point of the inductor (L11P) and an end point connected to a terminal (N12P), and an inductor (L13P) formed into the shape of a spiral in a region sandwiched between the inductor (L11P) and the inductor (L12P) and having a start point at a node between the inductor (L11P) and the inductor (L12P) and an end point connected to a terminal (N13P).

Apparatus and methods disclosed herein implement a MOS resistor using the current channel of a MOS transistor. The MOS resistance R(DS) is dependent upon MOS transistor geometry and nominal gate voltage. MOS resistor terminal-to-gate voltages are averaged and applied to the MOS transistor gate such as to maintain the MOS resistor terminal voltage to current ratio, resulting in a substantially constant R(DS). R(DS) is also compensated for temperature and process variations by adjusting gate voltages via negative feedback methods.

A motor-drive circuit comprising: a current-passage-control circuit to perform ON / OFF control of a drive transistor connected to a motor coil to pass current through the motor coil; an overcurrent-state-detection circuit to detect whether current passing through the drive transistor is in an overcurrent state where the current exceeds a predetermined threshold value; a charging and discharging circuit to start charging a capacitor in response to detecting the overcurrent state by the overcurrent-state-detection circuit and subsequently discharge the capacitor in response to not detecting the overcurrent state; and an overcurrent-protection-control circuit to stop the ON / OFF control to turn off the drive transistor, for an elapsed charging period for a charging voltage of the capacitor at a predetermined voltage to exceed a threshold voltage, and determine whether to perform such an overcurrent-protection-control as to turn off the drive transistor by detection of the overcurrent state, after the charging period has elapsed.