38 results about "Frequency scaling" patented technology

Generation of a clock signal in a semiconductor integrated circuit (IC) is controlled using a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock signal. An Adaptive Frequency Scaling (AFS) circuit selectively adjusts a frequency of the clock signal, based on the output of the NMA indicating a change in a power supply voltage of the semiconductor IC.

The invention relates to the technical field of power systems, and provides a power carrier signal adaptive separation method, device and equipment and a medium, and the method comprises the steps: sampling a power carrier signal, and decomposing the power carrier signal to obtain a multi-mode signal; dividing an interference component in the multi-mode signal into a plurality of frequency modes, and dynamically adjusting each frequency mode based on the intra-mode parameters to obtain a decoupling mode; performing time shift compensation on disturbance in the decoupling mode based on the time compensation coefficient and the frequency scale adjustment coefficient to obtain a steady-state feature; and adaptively calculating the modal energy of each interference modal in the steady-state characteristics, and dynamically adjusting the contribution proportion of each interference modal to obtain a multi-modal mask so as to realize the adaptive separation of the power carrier signals. According to the invention, high-precision and robust separation and dynamic recovery of the power line carrier signal can be realized, and the method is suitable for a complex power line channel environment.

The embodiment of the invention provides a GPU computing power scheduling method and device, equipment, a medium and a program product, and relates to the technical field of computing power scheduling, and the method comprises the steps: dividing a computing unit and video memory resources of a GPU into a plurality of dynamically adjustable partitions according to a real-time task demand; calculating the priority weight of each task; preemptive scheduling and cooperative scheduling are combined, resource preemption is carried out on the first priority task, and time division multiplexing is carried out on the non-preemptive task; executing a dynamic voltage frequency adjustment (DVFS) and task merging strategy; through dynamic resource partitioning, dynamic priority evaluation, a hybrid scheduling strategy and an energy efficiency optimization algorithm, the GPU resource utilization rate and the energy efficiency ratio in a multi-task scene are remarkably improved, and meanwhile, energy consumption is reduced by combining a DVFS and a task merging strategy.

A frequency scaling method includes: in response to a first operation of a user, determining a frequency scaling frequency based on a first historical load sequence, where the first historical load sequence is a historical load sequence obtained by latest statistics collection in M historical load sequences, and M is a positive integer greater than or equal to 1; determining a frequency scaling period based on a first power consumption budget and the frequency scaling frequency, where the first power consumption budget is a power consumption budget that is obtained based on a temperature rise prediction and that corresponds to the first operation; and performing frequency scaling based on the frequency scaling period and the frequency scaling frequency.

The invention relates to the technical field of server hardware control, and discloses a server hardware acceleration control system based on noise temperature coupling. The system comprises a multi-source noise collector, a temperature control accelerator, a noise temperature coupling analyzer and an acceleration decision master control unit. The multi-source noise collector is deployed on the surface of the acceleration unit and an internal key node, and captures an electromagnetic radiation noise spectrum and a mechanical vibration noise waveform in real time; the temperature control accelerator integrates a thermoelectric refrigeration array and a voltage frequency modulation module, receives the temperature sensing data flow, and generates a pulse type refrigeration instruction and clock frequency correction according to a dynamic strategy; the coupling analyzer decomposes the multi-modal noise signal, extracts an energy feature vector, and constructs a coupling coefficient matrix; and after receiving the matrix operation, the acceleration decision-making unit outputs a frequency scaling factor and a voltage offset to the temperature control accelerator, feeds back a failure frequency band marking result update coefficient, and combines noise and temperature coupling characteristics to realize dynamic balance of hardware acceleration performance and stability.

This application discloses a scalar control method and apparatus for a brushless DC motor. The method includes: obtaining the motor operating frequency feedback value for the current control cycle based on t1(ZC) and t0(ZC); extracting the high-frequency component from the motor operating frequency feedback value for the current control cycle; obtaining the dynamic correction amount of the emission frequency to be superimposed; calculating the low-frequency component from the motor operating frequency feedback value for the current control cycle; generating the adaptive frequency scaling factor and the voltage correction amount for the current control cycle; and generating the motor drive control signal for the current control cycle. Compared to other scalar control schemes, this scheme can effectively improve the dynamic and steady-state performance of the brushless DC motor. Furthermore, this scheme has a smaller computational load and lower hardware implementation cost, requiring only at least one phase of motor output voltage as an analog comparator input for obtaining the zero-crossing signal of the motor back EMF voltage, without the need for analog sampling.

A circuit including a digital-to-analog converter (DAC) having a first terminal and a second terminal. The circuit also includes a first diode having a first terminal coupled to the second terminal of the DAC and having a second terminal coupled to the first terminal of the DAC. A comparator has a first terminal and a second terminal. A second diode has a first terminal coupled to the second terminal of the DAC and has a second terminal coupled to the second terminal of the comparator. A voltage-to-current converter (V2I) has a terminal. A resistor has a first terminal coupled to the second terminal of the second diode and has a second terminal coupled to the terminal of the V2I converter.

An integrated circuit comprises an oscillator which outputs a clock signal, a logic circuit portion, a detection circuit portion for detecting signal propagation delay relative to clock frequency, and a power supply which provides a configurable supply voltage. The detection circuit comprises a latch circuit portion, a delay circuit portion and a comparison circuit portion. The latch circuit portion outputs an alternating signal which changes state in dependence on the clock signal. This is received by the delay circuit portion which outputs first and second delayed signals respectively subject to first and second propagation delays each dependent on the supply voltage. The comparison circuit portion compares the alternating signal with the delayed signals, and outputs respective comparison signals if said signals indicate that the respective propagation delay is smaller than the clock signal period. A control circuit portion controls the supply voltage in dependence on the comparison signals.

Described herein, in one embodiment, are techniques to facilitate the partial powerdown of sub-components of an execution unit or other graphics processing resource based on the workload to be executed. In another embodiment, granular dynamic voltage and frequency scaling is enabled in which the voltage and frequency of groups of processing resources within a graphics processor can be separately scaled.

The invention belongs to the technical field of quantum frequency scale, dielectric constant and dielectric loss measurement, and particularly relates to a method and a device for measuring dielectric parameters of a loading medium of a miniaturized cavity bubble system. The method comprises the following steps: connecting a measurement device for loading dielectric parameters of a medium into a cavity bubble system in an atomic clock, and actually measuring the cavity bubble system by using the measurement device; the dielectric parameters comprise a dielectric constant and dielectric loss; the measuring device constructs a simulation model according to the state parameters of the cavity bubble system; parameter scanning analysis is carried out according to the simulation model, and relation images between dielectric parameters of an actual loading medium in the atomic clock and cavity bubble system simulation resonant frequency, an on-load Q value and a voltage standing wave ratio are obtained; and according to the actually measured resonant frequency, the load Q value and the voltage standing wave ratio, comparing the simulated resonant frequency and the simulated load Q value on the relation image, and determining the dielectric parameter value of the loading medium and the relation between the dielectric parameter value and the temperature.

The embodiment of the invention provides a resource allocation method and device, electronic equipment, a chip and a medium, and relates to the technical field of communication, and the method comprises the steps: determining a dynamic voltage and frequency scaling (DVFS) gear based on the number of resource elements (RE) in each time slot and a channel quality index (CQI) value; based on the DVFS gear, a number of enabled target cores is determined. According to the method disclosed by the invention, the number of the started target cores is determined according to the real-time RE number and the channel quality index corresponding to the received reference signal, so that dynamic power consumption control is realized, flexible power consumption adjustment is achieved, the energy consumption of the terminal is further saved, and the performance of the terminal is fully exerted.

A frequency adjustment method and apparatus, a processor, a chip, and a computer device are provided, and relate to the computer field. The method includes: A server obtains a load average and a PMU status in a frequency adjustment domain; and the server adjusts a frequency of a processor core in the frequency adjustment domain based on the load average and the PMU status, where the load average indicates an average of load values of all processor cores in the frequency adjustment domain when different processor cores execute tasks, and the PMU status indicates whether a running value of a PMU event reported by the processor core in the frequency adjustment domain reaches a threshold corresponding to the PMU event.

The invention relates to an AI intelligent calculation system power consumption dynamic power management and dynamic voltage and frequency regulation method, and belongs to the technical field of artificial intelligence. According to the AI intelligent computing system, an intelligent hybrid heterogeneous computing architecture of CPU + NPU + FPGA is adopted, computing power improvement of the low-power-consumption miniaturized intelligent computing system can be achieved, and the requirement for high computing power of an AI data processing function is met. The real-time state of the system is judged through a software algorithm, dynamic voltage and frequency regulation is performed on the CPU while dynamic power management of the intelligent computing system is realized, the problems of poor endurance and high energy consumption of an embedded unmanned intelligent platform in a severe environment can be solved, longer endurance of unmanned intelligent equipment in the severe environment can be ensured, and the service life of the unmanned intelligent equipment is prolonged. And the unmanned equipment is enabled to avoid infrared tracking.

The embodiment of the application provides a GPU computing power scheduling method, device, equipment, medium and program product, relates to the technical field of computing power scheduling, and the method comprises the following steps: according to real-time task demand, dividing the computing unit and the display memory resource of a GPU (Graphics Processing Unit) into a plurality of dynamically adjustable partitions; calculating the priority weight of each task; in combination with preemptive scheduling and cooperative scheduling, implementing resource preemption on a first priority task, and performing time-sharing multiplexing on a non-preempted task; performing dynamic voltage and frequency scaling (DVFS) and task merging strategy; through dynamic resource partitioning, dynamic priority evaluation, hybrid scheduling strategy and energy efficiency optimization algorithm, the GPU resource utilization and energy efficiency ratio in a multi-task scenario are significantly improved, and the energy consumption is reduced in combination with the DVFS and task merging strategy.

The invention relates to frequency scaling in a multi-tenant environment. Examples described herein relate to circuitry to: monitor availability data for a plurality of processes; determining one or more priority levels associated with at least one of the plurality of processes based on the policy parameters; and adjusting an operating frequency of the interface circuit based on the monitored availability data and the determined priority level of the process. In some examples, an operating frequency of an interface circuit is adjusted to prioritize an operating frequency requested by a high priority workload relative to an operating frequency requested by a low priority workload.

The application relates to the technical field of server hardware control, and discloses a server hardware acceleration control system based on noise temperature coupling. The system comprises a multi-source noise collector, a temperature control accelerator, a noise temperature coupling analyzer and an acceleration decision master control unit. The multi-source noise collector is arranged on the surface and internal key nodes of the acceleration unit, and can capture electromagnetic radiation noise spectrum and mechanical vibration noise waveform in real time; the temperature control accelerator integrates a thermoelectric refrigeration array and a voltage frequency modulation module, receives temperature sensing data flow, generates pulse type refrigeration instructions and clock frequency correction amount according to a dynamic strategy; the coupling analyzer decomposes multi-modal noise signals, extracts energy feature vectors and constructs a coupling coefficient matrix; the acceleration decision unit receives the matrix operation, outputs a frequency scaling factor and a voltage bias to the temperature control accelerator, feeds back a failure frequency band marker result update coefficient, and realizes dynamic balance of hardware acceleration performance and stability by fusing noise and temperature coupling characteristics.

The disclosed techniques provide a dynamic voltage and frequency scaling (DVFS) module and a domain residing in a core. The DVFS module includes a Voltage and Memory Assist Table (VMAT), including firmware-programmable registers that store target voltages that correspond to performance states and firmware-programmable registers that store memory assist values that correspond to the performance states. The domain includes memories. The DVFS module is configured to, during a current performance state: provide a core voltage to the domain, such that the core voltage is provided based on a target voltage among the target voltages that corresponds to the current performance state, and provide memory assist signaling to the memories, such that the memory assist signaling is provided based on the memory assist values that correspond to the current performance state. The DVFS module uses an efficient crawl to transition memory assist values from one performance state to another performance state.

The invention provides a digital atomic clock group management system and method, and the system comprises a plurality of atomic clocks, each atomic clock is connected with an ADC, each ADC is connected with the corresponding output end of the same multi-path power divider, each ADC is connected with a phase frequency detector, each phase frequency detector is connected with a stationary processor, and each stationary processor is connected with an analog-to-digital converter. And each stationary processor is connected with the corresponding input end of the same weighted averager. The output end of the weighted averager is connected with the loop filter, the loop filter is connected with the DAC controller, the DAC controller is connected with the DACs, each DAC is connected with the same adder circuit, and the adder circuit is connected with the VCXO. The clock group management unit comprises a scale algorithm module, a frequency modulation, phase modulation and drift modulation device, a loop parameter controller, a clock authorization manager, a working mode manager, a management mode selector, a clock group manager, a main clock selector, a channel controller, a weight controller and a phase difference and frequency difference demodulator. The system has the advantages of digitization, integration and expandability. The clock group management scheme and the time frequency scale algorithm are separated. According to the invention, high-precision generation of the satellite-borne VCXO voltage-controlled signal is realized.

A processing system dynamically scales at least one of voltage and frequency at a subset of a plurality of compute units of a graphics processing unit (GPU) based on characteristics of a kernel or workload to be executed at the subset. A system management unit for the processing system receives a compute unit mask, designating the subset of a plurality of compute units of a GPU to execute the kernel or workload, and workload characteristics indicating the compute-boundedness or memory bandwidth-boundedness of the kernel or workload from a central processing unit of the processing system. The system management unit determines a dynamic voltage and frequency scaling policy for the subset of the plurality of compute units of the GPU based on the compute unit mask and the workload characteristics.

Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.

An AI device may include a neural processing unit (NPU) that can execute neural networks. Agents may run on the AI device to ensure that the performance of the NPU meets quality of service (QoS) requirements in executions of neural networks. Jobs for executing one or more neural networks may be submitted by applications running on the AI device. The jobs may be grouped into queues based on their priorities. The jobs in the same queue may have the same priority. Different queues may be assigned to different agents. An agent may monitor the jobs in the queue that is assigned to the agent. The agent may also be subscribed to one or more other queues and receive activity data of the other queues. The agent may determine its residency on the NPU and use the residency and its QoS requirement to adjust the frequency of the NPU.

A method for memory management is described. The method includes detecting a mobile device entering a deep sleep state. The method also includes monitoring a lag counter for entering the deep sleep state with respect to a time period that the mobile device is in the deep sleep state to calculate a lag statistic threshold. The method further includes comparing the lag statistic threshold to a threshold configuration value. The method also includes adjusting memory management and / or frequency scaling of the mobile device when the lag statistic threshold is greater than the threshold configuration value.

The invention discloses an energy big data governance method and system based on digital twinning, and relates to the field of energy big data governance. The method comprises the following steps: collecting vibration data in real time, decomposing the vibration data into a plurality of frequency scale components, and removing background noise signals to obtain a plurality of de-noising frequency scale components; searching a scale component where the wear vibration frequency of the main bearing is located, extracting wear vibration energy characteristics of the wear vibration frequency from the scale component, and calculating the confidence of the wear vibration energy characteristics; when the confidence coefficient exceeds a main bearing wear degradation signal threshold value, wear vibration energy characteristics are enhanced; and fusing the plurality of de-noising frequency scale components and the processed wear enhancement characteristic signals into refined data, and transmitting the refined data to a digital twin platform, so that the digital twin platform performs adaptive adjustment on the main bearing of the wind driven generator. According to the invention, the early wear degradation signal of the main bearing of the wind driven generator can be effectively identified and enhanced, and misjudgment can be avoided to provide more accurate refined data for a digital twin platform to realize adaptive adjustment of the main bearing.

The invention discloses a high-performance processor power supply-oriented on-chip adaptive voltage and frequency adjusting device, which comprises a digital low dropout regulator (DLDO) with a time domain voltage comparator, and is characterized in that the time domain voltage comparator comprises three comparison registers and four delay units working in four voltage domains of Vcomp, Vhigh, Vref and Vlow respectively; and the three comparison registers respectively take the voltage level Dout of the output signal of the delay unit corresponding to the voltage domain Vcomp as a clock signal to sample the voltage levels of the output signals of the other delay units corresponding to the voltage domains Vhigh, Vref and Vlow so as to obtain three paths of voltage comparison results. The voltage comparator aims to solve the problems of stability, resolution, response speed and power consumption of a voltage comparator built by a traditional on-chip analog circuit, the voltage comparator can be synthesized, and the voltage comparator has the advantages of being high in robustness, high in resolution, high in response speed and low in power consumption.

An integrated circuit performing dynamic voltage and frequency scaling operations and a method of operating the same are provided. In one aspect, an integrated circuit includes: a plurality of intellectual property (IP) blocks; a memory configured to store a dynamic voltage and frequency scaling (DVFS) table in which operating voltages and operating frequencies are classified into a plurality of groups based on power characteristics of the plurality of IP blocks, where the operating voltages and operating frequencies correspond to utilization rates; and a DVFS controller configured to calculate a workload of each of the plurality of IP blocks, and control an operation frequency provided to each of the plurality of IP blocks based on the calculated workload and the DVFS table. The DVFS controller is configured to change an operating frequency of the IP block based on a power characteristic of the IP block of the plurality of IP blocks before the utilization reaches a threshold utilization.

The invention relates to the technical field of artificial intelligence chip control, in particular to a dynamic voltage frequency adjustment method and system for large language model reasoning. The method comprises the following steps: based on a detection signal related to a process of an inference task, identifying that a current working stage is a calculation-intensive Prefill stage or a memory bandwidth-intensive Decode stage; in response to the identified working stage, determining a target core frequency of a computing core corresponding to the current working stage and a target memory frequency of an off-chip memory interface; and according to a preset security protocol, controlling the frequencies and voltages of the computing core and the off-chip memory interface to be reconfigured according to a target core frequency and a target memory frequency. According to the dynamic voltage frequency adjustment method for large language model reasoning, power consumption redundancy of non-bottleneck resources in each stage of a large language model reasoning task is eliminated, and the calculation efficiency under unit energy consumption is greatly improved.

The application discloses a kind of on-chip adaptive voltage and frequency regulation device for high-performance processor power supply, including digital low dropout regulator DLDO with time domain voltage comparator, time domain voltage comparator includes three comparison registers and four delay units respectively working in Vcomp, Vhigh, Vref and Vlow four voltage domains, three comparison registers respectively with the voltage level Dout of the output signal of corresponding delay unit in voltage domain Vcomp as clock signal to sample the rest with the voltage level of the output signal of corresponding delay unit in voltage domain Vhigh, Vref and Vlow to obtain three-way voltage comparison result.The application aims to solve the problems of stability, resolution, response speed and power consumption of the voltage comparator built by traditional on-chip analog circuit, realize the synthesis of voltage comparator, with the advantages of strong robustness, high resolution, fast response speed and low power consumption.

The application relates to the technical field of master-slave data interaction, in particular to a cross-domain circuit and method supporting dynamic voltage or frequency adjustment, which comprises a host cross-domain circuit and a slave cross-domain circuit connected in sequence, the host cross-domain circuit is connected with an upstream host device, and the slave cross-domain circuit is connected with a downstream slave device; the host cross-domain circuit comprises a distribution control circuit, a first state controller, a first transaction blocking circuit and a sending module; the slave cross-domain circuit comprises a second state controller, a second transaction blocking circuit and a receiving module; the host cross-domain circuit and the slave cross-domain circuit are completely separated from different clock domains, reset domains and power domains, the circuit is more easily realized on a large-scale high-speed chip, and the system is convenient to control; the distribution control circuit, the first state controller and the first transaction blocking circuit work cooperatively to support an error response function and a blocking function of a protocol data transmission channel, and better safety of the system can be provided.

An electronic device according to embodiments of the present disclosure may comprise: a memory including one or more storage media for storing at least one instruction; and at least one processor including a processing circuit for executing the at least one instruction. The at least one processor may generate a short-term current profile of each unit block, generate a current profile library by summing the short-term current profiles for each bias condition of multiple unit blocks, generate a lookup table including information on a block combination according to at least one operation scenario, configure a long-term dynamic voltage and frequency scaling (DVFS) envelope on the basis of a worst transient interval, extract a short-term voltage profile for the long-term DVFS envelope from the current profile library on the basis of the lookup table, generate a long-term voltage profile by temporally overlapping the short-term voltage profiles on the basis of the long-term DVFS envelope, and output a power noise log on the basis of the long-term voltage profile.

Disclosed in the present invention is an energy efficiency optimization method based on dynamic voltage and frequency scaling (DVFS). The method comprises: in an offline state of a large language model, performing energy consumption tests on data of different load sizes, so as to obtain energy consumption performances under different DVFS configurations; on the basis of the obtained energy consumption performances under the different DVFS configurations, determining optimal DVFS configurations for each batch in a pre-filling stage and a decoding stage; and on the basis of the determined optimal DVFS configurations, scaling the core frequency and memory frequency of a graphics processing unit, so as to optimize the energy efficiency of inference performed by means of the large language model. The present invention provides a DVFS-based optimization solution, which respectively uses different DVFS configurations for a pre-filling stage and decoding stage of large model inference, thereby implementing the optimization of energy consumption.