74 results about "Frequency scaling" patented technology

Generation of a clock signal in a semiconductor integrated circuit (IC) is controlled using a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock signal. An Adaptive Frequency Scaling (AFS) circuit selectively adjusts a frequency of the clock signal, based on the output of the NMA indicating a change in a power supply voltage of the semiconductor IC.

The invention relates to the technical field of signal processing, and discloses a harbor equipment vibration signal processing method, which comprises the following steps: constructing a comprehensive function, and calculating a harbor equipment vibration signal based on the characteristics of a frequency scale, a second wavelet basis function and a threshold value; the concentration ratio of energy distribution, the calculation complexity of second wavelet basis functions under the frequency scale, the orthogonal value between the second wavelet basis functions under the frequency scale, the sparse value of second wavelet coefficients under the frequency scale and the signal-to-noise ratio of time domain signals reconstructed after threshold processing are comprehensively considered. The selection of the optimized frequency scale, the optimized second wavelet basis function and the optimized threshold is realized. The innovative method gets rid of the limitation of a single or optimized algorithm, fixed parameter setting or predefined rules in the prior art, and significantly improves the precision and robustness of low-frequency vibration signal processing.

The invention relates to the technical field of power systems, and provides a power carrier signal adaptive separation method, device and equipment and a medium, and the method comprises the steps: sampling a power carrier signal, and decomposing the power carrier signal to obtain a multi-mode signal; dividing an interference component in the multi-mode signal into a plurality of frequency modes, and dynamically adjusting each frequency mode based on the intra-mode parameters to obtain a decoupling mode; performing time shift compensation on disturbance in the decoupling mode based on the time compensation coefficient and the frequency scale adjustment coefficient to obtain a steady-state feature; and adaptively calculating the modal energy of each interference modal in the steady-state characteristics, and dynamically adjusting the contribution proportion of each interference modal to obtain a multi-modal mask so as to realize the adaptive separation of the power carrier signals. According to the invention, high-precision and robust separation and dynamic recovery of the power line carrier signal can be realized, and the method is suitable for a complex power line channel environment.

Disclosed is a system-on-chip. The system-on-chip including at least one operation processing unit configured to process an instruction based on a driving voltage and a clock signal, a temperature management module configured to estimate a cooling coefficient and a heating coefficient associated with the at least one operation processing unit based on a temperature measured at the at least one operation processing unit, and determine an operating frequency of the clock signal to be sent to the at least one operation processing unit based on the cooling coefficient and the heating coefficient, and a dynamic voltage and frequency scaling (DVFS) module configured to output a control signal for adjusting the driving voltage and the clock signal based on the operating frequency.

The invention discloses a fault feature extraction method and device based on the Internet of Things, electronic equipment and a storage medium. The method comprises the following steps: sampling vibration signals sent by a vibration sensor on industrial equipment to obtain a discrete signal sequence; dividing the discrete signal sequence into a plurality of time frame signals; performing component decomposition on the time frame signal to obtain a plurality of signal components; performing wavelet transformation on the signal component to obtain a wavelet coefficient; determining the frequency scale of the wavelet coefficient based on the similarity objective function; and performing calculation based on all the frequency scales to obtain a fault characteristic parameter corresponding to the time frame signal. According to the method, the bandwidth requirement of fault diagnosis in the Internet of Things environment can be remarkably reduced, so that the real-time performance of work such as fault diagnosis is remarkably improved while it is ensured that equipment faults are effectively recognized.

Methods, systems, and apparatus, including computational instructions / programs encoded on non-transitory computer-readable media, are disclosed to implement collaborative controls for dynamic voltage & frequency scaling ("DVFS") using an integrated circuit comprising a System-on-Chip ("SoC") and a memory device coupled to the SoC. The system identifies user-experience criteria for generating an output of a machine-learning ("ML") model implemented at the integrated circuit and determines a performance target required to satisfy the user-experience criteria. The system computes a first target operating point of a processing-in-memory ("PiM") block inside the memory device and a second target operating point of the host core. The system performs computations at the PiM block using the target operating point established based on the control signals. The first and second target operating points achieve the best energy efficiency, while the PiM block and the host core collaboratively satisfy the user-experience criteria.

The embodiment of the invention provides a GPU computing power scheduling method and device, equipment, a medium and a program product, and relates to the technical field of computing power scheduling, and the method comprises the steps: dividing a computing unit and video memory resources of a GPU into a plurality of dynamically adjustable partitions according to a real-time task demand; calculating the priority weight of each task; preemptive scheduling and cooperative scheduling are combined, resource preemption is carried out on the first priority task, and time division multiplexing is carried out on the non-preemptive task; executing a dynamic voltage frequency adjustment (DVFS) and task merging strategy; through dynamic resource partitioning, dynamic priority evaluation, a hybrid scheduling strategy and an energy efficiency optimization algorithm, the GPU resource utilization rate and the energy efficiency ratio in a multi-task scene are remarkably improved, and meanwhile, energy consumption is reduced by combining a DVFS and a task merging strategy.

The present techniques relate to mitigating droop conditions in systems having dynamic voltage and frequency scaling and there is disclosed a method of controlling a dynamic voltage and frequency scaling circuit, comprising: detecting a voltage droop relative to a current nominal voltage and frequency state; responsive to said current nominal voltage and frequency state having a corresponding fallback state in a safe operating zone of voltage and frequency, switching activity from a nominal source to a fallback source; and when a fallback to a safe operating zone is unavailable for said current nominal voltage and frequency state, pausing activity of the dynamic voltage and frequency scaling circuit.

A frequency scaling method includes: in response to a first operation of a user, determining a frequency scaling frequency based on a first historical load sequence, where the first historical load sequence is a historical load sequence obtained by latest statistics collection in M historical load sequences, and M is a positive integer greater than or equal to 1; determining a frequency scaling period based on a first power consumption budget and the frequency scaling frequency, where the first power consumption budget is a power consumption budget that is obtained based on a temperature rise prediction and that corresponds to the first operation; and performing frequency scaling based on the frequency scaling period and the frequency scaling frequency.

The invention relates to the technical field of server hardware control, and discloses a server hardware acceleration control system based on noise temperature coupling. The system comprises a multi-source noise collector, a temperature control accelerator, a noise temperature coupling analyzer and an acceleration decision master control unit. The multi-source noise collector is deployed on the surface of the acceleration unit and an internal key node, and captures an electromagnetic radiation noise spectrum and a mechanical vibration noise waveform in real time; the temperature control accelerator integrates a thermoelectric refrigeration array and a voltage frequency modulation module, receives the temperature sensing data flow, and generates a pulse type refrigeration instruction and clock frequency correction according to a dynamic strategy; the coupling analyzer decomposes the multi-modal noise signal, extracts an energy feature vector, and constructs a coupling coefficient matrix; and after receiving the matrix operation, the acceleration decision-making unit outputs a frequency scaling factor and a voltage offset to the temperature control accelerator, feeds back a failure frequency band marking result update coefficient, and combines noise and temperature coupling characteristics to realize dynamic balance of hardware acceleration performance and stability.

This application discloses a scalar control method and apparatus for a brushless DC motor. The method includes: obtaining the motor operating frequency feedback value for the current control cycle based on t1(ZC) and t0(ZC); extracting the high-frequency component from the motor operating frequency feedback value for the current control cycle; obtaining the dynamic correction amount of the emission frequency to be superimposed; calculating the low-frequency component from the motor operating frequency feedback value for the current control cycle; generating the adaptive frequency scaling factor and the voltage correction amount for the current control cycle; and generating the motor drive control signal for the current control cycle. Compared to other scalar control schemes, this scheme can effectively improve the dynamic and steady-state performance of the brushless DC motor. Furthermore, this scheme has a smaller computational load and lower hardware implementation cost, requiring only at least one phase of motor output voltage as an analog comparator input for obtaining the zero-crossing signal of the motor back EMF voltage, without the need for analog sampling.

The present techniques relate to mitigating droop conditions over state transitions in systems having dynamic voltage and frequency scaling and there is disclosed a method of controlling a dynamic voltage and frequency scaling circuit, comprising: initiating a transition from a first voltage and frequency state to a second voltage and frequency state; switching activity from a first nominal source to a first fallback source; retuning the first nominal source to become a second fallback source at the second voltage and frequency state; switching activity from the first fallback source to the second fallback source; retuning the first fallback source to become a second nominal source at the second voltage and frequency state; and switching activity from the second fallback source to the second nominal source.

The present invention relates to the technical field of signal processing, and discloses a vibration signal processing method for port equipment. By constructing a comprehensive function, based on the characteristics of the frequency scale, the second wavelet basis function, and the threshold, the concentration of energy distribution, the computational complexity of the second wavelet basis function under the frequency scale, the orthogonality value between the second wavelet basis functions under the frequency scale, the sparse value of the second wavelet coefficients under the frequency scale, and the signal-to-noise ratio of the reconstructed time-domain signal after threshold processing are comprehensively considered, realizing the selection of the optimized frequency scale, the optimized second wavelet basis function, and the optimized threshold. This innovative method gets rid of the limitations of single or optimized algorithms, fixed parameter settings, or predefined rules in the prior art, and significantly improves the accuracy and robustness of low-frequency vibration signal processing.

The present technology relates to mitigating voltage drop conditions in systems with dynamic voltage and frequency scaling, and discloses a method of controlling a dynamic voltage and frequency scaling circuit, the method comprising: detecting a voltage drop relative to a current nominal voltage and frequency state; in response to the current nominal voltage and frequency state having a corresponding fallback state in a safe operating region of voltage and frequency, switching activity from a nominal source to a fallback source; and suspending the activity of the dynamic voltage and frequency scaling circuit when the current nominal voltage and frequency state cannot be fallback to the safe operating region.

A circuit including a digital-to-analog converter (DAC) having a first terminal and a second terminal. The circuit also includes a first diode having a first terminal coupled to the second terminal of the DAC and having a second terminal coupled to the first terminal of the DAC. A comparator has a first terminal and a second terminal. A second diode has a first terminal coupled to the second terminal of the DAC and has a second terminal coupled to the second terminal of the comparator. A voltage-to-current converter (V2I) has a terminal. A resistor has a first terminal coupled to the second terminal of the second diode and has a second terminal coupled to the terminal of the V2I converter.

The invention provides a frequency scale measurement method and device, computer equipment and a storage medium, and the method comprises the steps: carrying out the frequency division processing of a measurement signal outputted by a frequency source, and obtaining a low-frequency pulse signal; carrying out delay measurement and time interval counting on the low-frequency pulse signal by using a high-precision time interval counter, and outputting the low-frequency pulse signal in a timestamp form; the method comprises the following steps of: setting a sliding window, carrying out sliding average filtering processing on timestamps by utilizing a sliding average algorithm, carrying out sliding action difference on all the timestamps to obtain time differences, grouping the time differences in sequence, and averaging in groups to obtain average time differences; the number of measured samples is increased by increasing the length of the sliding window, so that statistical errors are reduced; a frequency measurement value, a relative frequency deviation and an Arron variance are calculated using the average time difference. According to the method provided by the invention, the sliding window is increased, and the frequency measurement result is obtained by using the algorithm of grouping and averaging the time difference, so that the method has higher measurement precision and stability.

An integrated circuit comprises an oscillator which outputs a clock signal, a logic circuit portion, a detection circuit portion for detecting signal propagation delay relative to clock frequency, and a power supply which provides a configurable supply voltage. The detection circuit comprises a latch circuit portion, a delay circuit portion and a comparison circuit portion. The latch circuit portion outputs an alternating signal which changes state in dependence on the clock signal. This is received by the delay circuit portion which outputs first and second delayed signals respectively subject to first and second propagation delays each dependent on the supply voltage. The comparison circuit portion compares the alternating signal with the delayed signals, and outputs respective comparison signals if said signals indicate that the respective propagation delay is smaller than the clock signal period. A control circuit portion controls the supply voltage in dependence on the comparison signals.

The present techniques relate to mitigating droop conditions over state transitions in systems having dynamic voltage and frequency scaling and there is disclosed a method of controlling a dynamic voltage and frequency scaling circuit, comprising: initiating a transition from a first voltage and frequency state to a second voltage and frequency state; switching activity from a first nominal source to a first fallback source; retuning the first nominal source to become a second fallback source at the second voltage and frequency state; switching activity from the first fallback source to the second fallback source; retuning the first fallback source to become a second nominal source at the second voltage and frequency state; and switching activity from the second fallback source to the second nominal source.

Described herein, in one embodiment, are techniques to facilitate the partial powerdown of sub-components of an execution unit or other graphics processing resource based on the workload to be executed. In another embodiment, granular dynamic voltage and frequency scaling is enabled in which the voltage and frequency of groups of processing resources within a graphics processor can be separately scaled.

An exemplary computing device includes a plurality of circuits and / or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

The invention provides a dynamically-configured mixed system calculation method and system, a chip and a storage medium. The method comprises the steps that metadata and data labels of two operands participating in a target calculation instruction are read; respectively writing the two operands into two target registers according to a calculation mode; and distributing a corresponding calculation unit for the target calculation instruction for calculation according to tag bits of the two target registers. According to the hybrid system calculation method and system, the chip and the storage medium provided by the embodiment of the invention, native instruction support is provided for hybrid system calculation, a dynamic register combination mechanism allows flexible adjustment of an arithmetic unit according to task requirements, and power consumption is remarkably reduced through strategies such as idle state closing, dynamic voltage adjustment and frequency scaling; multiple ternary modes and operation units with different lengths are supported, larger numerical values and complex tasks can be easily expanded, and different application requirements are met.

The invention belongs to the technical field of quantum frequency scale, dielectric constant and dielectric loss measurement, and particularly relates to a method and a device for measuring dielectric parameters of a loading medium of a miniaturized cavity bubble system. The method comprises the following steps: connecting a measurement device for loading dielectric parameters of a medium into a cavity bubble system in an atomic clock, and actually measuring the cavity bubble system by using the measurement device; the dielectric parameters comprise a dielectric constant and dielectric loss; the measuring device constructs a simulation model according to the state parameters of the cavity bubble system; parameter scanning analysis is carried out according to the simulation model, and relation images between dielectric parameters of an actual loading medium in the atomic clock and cavity bubble system simulation resonant frequency, an on-load Q value and a voltage standing wave ratio are obtained; and according to the actually measured resonant frequency, the load Q value and the voltage standing wave ratio, comparing the simulated resonant frequency and the simulated load Q value on the relation image, and determining the dielectric parameter value of the loading medium and the relation between the dielectric parameter value and the temperature.

The embodiment of the invention provides a resource allocation method and device, electronic equipment, a chip and a medium, and relates to the technical field of communication, and the method comprises the steps: determining a dynamic voltage and frequency scaling (DVFS) gear based on the number of resource elements (RE) in each time slot and a channel quality index (CQI) value; based on the DVFS gear, a number of enabled target cores is determined. According to the method disclosed by the invention, the number of the started target cores is determined according to the real-time RE number and the channel quality index corresponding to the received reference signal, so that dynamic power consumption control is realized, flexible power consumption adjustment is achieved, the energy consumption of the terminal is further saved, and the performance of the terminal is fully exerted.

A frequency adjustment method and apparatus, a processor, a chip, and a computer device are provided, and relate to the computer field. The method includes: A server obtains a load average and a PMU status in a frequency adjustment domain; and the server adjusts a frequency of a processor core in the frequency adjustment domain based on the load average and the PMU status, where the load average indicates an average of load values of all processor cores in the frequency adjustment domain when different processor cores execute tasks, and the PMU status indicates whether a running value of a PMU event reported by the processor core in the frequency adjustment domain reaches a threshold corresponding to the PMU event.

The invention relates to an AI intelligent calculation system power consumption dynamic power management and dynamic voltage and frequency regulation method, and belongs to the technical field of artificial intelligence. According to the AI intelligent computing system, an intelligent hybrid heterogeneous computing architecture of CPU + NPU + FPGA is adopted, computing power improvement of the low-power-consumption miniaturized intelligent computing system can be achieved, and the requirement for high computing power of an AI data processing function is met. The real-time state of the system is judged through a software algorithm, dynamic voltage and frequency regulation is performed on the CPU while dynamic power management of the intelligent computing system is realized, the problems of poor endurance and high energy consumption of an embedded unmanned intelligent platform in a severe environment can be solved, longer endurance of unmanned intelligent equipment in the severe environment can be ensured, and the service life of the unmanned intelligent equipment is prolonged. And the unmanned equipment is enabled to avoid infrared tracking.

The embodiment of the application provides a GPU computing power scheduling method, device, equipment, medium and program product, relates to the technical field of computing power scheduling, and the method comprises the following steps: according to real-time task demand, dividing the computing unit and the display memory resource of a GPU (Graphics Processing Unit) into a plurality of dynamically adjustable partitions; calculating the priority weight of each task; in combination with preemptive scheduling and cooperative scheduling, implementing resource preemption on a first priority task, and performing time-sharing multiplexing on a non-preempted task; performing dynamic voltage and frequency scaling (DVFS) and task merging strategy; through dynamic resource partitioning, dynamic priority evaluation, hybrid scheduling strategy and energy efficiency optimization algorithm, the GPU resource utilization and energy efficiency ratio in a multi-task scenario are significantly improved, and the energy consumption is reduced in combination with the DVFS and task merging strategy.

The invention relates to frequency scaling in a multi-tenant environment. Examples described herein relate to circuitry to: monitor availability data for a plurality of processes; determining one or more priority levels associated with at least one of the plurality of processes based on the policy parameters; and adjusting an operating frequency of the interface circuit based on the monitored availability data and the determined priority level of the process. In some examples, an operating frequency of an interface circuit is adjusted to prioritize an operating frequency requested by a high priority workload relative to an operating frequency requested by a low priority workload.

A system includes a high bandwidth memory (HBM) arranged into portions including memory cells, the HBM further including a differentiated dynamic voltage and frequency scaling (DDVFS) device to perform the following: for a first set of one or more of the memory cells in a first one of the portions, the first set including a first one of the memory cells, controlling a temperature of the first set based on one or more first environmental signals corresponding to at least a first transistor in the first memory cell; and for a second set of one or more of the memory cells in a second one of the portions, the second set including a second one of memory cells, controlling a temperature of the second set based on one or more second environmental signals corresponding to at least a second transistor in the second memory cell.

In one embodiment, a system on a chip integrated circuit (SoC) is provided that includes graphics processing resources including one or more graphics processing cores a memory subsystem including a memory controller, a physical interface, and a memory device and circuitry to dynamically adjust a voltage and frequency of the memory subsystem based on a workload executed by the graphics processing resources.

The application relates to the technical field of server hardware control, and discloses a server hardware acceleration control system based on noise temperature coupling. The system comprises a multi-source noise collector, a temperature control accelerator, a noise temperature coupling analyzer and an acceleration decision master control unit. The multi-source noise collector is arranged on the surface and internal key nodes of the acceleration unit, and can capture electromagnetic radiation noise spectrum and mechanical vibration noise waveform in real time; the temperature control accelerator integrates a thermoelectric refrigeration array and a voltage frequency modulation module, receives temperature sensing data flow, generates pulse type refrigeration instructions and clock frequency correction amount according to a dynamic strategy; the coupling analyzer decomposes multi-modal noise signals, extracts energy feature vectors and constructs a coupling coefficient matrix; the acceleration decision unit receives the matrix operation, outputs a frequency scaling factor and a voltage bias to the temperature control accelerator, feeds back a failure frequency band marker result update coefficient, and realizes dynamic balance of hardware acceleration performance and stability by fusing noise and temperature coupling characteristics.