91 results about "Frequency divider" patented technology

This invention belongs to the field of time-frequency unification and relates to a fast discipline method and system based on a high-stability OCXO. The method includes selecting a primary reference source, inputting the reference signal into a phase-locked loop frequency multiplier for frequency multiplication, and inputting the processed high-frequency reference signal into a high-precision phase measurement module. A monitoring and processing platform controls two frequency standard signals output from the OCXO frequency standard source through a control word. The first frequency standard signal of the first channel is input into a phase-locked loop frequency divider, and the second frequency standard signal is output to the high-precision phase measurement module. The third frequency standard signal of the second channel is directly input into the high-precision phase measurement module to measure the phase difference between the high-frequency reference signal and the second frequency standard signal. The monitoring and processing platform outputs an updated control word through a fast discipline algorithm to correct the OCXO frequency standard source parameters. The fast discipline process continues until the OCXO frequency standard source stabilizes and the phase difference with the reference source converges, ending the fast discipline state.

A fractional-N phase-locked loop (PLL) and its charge pump control method are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a frequency divider clock controller. The first current source provides a first current. The first PFD generates a first detection signal based on a first frequency divider clock to control the first current source, wherein the first frequency divider clock is generated based on an oscillation clock with an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal based on a second frequency divider clock to control the second current source. The frequency divider controller controls the second frequency divider clock based on a variable delay relative to the first frequency divider clock, wherein the variable delay is an integer multiple of the oscillation period. Using this method, phase noise can be reduced.

This invention discloses a power transistor drive circuit, PCB board, and controller, including a load detection circuit, a clock unit, a frequency divider counter, a 2-to-1 multiplexer, a drive circuit, and a power circuit. The input terminal of the load detection circuit is connected to the output terminal of the power circuit, and the output terminal of the load detection circuit is connected to the enable terminal of the 2-to-1 multiplexer. The clock unit is connected to the load detection circuit and the frequency divider counter, and the output terminal of the frequency divider counter is connected to the input terminal of the 2-to-1 multiplexer. The output terminals of the 2-to-1 multiplexer are connected to the input terminals of the drive circuit, and the output terminal of the drive circuit is connected to the input terminal of the power circuit. This solution can switch the drive cycle according to the output status of the power transistor, thereby reducing the switching frequency of the power transistor and effectively reducing the switching losses of the power transistor.

This invention discloses a radio frequency millimeter-wave phase-to-voltage converter, belonging to the field of radio frequency microwave integrated circuit technology. The converter includes: a first and second frequency divider chain for dividing two input signals to achieve phase compression; a first and second quadrature generator for providing a -90° linearized bias; a three-state coupling network connected between the two frequency divider chains to eliminate phase mode ambiguity introduced by the frequency dividers through reconfigurable coupled phase; and a symmetrical phase detector for converting the linearized phase difference into a voltage signal output. This invention compresses the ±180° phase difference to a small angle range using phase compression technology, combined with linearized bias to allow the phase detector to operate in the linear region, and utilizes the three-state coupling network to achieve unambiguous detection across the entire 360° phase range. Implemented using a 40nm CMOS process, it requires no external clock, has no inductor design, a core area of ​​only 0.016mm², power consumption of 22mW, a response speed of 120ns, and a linearity of 1.05% FSR.

In a start-up sequence of a phase-locked loop, the voltage-controlled oscillator is controlled by a first voltage to operate in a linear regime and a first count of a register of a frequency divider is read. Then, the voltage-controlled oscillator is controlled by a second voltage having an offset from the first voltage and a second count of the register is read. A slope of the linear regime is then determined from a difference between the first and second counts and an offset of the first and second voltages. A determination is made of a third voltage needed to reach a target frequency of the output signal as a function of the slope and a deviation between a current value of the register count and a target value corresponding to the target frequency. The voltage-controlled oscillator is then controlled with the third voltage.

A phase-locked loop and a method for generating an output clock with reduced jitter. The phase-locked loop with reduced jitter comprises a phase detector for comparing a phase of a reference clock with a phase of a feedback clock to generate a plurality of up and down control signals; a voltage-controlled oscillator for generating an oscillation signal according to the plurality of up and down control signals; an output divider for dividing the oscillation signal to generate the output clock; a non-integer feedback divider for dividing the oscillation signal according to a modulated sequence to generate a modulated clock; a divider in series with the non-integer feedback divider and for dividing the modulated clock by a fixed modulus to generate a divided clock; wherein a frequency of the modulated clock is an integer multiple of a frequency of the divided clock, and one of the modulated clock and the divided clock is used as the feedback clock.

The application provides a programmable frequency divider, a phase-locked loop circuit, a chip and an electronic device, and the programmable frequency divider comprises: a frequency division module, which comprises n frequency division unit cascades, each frequency division unit is controlled by shielding based on a respective reset signal and is controlled by frequency division based on a respective frequency division control bit and a mode input signal, so as to perform frequency division operation on a respective input clock, wherein n is a natural number greater than 1; a control module, which is connected with the frequency division control end and the reset end of each frequency division unit in the frequency division module, and is used for providing a corresponding frequency division control bit and a corresponding reset signal to each frequency division unit; and an output sampling module, which is connected with the mode output end of the second frequency division unit in the frequency division module, and samples the mode output signal of the second frequency division unit based on the input clock of the first frequency division unit to obtain a final frequency division clock. The application solves the problem that the existing programmable frequency divider cannot realize a wide frequency division range.

The application provides a peak inductive reuse CML divide-by-two frequency divider circuit. The circuit comprises a first CML latch and a second CML latch, the two CML latches are interconnected in a divide-by-two frequency division mode; a first peak inductor, a second peak inductor, a third peak inductor and a fourth peak inductor, the four peak inductors are sequentially connected in a ring circuit; a non-inverting output end of the first CML latch is connected to a first common connection point of the first peak inductor and the fourth peak inductor; an inverting output end of the first CML latch is connected to a second common connection point of the second peak inductor and the third peak inductor; a non-inverting output end of the second CML latch is connected to a third common connection point of the first peak inductor and the second peak inductor; and an inverting output end of the second CML latch is connected to a fourth common connection point of the third peak inductor and the fourth peak inductor. The technical scheme of the application can improve the frequency division speed while reducing the chip area.

An integrated circuit device (200) is provided. In some examples, the integrated circuit device includes a first timing resetter (216) configured to receive a reference clock signal (201) and a voltage controlled oscillator (VCO) output signal (212), the first retimer configured to provide a first retimed clock signal (216A) in response to the reference clock signal and the VCO output signal. A first multiplexer (215) receives the first retimed clock signal and provides a feedback clock signal (215A). A phase frequency detector (202) receives a feedback clock signal and a reference clock signal and provides error signals (202A and 203A) in response to the feedback clock signal and the reference clock signal. A VCO (211) receives a voltage signal (220A) based on the error signal, the VCO configured to provide a VCO output signal (212) in response to the voltage signal.

1. Name of the product in this design: Frequency divider board (II). 2. Purpose of this design: for audio signal processing. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: 3D view 1.

A device may include: a reference divider circuit for dividing a reference clock; a phase-frequency detector circuit for detecting a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock; a loop filter circuit for filtering the detector output; a voltage-controlled oscillator (VCO) control output pin coupled to the loop filter output; a VCO clock divider control output pin for selecting the divisor of an external clock divider circuit; a divider VCO clock input pin coupled to the output of the external clock divider circuit; a pulse width modulation (PWM) circuit having a PWM clock input coupled to the divider VCO clock input pin; a period register for storing a period value; a duty cycle register for storing a duty cycle value; and a PWM output based on the period value and the duty cycle value.

This application provides a phase-locked loop (PLL), a control method, and a frequency source. It includes a controller, a time-to-digital converter (TD-to-digital converter), an arithmetic logic unit (ALU), a digitally controlled oscillator (DCO), and a frequency divider. The DCO outputs a linearly swept frequency signal based on a frequency control signal from the ALU. The frequency divider generates a divided frequency signal based on the output frequency of the DCO. The TD-to-digital converter outputs the phase difference between the divided frequency signal and a reference signal. The ALU outputs a frequency control signal based on the phase difference and a control code to adjust the output frequency of the DCO. The controller acquires the output signal of the TD-to-digital converter after a step point in the division ratio, and adjusts the control code until the output signal of the TD-to-digital converter after the step point is zero when the output signal is not zero. This method improves the linearity of the sawtooth waveform generated by the PLL at the step point.

A phase-locked loop (PLL) and clock signal control method are disclosed. The PLL features high-precision frequency conversion and includes a PLL main circuit, a fractional-division modulator, and a dynamic frequency adjustment monitoring and ramp controller. The PLL main circuit has a frequency divider, which divides a clock signal to serve as a feedback clock. The fractional-division modulator is coupled to the frequency divider to modulate a fractional-division request, thereby controlling the division ratio. The dynamic frequency adjustment monitoring and ramp controller responds to a change in a target division ratio by generating a sequence of step division ratios to update the fractional-division request. This application achieves smooth dynamic adjustment of the PLL frequency by updating the division request in a step manner.

The present invention relates to a phase control loop (1) comprising a phase detection unit (2) for detecting a phase of a reference signal (100) and for outputting a measurement signal φ meas , a phase deviation detection unit (3) for generating an error signal φ err from the measurement signal φ meas and a target signal φ tgt , a loop filter (4) for filtering the error signal φ err, a modulator unit (5) for modulating the filtered error signal and generating a tune signal (500), and an oscillator (6) for generating an output signal (300) from the tune signal (500), wherein a feedback signal (200) formed from an output signal (300) of the phase-locked loop (1) is supplied to the phase detection unit (2), and wherein the phase-locked loop (1) further comprises: a divider unit (8) configured to generate a modulator clock signal (800) from an oscillator clock signal (400) of the oscillator (6) and to supply the modulator clock signal (800) to the modulator unit (5), and a sampler unit (15) configured to detect an offset (900) between the reference signal (100) and the modulator clock signal (800) by the offset (900) in determining the error signal φ err to take precise account of.

The utility model discloses a kind of multistage frequency divider and control system, drive system.The multistage frequency divider includes: the first input end of first frequency division module is used to access clock signal, first frequency division module is configured as according to clock signal output multiple same or different frequency first frequency division signal, wherein the first output end of first frequency division module is coupled with the first input end of second frequency division module by level converter;Second frequency division module is configured as according to first frequency division signal output multiple same or different frequency second frequency division signal, wherein the first output end of second frequency division module is coupled with the second input end of first frequency division module by level converter;First frequency division module is also configured as according to second frequency division signal output multiple same or different frequency third frequency division signal.The multistage frequency divider provided in the utility model embodiment is favorable to meet the multiple frequency signal input demand of equipment.

The application discloses a phase-locked loop circuit and electronic device, and relates to the technical field of integrated circuits, which comprises a frequency discriminator, a charge pump, a low-pass filter, a voltage-controlled oscillator, a frequency divider and a reinforcing circuit, wherein the frequency discriminator, the charge pump, the low-pass filter and the voltage-controlled oscillator are sequentially connected, the frequency divider is connected with the frequency discriminator and the voltage-controlled oscillator; the reinforcing circuit is arranged between the charge pump and the low-pass filter; when the single event transient effect does not occur in the charge pump, the reinforcing circuit does not work; when the single event transient effect occurs in the charge pump, the reinforcing circuit works to reversely compensate the pulse current generated by the single event transient effect of the charge pump. The application can attenuate the pulse current injected (or discharged) by the charge pump subjected to single particle bombardment to the low-pass filter, reduce the influence on the control voltage of the voltage-controlled oscillator, and accelerate the recovery time after the phase-locked loop is unlocked.

This invention discloses an excitation circuit and method for a fluxgate magnetic probe. The excitation circuit includes a crystal oscillator, a frequency divider, a D flip-flop, a first current amplifier, a second current amplifier, a first resistor, a second resistor, a first capacitor, a second capacitor, a transistor, and an excitation coil. The crystal oscillator generates a high-frequency periodic signal, which is input to the input terminal of the frequency divider. The frequency divider divides the signal to obtain a square wave signal of the desired frequency. The square wave signal is input to the input terminal of the first current amplifier and the data input terminal of the D flip-flop. The data output terminal of the D flip-flop is connected to the input terminal of the second current amplifier. The first current amplifier is sequentially connected to the first resistor, the first capacitor, the excitation coil, the second capacitor, and the second resistor. The other end of the second resistor is connected to the output terminal of the second current amplifier. The base of the transistor is connected to the output terminal of the first current amplifier, and the collector of the transistor is connected to the clock control terminal of the D flip-flop.

Aspects relate to a divide by 3 prescaler for an integrated circuit. An apparatus includes a first logic block configured to generate a first input pulse at a rising edge of a clock signal, and a second logic block configured to generate a second input pulse after the first input pulse that ends at a falling edge of the clock signal. The falling edge is for a clock cycle subsequent to the rising edge. A third logic block is coupled to the first input pulse and the second input pulse and configured to generate a divide by 3 clock output.

An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.

The application provides a latch circuit, a divide-by-two, divide-by-three and divide-by-five circuit and an HS-MMD, which comprises a first tri-state gate, a second tri-state gate and a first inverter; an input end of the first tri-state gate is a first input end of the latch circuit, a control end of the first tri-state gate is a second input end of the latch circuit, the control end of the first tri-state gate is used for receiving a first clock signal, an output end of the first tri-state gate is an output end of the latch circuit, the output end of the first tri-state gate is also connected to an input end of the first inverter, an output end of the first inverter is connected to a first input end of the second tri-state gate, an output end of the second tri-state gate is connected to the output end of the first tri-state gate, and a second input end of the second tri-state gate is used for receiving a second clock signal. The application does not need to set a high-speed pre-divider, the MMD can directly process signals from a VCO, is beneficial to the modular integration of a PLL, and improves the integration degree of the PLL.

The present disclosure proposes a transmitter and receiver for medical applications, wherein the transmitter comprises: an analog front end for receiving an analog signal of a neural electrode; a digital baseband processing module for digitizing and channel coding the analog signal to obtain a coded signal; a modulator for 16-QAM modulation of the coded signal to obtain a modulated signal; 16-QAM modulation is used to improve the scalable data rate; a plurality of target frequency signals are generated by a phase-locked frequency divider, and the target frequency signals are divided into a plurality of target sub-frequency signals; the phase of the modulated signal is adjusted based on the plurality of target sub-frequency signals to obtain a phase-adjusted signal, realizing multi-band data transmission within the transmitter; and finally a power amplifier amplifies the phase-adjusted signal, and the amplified phase-adjusted signal is transmitted to a transmitting unit so that the transmitting unit transmits a signal, realizing high-speed and low-power signal transmission.

This invention provides a method and system for detecting mode-locked optical fiber frequency combs. The method involves calculating the theoretical repetition frequency of the optical fiber frequency comb based on the cavity length of the optical system. Pump light is injected into the optical system, and the output light is converted into an electrical signal by a photodetector. This electrical signal is then filtered out by a bandpass amplifier to obtain the fundamental frequency signal of the optical fiber frequency comb, which is then amplified. The signal is then down-divided to the kHz level by a frequency divider / amplifier signal processing unit, and finally converted into a square wave signal by a voltage comparator. The current division level and division ratio of the frequency divider / amplifier signal processing unit are determined by a microcontroller based on the theoretical repetition frequency of the optical fiber frequency comb. A rubidium atomic clock provides a clock reference for the microcontroller, which determines whether the optical fiber frequency comb has achieved mode-locked operation based on the measurement error of the time interval between the square wave signal periods. This invention can accurately detect the mode-locked state of optical fiber frequency combs with relatively low repetition frequencies.

An apparatus, including: a first synchronizer configured to synchronize a frequency divider reset signal with a reference clock signal to generate a reference clock domain reset signal; a set of delay buffers configured to generate a set of delayed staggered reference clock domain reset signals based on the reference clock domain reset signal; a set of second synchronizers configured to synchronize the set of delayed staggered reference clock domain reset signals with a phase lock loop (PLL) clock signal to generate a set of PLL clock domain reset signals; a phase detector configured to generate a signal related to a phase difference between respective clocking edges of the reference clock signal and the PLL clock signal; a phase corrector configured to generate a select signal based on the phase difference signal; and a multiplexer configured to output one of the PLL clock domain reset signals based on the select signal.

A monitoring circuit includes first and second oscillators, first and second frequency dividers, first and second counters, a determination portion, and an identification portion. The first and second frequency dividers respectively divide frequencies of first and second clock signals outputted from the first and second oscillators, respectively. The first and second counters respectively count the numbers of clocks of the second and first clock signals at first and second numbers of periods of first and second frequency-divided signals outputted from the first and second frequency dividers, respectively. The determination portion determines, based on results of counting by the first and second counters, whether or not an abnormality has occurred in either of the first and second clock signals. The identification portion identifies, at the occurrence of an abnormality in either of the first and second clock signals, which of the first and second clock signals is in an abnormal state.

This invention discloses a low-phase-noise variable reference source circuit, comprising an input power divider circuit, a first phase-locked loop (PLL) circuit, a first filter circuit, a second PLL circuit, a second filter circuit, a harmonic generator circuit, a first filter amplifier circuit, a mixer circuit, a second filter amplifier circuit, a frequency divider circuit, and a third filter circuit. In this invention, a reference signal enters the power divider circuit, one path is sent to the PLL circuit, where it generates a 40-100MHz signal after two PLL circuits; the other path is sent to the spectrum generator circuit to generate a 1700MHz signal. After mixing by the mixer circuit, a broadband radio frequency signal of 1600-1660MHz is generated. Finally, after being divided by 16 by the frequency divider circuit, an adjustable and low-phase-noise signal of 100-110MHz is generated. This circuit is commonly used as a reference input in communication equipment (low-cost instruments, handheld radios, satellite communications), playing a crucial role in various communication devices and having a wide range of applications.

This application discloses a phase-locked loop (PLL) output frequency calibration circuit. A reference clock is input into a fractional-division PLL and used as its reference clock. Simultaneously, this clock is also input to a voltage-controlled pulse (VCP) generator. Under the influence of a control voltage, the VCP generator produces digital pulses with the number of logic high levels proportional to the control voltage, which are then fed into a ΣΔ modulator. The ΣΔ modulator processes the configuration value from the fractional register and, together with the configuration value from the integer register, sends it to the frequency divider controller to generate the required division ratio for the PLL, thus outputting a clock. This clock is adjusted according to changes in the external control voltage. Using this technical solution, the frequency of the reference clock does not need to be changed. The relationship between the number of logic high levels in the digital pulses generated by the VCP generator and the number of logic high levels in the digital pulses of the ΣΔ modulator determines whether to change the output of the ΣΔ modulator, thereby achieving calibration of the PLL output frequency.

This utility model discloses a functional board deformation stress detection system, relating to the field of functional board testing. It includes a cylinder, a pressure detection module, and a deformation stress detection module. The functional board to be tested is placed above the pressure detection module, and the cylinder is located directly above the pressure detection module. The deformation stress detection module connects the pressure detection module and the cylinder. After detecting the pressure, the pressure detection module outputs a high-level signal to the deformation stress detection module. The deformation stress detection module includes a time control circuit and a deformation detection circuit. The time control circuit consists of a frequency divider circuit and a timing circuit, which can generate a periodic square wave and achieve precise timing. The deformation detection circuit uses components such as a PMOS transistor, comparator, and latching diode to convert the time difference into a voltage difference, combined with an LED to indicate the detection result. This utility model detects deformation by converting the time difference into a voltage, achieving precise deformation detection. The preset time can be manually adjusted via external buttons to meet different needs.