524 results about "Frequency divider" patented technology

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

An electronic interface device is configured for use with associated optics for employing coded light for illuminating a liquid, gaseous, or other analyte or target, such as for measuring or determining a composition or other property of the analyte or target. The arrangement can help enable a far higher level of performance, such as for spectral analysis, imaging, or both. A shared common clock on both the illumination and receive sides of the system can be included, such as together with one or more of reference detection, per-channel wavelength-dependent modulation, multiple concurrent feedback loops at different levels, orthogonal and circulant codes, phase-scrambling to better utilize ADC dynamic range, oversampling, and other signal processing can be provided. Modulation codes can optionally employ a clock divider, such as which can be configured to satisfy one or more specified constraints.

The invention discloses a clock synchronization system. The clock synchronization system comprises a trigger group and a frequency divider group, the trigger group comprises N triggers, and the frequency divider group comprises N frequency dividers; the trigger group receives N paths of clock signals and one path of SYNC pulse signal, the N paths of clock signals are respectively transmitted to the N frequency dividers, and the N paths of pulse signals output by the trigger group are respectively transmitted to the N frequency dividers, N is a positive integer greater than 1, through the technical scheme of the invention, the risk of generating a metastable state can be reduced, and the power consumption can be reduced at the same time.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

The invention relates to the technical field of application of thermal printing heads, in particular to a thermal printing device and a printing method for simplifying gray scale printing and achieving fine gray scale control, and the thermal printing device is provided with an external printing host and a thermal printing head. A PWM modulation unit, a clock unit CLK, a frequency divider, a latch unit LATCH, a printing gating unit STB and a plurality of control units in one-to-one correspondence with a plurality of heating points in the heating resistor are arranged in the printing logic control component, and the printing gating unit STB is used for outputting a current line printing gating control signal to the control units; the PWM modulation unit is used for carrying out pulse width modulation on a printing pulse number mi issued by an external host and outputting heating time pulse signals superposed with different duty ratio pulses to the control unit so as to meet different color development temperature requirements; compared with an existing mode that multiple times of sending of printing data are combined with STB gating, the cost requirement for printer control resources is remarkably reduced on the premise that gray level fine control is met.

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

The present invention provides an ultrasonic motor starting device and method based on an index output with high performance, which relates to the field of ultrasonic motor starting. The device includes a two-input AND gate having a first input terminal, a second input terminal and an output terminal, and the first input terminal is T i It is used to input the timing signal, and the second input terminal is connected to the pulse output terminal of the division counter, the output terminal of the AND gate is connected to the input terminal of the D flip-flop, the clock terminal of the D flip-flop is connected to the clock terminal of the division counter, and receives the CLOCK clock, the CLOCK clock is the system clock, the output terminal of the D flip-flop is connected to the clock terminal of the latch, and the input terminal of the latch is i DATA is used to receive the division value, F i The DATA division value is the time length T i The multi-channel data output terminal of the latch is connected to the data input terminal of the frequency divider counter, and the output terminal of the frequency divider counter outputs a SIN driving signal or a COS driving signal. The present invention can improve the safety and reliability of ultrasonic motor starting.

A Global Navigation Satellite System (GNSS) receiver for processing GNSS satellite signals use a quasi-asynchronous sampling frequency grid to process the received signals. The GNSS receiver includes a plurality of RF paths configured to receive Global Navigation Satellite System (GNSS) signals from an antenna and transmit the GNSS signals in a frequency range for digitizing the GNSS signals. A phase-locked loop is configured to generate a clock signal and a plurality of clock dividers are configured to receive the clock signal and divide the clock signal. Each of a plurality of navigation systems receive a clock signal from one of the plurality of clock dividers.

The invention provides a semiconductor device, a memory system and an operating method thereof. The semiconductor device includes: a delay-locked loop (DLL) configured to output a first correction value corresponding to a single period of a clock; and a duty cycle correction circuit including a frequency divider configured to divide the clock into half to generate a divided clock, delay the divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generate an adjusted clock having a duty cycle of 5: 5 based on the divided clock and the delayed clock. The delay value is adjusted or changed based on the first correction value.

The present disclosure provides an integrated circuit, which includes a divider stage, a frequency trimming stage, a voltage control stage, and a logic stage. The divider stage is configured to generate a first clock signal by dividing a frequency of an input clock signal. The frequency trimming stage is configured to add a first delay to the first clock signal to generate a second clock signal. The voltage control stage is configured to repeatedly adjust a second delay of the second clock signal according to a control signal generated by a feedback path to generate a third clock signal. The logic stage is configured to perform a logic operation according to the first clock signal and the third clock signal to generate an output clock signal.

The invention provides a static frequency divider with adjustable self-resonant frequency and a clock circuit, and relates to the technical field of circuits, the frequency divider comprises a master latch and a slave latch; each of the master latch and the slave latch comprises a current source, an adjustable resistor unit, a differential amplification pair, a cross coupling pair and a load resistor pair; the current source is connected with the first current branch and the second current branch, the first current branch is connected with the load resistor pair through the differential amplification pair, the second current branch is connected with the load resistor pair through the cross coupling pair, the first current branch is provided with a first switching tube, and the second current branch is provided with a second switching tube and an adjustable resistor unit which are connected in series. Thus, the adjustable resistor unit is configured on the second current branch, association between the resistance value of the adjustable resistor unit and the frequency of the frequency divider is established, a hardware basis is provided for frequency adjustability, and frequency requirements of different scenes are met by adjusting the resistance value of the adjustable resistor unit and adjusting the self-resonant frequency of the frequency divider.

The application discloses an ultra-wideband reconfigurable injection locking multi-mode single-ended input / output frequency divider circuit, comprising an input unit, a frequency division circuit connected with the input unit, and an output unit connected with the frequency division circuit, wherein the frequency division circuit comprises an injection locking two-frequency division circuit and an injection locking three-frequency division circuit; the input unit utilizes a balun structure circuit, so that the injection locking two-frequency division circuit and the injection locking three-frequency division circuit are the same single-ended input; and the output unit utilizes a Multi-tank resonant network structure to realize single-ended output of two / three frequency division modes. The application can realize better efficacy, ultra-wideband performance, lower cost and easy integration in the design of a wideband millimeter wave phase-locked loop chip.

A clock synchronization (SYNC) system. The clock SYNC system comprises a trigger group (110) and a frequency divider group (120); the trigger group (110) comprises N triggers; the frequency divider group (120) comprises N frequency dividers; and the trigger group (110) receives N clock signals and one SYNC pulse signal, respectively transmits the N clock signals to the N frequency dividers, and respectively transmits to the N frequency dividers the N pulse signals outputted by the trigger group (110), wherein N is a positive integer greater than 1.

A clock signal correction device includes a first clock signal generator configured to generate an internal clock signal in a first mode, a divider configured to generate a plurality of first clock signals having different phases based on the internal clock signal, a calibration circuit configured to generate a first skew code corresponding to a skew between a first clock signal and a second clock signal of the plurality of first clock signals and a second skew code corresponding to a skew between a third clock signal and a fourth clock signal of the plurality of first clock signals, and a skew adjustment circuit configured to adjust the phases of a plurality of second clock signals having different phases generated using a clock signal received from an external source based on the first skew code and the second skew code in a second mode different from the first mode.

The application discloses a frequency divider-free phase-locked loop and a reference double-delay frequency locking method thereof. The sub-sampling phase-locked loop architecture receives an output of an oscillator and feeds back the output to a reference double-delay frequency locking loop. The output end of a reference double-delay generator in the reference double-delay frequency locking loop is electrically connected with the input end of a sample-and-hold circuit, and the output end of the sample-and-hold circuit is electrically connected with the input end of an automatic phase error state detector. The sample-and-hold circuit simultaneously receives an oscillator output feedback signal of the sub-sampling phase-locked loop architecture. The output end of the automatic phase error state detector is electrically connected with the input end of an adaptive output frequency corrector, and the output end of the adaptive output frequency corrector is electrically connected with the sub-sampling phase-locked loop architecture. Unequal double-reference clock delays are introduced, the sample-and-hold circuit is combined to realize the detection of the output frequency, a new frequency locking loop working at a reference frequency is used to replace a traditional frequency locking loop, and the problem of high power consumption caused by a high-frequency frequency divider is solved.

The application provides an equivalent sampling circuit and device, and an equivalent sampling method, and relates to the field of circuits.The equivalent sampling circuit comprises a frequency discriminator, a voltage-controlled oscillator, a first frequency divider, a second frequency divider and a sampling unit; wherein the frequency discriminator is used to obtain a reference signal and a first frequency division signal, compare the frequency and phase of the first frequency division signal and the reference signal respectively, and obtain the frequency difference and phase difference of the first frequency division signal and the reference signal; the voltage-controlled oscillator is used to generate a second oscillation signal based on the frequency difference and the phase difference; the second frequency divider is used to perform integer frequency division on the second oscillation signal by using an integer frequency division coefficient to generate a second frequency division signal; and the sampling unit is used to perform equivalent sampling on a to-be-tested signal based on the second frequency division signal.The equivalent sampling circuit in the application can greatly improve the time delay step of the second frequency division signal, does not increase the circuit cost, and ensures the accuracy of sampling.

The invention provides a clock signal correction apparatus, a semiconductor apparatus, and a computing system. The clock signal correction apparatus includes: a first clock signal generator configured to generate an internal clock signal in a first mode; a frequency divider configured to generate a plurality of first clock signals having different phases based on the internal clock signal; a calibration circuit configured to generate a first skew code corresponding to a skew between a first clock signal and a second clock signal of the plurality of first clock signals and a second skew code corresponding to a skew between a third clock signal and a fourth clock signal of the plurality of first clock signals; and a skew adjustment circuit configured to adjust phases of a plurality of second clock signals having different phases generated using a clock signal received from an external source based on the first skew code and the second skew code in a second mode different from the first mode.

This invention belongs to the field of time-frequency unification and relates to a fast discipline method and system based on a high-stability OCXO. The method includes selecting a primary reference source, inputting the reference signal into a phase-locked loop frequency multiplier for frequency multiplication, and inputting the processed high-frequency reference signal into a high-precision phase measurement module. A monitoring and processing platform controls two frequency standard signals output from the OCXO frequency standard source through a control word. The first frequency standard signal of the first channel is input into a phase-locked loop frequency divider, and the second frequency standard signal is output to the high-precision phase measurement module. The third frequency standard signal of the second channel is directly input into the high-precision phase measurement module to measure the phase difference between the high-frequency reference signal and the second frequency standard signal. The monitoring and processing platform outputs an updated control word through a fast discipline algorithm to correct the OCXO frequency standard source parameters. The fast discipline process continues until the OCXO frequency standard source stabilizes and the phase difference with the reference source converges, ending the fast discipline state.

The application discloses a frequency divider and a frequency division system, and relates to the field of signal processing.The frequency divider comprises an input port, an all-pass filter, a first adder and a second adder.The input port is connected with the input end of the all-pass filter, the input end of the first adder and the input end of the second adder.The output end of the all-pass filter is connected with the input end of the first adder and the input end of the second adder.The all-pass filter filters an original signal input by the input port based on preset filter coefficients to obtain a filtered first signal.The output end of the first adder is connected with a high-pass output port of the frequency divider, and the output end of the second adder is connected with a low-pass output port of the frequency divider.The first adder is used for adding a negative value of the first signal to the original signal to obtain a high-pass signal of the frequency divider.The second adder is used for adding the first signal to the original signal to obtain a low-pass signal of the frequency divider.The application provides a frequency divider based on an all-pass filter, which effectively reduces the occupied computing resources of the frequency divider.

A digital phase-locked loop that tunes frequency and corrects phase errors using a variable capacitance based on a pulse signal is provided. The digital phase-locked loop comprises: a phase detector for comparing a phase of a reference signal with a phase of a feedback signal; a digital loop filter for outputting an adjustment signal for adjusting the duty ratio of the first time period based on the lifting signal of the phase detector; the variable capacitance controller is used for outputting a capacitance control signal with a duty ratio based on the feedback signal, the adjusting signal and the lifting signal; a digitally controlled oscillator for changing a first capacitance of the capacitor bank circuit based on the capacitance control signal and adjusting a phase based on an average of the first capacitance during a first time period; and the frequency divider is used for carrying out frequency division on the output signal.

The invention discloses a distributed photovoltaic aggregation frequency modulation standby optimal configuration method considering node frequency security constraints under transmission and distribution cooperation. The method comprises the following steps: describing uncertainty of photovoltaic aggregation frequency modulation capability by using a Gaussian mixture model, and establishing a power transmission network node frequency response model containing frequency space distribution characteristics; taking minimization of system power generation and frequency modulation reserve cost as a target, and combining opportunity constraint planning to construct an optimal configuration model; a response model is reduced based on a frequency divider theory, a Bernstein polynomial approximates frequency dynamics, and a differential algebraic equation is converted into an algebraic equation; then, binary expansion and Gaussian mixture model linear invariance are utilized to convert the model into a mixed integer linear programming model, and Bernstein polynomial convex hull property tightening constraint is combined; and finally, solving the model to obtain the optimal photovoltaic aggregation frequency modulation reserve capacity and control parameters. The frequency space distribution is accurately described, the problem of insufficient frequency safety risk identification is solved, and the frequency safety level of a power system is improved.

The invention relates to a device (10) for amplifying a laser pulse which comprises a divider section (14) for dividing the laser pulse into multiple sub pulses (43) and for introducing a time delay between the sub pulses (43), a compressor section (15) for compressing the temporally divided sub pulses (43) and a combiner section (17) for combining the compressed sub pulses (44) to one compressed laser pulse (45).

The invention provides a phase-locked loop rapid locking circuit structure and a control method thereof, the circuit structure comprises a voltage-controlled oscillator, a frequency divider, a phase discriminator and a rapid locking loop filter, and the rapid locking loop filter comprises a capacitive digital-to-analog conversion module. According to the invention, the capacitive digital-to-analog converter module is adopted, and the control voltage of the voltage-controlled oscillator can be rapidly and accurately set based on the charge sharing principle, so that rapid locking is realized; moreover, the structure multiplexes the capacitor in the loop filter, and does not need an extra area. The method has the advantages of high precision, low power consumption and low cost, and has extremely high application value and potential.

To provide an amplifier circuit capable of miniaturization and widening bandwidth.SOLUTION: An amplification circuit includes: a first distributor for distributing an input signal to a first signal and a second signal; a first amplifier for amplifying the first signal; a second amplifier for amplifying the second signal; a combiner for combining the first signal and the second signal, and outputting the combined signal as an output signal; and a CRLH line, connected to at least either a first line connecting the first distributor and the first amplifier or a second line connecting the first distributor and the second amplifier, for adjusting a phase of at least the first signal flowing the first line or the second signal flowing the second line.SELECTED DRAWING: Figure 3

Disclosed are a clock divider and a control method thereof, which enable retention work to be smoothly performed by ensuring that an output clock of the clock divider is in a low-level state in a retention signal conversion section. A clock divider according to an embodiment of the present invention comprises: a counter that counts clocks of an input clock and generates a counter output for dividing the input clock; an output clock generator that generates a generated clock edge according to the counter output, thereby generating an output clock divided from an input clock; and the state machine controls the counter according to a clock low level request of the power management unit, so that the output clock is in a low level state in a retention signal conversion interval.

Embodiments of the present disclosure relate to a circuit for generating and trimming stages of memory cell read operations. A read signal generator generates a read signal to control a read operation of a memory array. The read signal generator may be selectively controlled to generate an oscillating signal having a period corresponding to a characteristic of the read signal. The oscillation signal is passed to a frequency divider that divides the oscillation signal and supplies the divided oscillation signal to an output pad. The frequency of the oscillating signal may be measured at the output pad. The frequency of the oscillating signal may be calculated as a function of the frequency of the oscillating signal, and the duration of the signal characteristic read. The read signal characteristics may then be adjusted as required.

Embodiments disclosed herein relate to the management of a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing spurious pulses of clock output. In one example, a system provides a first clock signal via an oscillator and a second clock signal based on the first clock signal and a divider. The system further receives a first signal that indicates a change in a frequency of the first clock signal from a first frequency to a second frequency. In response to the first signal, the system determines an edge of the second clock signal and provides, at a time based on the edge of the second clock signal, a second signal to the oscillator to cause the change to the second frequency.

The invention discloses a circuit structure and a method for ensuring the stability of a clock circuit signal in a power-on stage, and the circuit structure comprises an asynchronous frequency divider which is formed by cascading a plurality of stages of D triggers and is triggered by an output signal of a clock circuit; the clock gating unit is used for shielding a current signal output by the asynchronous frequency divider after the count of the asynchronous frequency divider reaches a set parameter and a frequency division clock signal is started to be output; and the clock stability judgment logic circuit is used for carrying out stability judgment on the shielded signal, and when the judgment result is stable, the clock gating unit relieves shielding on the current crystal oscillator clock signal and transmits the current crystal oscillator clock signal to the digital circuit. Through a circuit structure of an asynchronous frequency divider and a gated clock technology, a crystal oscillator clock is safely and reliably converted into a working clock of a digital circuit.