826 results about "Frequency divider" patented technology

The invention provides a clock signal generating circuit, a wired communication transceiver and electronic equipment, and the circuit outputs a first DC voltage comprising phase difference information and frequency difference information of a reference clock signal and a feedback clock signal through a phase frequency detection module. The pulse generator generates a narrow pulse signal based on the DC voltage and a reference clock signal, the oscillation frequency of each secondary ring oscillator in the cross-coupled ring oscillator is controlled by the first DC voltage, and the cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross coupling ring oscillator receives the narrow pulse signal, frequency and phase locking is completed in an injection locking mode, and the frequency divider is used for conducting frequency division processing on any high-frequency clock signal and outputting a feedback clock signal. Therefore, a high-frequency multi-phase clock signal with low phase noise and high phase precision can be generated by using the low-frequency reference clock signal.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

A digital frequency synthesizer includes a delay-locked loop (DLL) that generates time-delayed versions of a reference clock signal, a clock divider that executes an integer-division operation on one delayed clock signal to generate an integer-divided clock signal, and control circuitry that generates fractional data for enabling a fractional division. The digital frequency synthesizer further includes a first clock selector that selects one delayed clock signal as a DLL clock signal based on the fractional data, a delay chain that generates time-delayed versions of the DLL clock signal, and a second clock selector that selects one delayed clock signal as a selected clock signal based on the fractional data. A rising edge of the integer-divided clock signal is adjusted based on the selected clock signal to generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.

The invention relates to a programmable frequency divider applied to JESD204B / C. The programmable frequency divider comprises a prescaler which realizes 1 / 2 / 4 dynamic frequency division through a closed-loop feedback structure; according to the 12-bit main frequency divider, the duty ratio of odd-even frequency division is controlled by a 11-stage asynchronous CML frequency-halving chain and a separation DFF0 module; the frequency dividing ratio N is equal to DIV Nlt; 11: 0gt; 2, the odd number frequency division duty ratio is automatically adjusted to (N + 1) / 2N; the cascade noise optimization comprises the following steps of: resampling by using an input clock fin through a retiming trigger (RetimeDFF1 / 2); according to the pulse generator, the number K of pulses output by a four-stage counter is equal to Pulsecount; 3: 0gt; a decimal value; and the output mode circuit supports three-mode direct connection. According to the programmable frequency divider, the HBT process CML unit and the emitter follower are adopted for buffering; and the high-precision clock synchronization requirements of JESD204B / C systems such as a 5G base station and a millimeter wave radar can be met.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

An amplifier includes a first amplifier circuit, and a second amplifier circuit that amplifies an output signal of the first amplifier circuit. The first amplifier circuit includes a first divider that divides an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and output an amplified signal as a third signal, a second divider that divide the second signal into a fourth signal and a fifth signal having different phases at a center frequency of an operation band, a first auxiliary amplifier that amplifies the fourth signal and outputs an amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs an amplified signal as a seventh signal, and a hybrid coupler including a first end, a second end, a third end, and a fourth end.

The invention discloses a frequency division frequency modulation control method and system for a power system containing an energy storage unit, and the method comprises the steps: building an energy storage power station comprehensive inertia control model based on an energy storage power station model; considering the influence of energy storage on frequency modulation continuous stability caused by charging and discharging, and establishing a self-adaptive frequency modulation control model considering the energy storage charge state; establishing a frequency response model of the power system based on a balance equation of a wind-light-water-fire power supply, an energy storage unit and a load in the power system; based on the response characteristics of the energy storage unit, establishing a frequency divider model; and comprehensively establishing a frequency control model considering frequency division frequency modulation of the energy storage power supply and other power supplies to realize frequency modulation control of the power system. The frequency modulation advantages that the energy storage unit is high in power supply response speed and can restrain high-frequency fluctuation are brought into play, the frequency response speed of the system is increased, and the frequency response capacity of the system is improved.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

The invention belongs to the technical field of clock chips, and discloses an intelligent calibration multi-channel clock chip system and a control method, the system comprises a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches; the clock output branch comprises a numerical control circuit and a frequency divider which are connected with each other; the initial phase-locked loop is used for receiving an input clock signal, performing frequency multiplication on the input clock signal to obtain a reference clock signal, and sending the reference clock signal to the numerical control circuit of the at least one clock output branch through the selector; and the numerical control circuit is used for eliminating the distributed transmission delay difference in the reference clock signal by adopting a digital compensation algorithm, generating a target clock signal according to the reference clock signal after the delay difference is eliminated, and sending the target clock signal to the corresponding frequency divider. According to the invention, the absolute synchronization error of each clock output branch can be reduced, and the application scene diversity and flexibility of the clock chip are improved.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

An OCC synchronization control system for cross-clock domain path scan testing is disclosed. The system comprises a first OCC and a second OCC, the first OCC is used for controlling test clock output of a first clock domain before frequency division, the second OCC is used for controlling test clock output of a second clock domain after frequency division, the first OCC receives a first high-speed clock signal, and the second OCC receives a second high-speed clock signal; the first OCC and the second OCC share the same group of trigger synchronization logic and are used for processing the synchronous trigger signal crossing the clock domain and providing synchronous control input for respective clock gating units, so that the first OCC and the second OCC generate respective test clock output under the same trigger reference. According to the OCC synchronous control system disclosed by the invention, in a circuit with a clock frequency divider, at least two OCCs are fused to share the same capture to trigger synchronous logic, so that synchronous clock pulse generation of clock domains before and after frequency division is realized, and the test coverage rate of a cross-clock path is improved.

In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

The invention relates to a distortion degree measuring system and method based on correlation operation, and the system comprises a signal source which is a to-be-measured signal source for outputting a mixed waveform comprising a fundamental wave and each harmonic component; the fundamental wave extraction module is used for separating and extracting a fundamental wave component of which the waveform is a single-frequency square wave from the signal to be detected; the phase-locked loop frequency multiplication module is used for receiving the fundamental component and locking and extracting a sine wave signal containing the fundamental component and a harmonic component through a phase-locked loop containing a programmable frequency divider; the correlator module is composed of a multiplier circuit and a low-pass filtering and amplifying circuit, receives a to-be-measured signal serving as an input signal and a sine wave signal serving as a reference signal, and outputs a direct-current component; and the single chip microcomputer is configured with the programmable frequency divider, samples the direct current component output by the correlator module, calculates the relative amplitude and the total harmonic distortion degree of the fundamental wave component and the harmonic component, and outputs the total harmonic distortion degree. The beneficial effects are that the measurement system and the signal processing method are suitable for signal harmonic analysis under a complex harmonic environment and a low signal-to-noise ratio condition, a high-performance processor and a computing power requirement are not needed, and the system takes an analog circuit as a main body and has the advantages of high measurement speed, high accuracy, low system cost and the like.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

A clock circuit, a receiver, and a passive optical communication network system are disclosed. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust the clock frequency of an output clock signal based on a transmission protocol, the clock circuit comprises at least one clock path and a frequency divider, and the at least one clock path comprises a first clock path; wherein the first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and interpolates a conversion signal of the reference clock signal by using the reference clock signal so as to output a multi-phase clock signal; and the frequency divider receives the multi-phase clock signal and performs frequency division on the multi-phase clock signal based on a preset frequency division value, and the preset frequency division value is determined based on a transmission protocol. The clock circuit can be compatible with fast clock switching schemes of data rates of different PON protocols, so that the adaptability and the locking performance of a receiver in a burst mode are improved.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

An electronic interface device is configured for use with associated optics for employing coded light for illuminating a liquid, gaseous, or other analyte or target, such as for measuring or determining a composition or other property of the analyte or target. The arrangement can help enable a far higher level of performance, such as for spectral analysis, imaging, or both. A shared common clock on both the illumination and receive sides of the system can be included, such as together with one or more of reference detection, per-channel wavelength-dependent modulation, multiple concurrent feedback loops at different levels, orthogonal and circulant codes, phase-scrambling to better utilize ADC dynamic range, oversampling, and other signal processing can be provided. Modulation codes can optionally employ a clock divider, such as which can be configured to satisfy one or more specified constraints.

The invention provides an intermediate frequency chip and a clock generation circuit thereof, an intermediate frequency module and a broadband terminal, and the clock generation circuit comprises a phase-locked loop which is used for generating a first clock signal based on a received reference clock signal, the first clock signal is used for representing a clock signal for controlling an analog-to-digital converter to sample in a process of converting an analog signal into a digital signal by the analog-to-digital converter in the intermediate frequency chip; the first frequency divider is used for carrying out frequency division on the first clock signal to generate a second clock signal, and the second clock signal is used for representing a sampling clock signal provided by the intermediate frequency chip to the baseband chip; and the multiplexer is used for outputting a target clock signal based on the received reference clock signal and the second clock signal, and the target clock signal is at least one of the reference clock signal and the second clock signal. According to the clock generation circuit, a plurality of clock generation chips do not need to provide clock signals for the on-chip processor of the baseband chip, so that the cost and complexity of a clock scheme are reduced.

The invention relates to a method and system for an injection locked frequency divider with frequency calibration. In some embodiments, a circuit system may include a series of symmetric stages, where an initial stage in the series is coupled to an input signal having a first plurality of phases and an output stage in the series couples an output signal including a second plurality of phases to a calibration engine, wherein a number of the phases in the output signal increases based at least on a number of the symmetric stages and a number of the first plurality of phases in the input signal. Additionally, the circuitry may include embodiments in which the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include embodiments in which the calibration engine outputs a current provided to the series, where the output current may be based at least on a calibration frequency.

The invention discloses a clock synchronization system. The clock synchronization system comprises a trigger group and a frequency divider group, the trigger group comprises N triggers, and the frequency divider group comprises N frequency dividers; the trigger group receives N paths of clock signals and one path of SYNC pulse signal, the N paths of clock signals are respectively transmitted to the N frequency dividers, and the N paths of pulse signals output by the trigger group are respectively transmitted to the N frequency dividers, N is a positive integer greater than 1, through the technical scheme of the invention, the risk of generating a metastable state can be reduced, and the power consumption can be reduced at the same time.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

The invention relates to the technical field of application of thermal printing heads, in particular to a thermal printing device and a printing method for simplifying gray scale printing and achieving fine gray scale control, and the thermal printing device is provided with an external printing host and a thermal printing head. A PWM modulation unit, a clock unit CLK, a frequency divider, a latch unit LATCH, a printing gating unit STB and a plurality of control units in one-to-one correspondence with a plurality of heating points in the heating resistor are arranged in the printing logic control component, and the printing gating unit STB is used for outputting a current line printing gating control signal to the control units; the PWM modulation unit is used for carrying out pulse width modulation on a printing pulse number mi issued by an external host and outputting heating time pulse signals superposed with different duty ratio pulses to the control unit so as to meet different color development temperature requirements; compared with an existing mode that multiple times of sending of printing data are combined with STB gating, the cost requirement for printer control resources is remarkably reduced on the premise that gray level fine control is met.

The invention discloses a solar spectrum frequency division combined heat and power generation system and an operation method, and relates to the technical field of renewable energy sources, and the method comprises the following steps: S001, building a coupling analysis baseline among irradiation parameters, heat distribution and optical characteristics, collecting the real-time temperature data and light beam wavefront information of a spectrum frequency divider under the condition of sun illumination, and calculating the real-time temperature data and light beam wavefront information of the spectrum frequency divider; and generating an estimated atlas of refractive index gradient distribution based on a thermally induced refractive index change rule. Through heat, light and force coupling control, accurate prediction, real-time identification and dynamic correction of the thermal lens effect are achieved, a closed-loop feedback mechanism is established, stable alignment of photoelectric and photo-thermal paths is guaranteed, the system energy efficiency and operation reliability are effectively improved, and the problems of deviation, energy efficiency reduction and part damage caused by a thermal lens in the prior art are solved.

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

The present invention provides an ultrasonic motor starting device and method based on an index output with high performance, which relates to the field of ultrasonic motor starting. The device includes a two-input AND gate having a first input terminal, a second input terminal and an output terminal, and the first input terminal is T i It is used to input the timing signal, and the second input terminal is connected to the pulse output terminal of the division counter, the output terminal of the AND gate is connected to the input terminal of the D flip-flop, the clock terminal of the D flip-flop is connected to the clock terminal of the division counter, and receives the CLOCK clock, the CLOCK clock is the system clock, the output terminal of the D flip-flop is connected to the clock terminal of the latch, and the input terminal of the latch is i DATA is used to receive the division value, F i The DATA division value is the time length T i The multi-channel data output terminal of the latch is connected to the data input terminal of the frequency divider counter, and the output terminal of the frequency divider counter outputs a SIN driving signal or a COS driving signal. The present invention can improve the safety and reliability of ultrasonic motor starting.

A Global Navigation Satellite System (GNSS) receiver for processing GNSS satellite signals use a quasi-asynchronous sampling frequency grid to process the received signals. The GNSS receiver includes a plurality of RF paths configured to receive Global Navigation Satellite System (GNSS) signals from an antenna and transmit the GNSS signals in a frequency range for digitizing the GNSS signals. A phase-locked loop is configured to generate a clock signal and a plurality of clock dividers are configured to receive the clock signal and divide the clock signal. Each of a plurality of navigation systems receive a clock signal from one of the plurality of clock dividers.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

The invention provides a semiconductor device, a memory system and an operating method thereof. The semiconductor device includes: a delay-locked loop (DLL) configured to output a first correction value corresponding to a single period of a clock; and a duty cycle correction circuit including a frequency divider configured to divide the clock into half to generate a divided clock, delay the divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generate an adjusted clock having a duty cycle of 5: 5 based on the divided clock and the delayed clock. The delay value is adjusted or changed based on the first correction value.

The present disclosure provides an integrated circuit, which includes a divider stage, a frequency trimming stage, a voltage control stage, and a logic stage. The divider stage is configured to generate a first clock signal by dividing a frequency of an input clock signal. The frequency trimming stage is configured to add a first delay to the first clock signal to generate a second clock signal. The voltage control stage is configured to repeatedly adjust a second delay of the second clock signal according to a control signal generated by a feedback path to generate a third clock signal. The logic stage is configured to perform a logic operation according to the first clock signal and the third clock signal to generate an output clock signal.