1021 results about "Frequency divider" patented technology

The invention provides a clock signal generating circuit, a wired communication transceiver and electronic equipment, and the circuit outputs a first DC voltage comprising phase difference information and frequency difference information of a reference clock signal and a feedback clock signal through a phase frequency detection module. The pulse generator generates a narrow pulse signal based on the DC voltage and a reference clock signal, the oscillation frequency of each secondary ring oscillator in the cross-coupled ring oscillator is controlled by the first DC voltage, and the cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross coupling ring oscillator receives the narrow pulse signal, frequency and phase locking is completed in an injection locking mode, and the frequency divider is used for conducting frequency division processing on any high-frequency clock signal and outputting a feedback clock signal. Therefore, a high-frequency multi-phase clock signal with low phase noise and high phase precision can be generated by using the low-frequency reference clock signal.

An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

The invention relates to a phase-locked loop circuit, a clock generator, a chip and electronic equipment, and the phase-locked loop circuit mainly comprises a phase frequency detector which is used for generating a phase detection output signal according to the phase of a reference clock signal and the phase of a feedback clock signal; the proportional path module is used for generating a first control current according to the phase discrimination output signal; the integral path module is used for generating a second control current according to the phase discrimination output signal; the current control oscillation module is used for generating a clock output signal according to the first control current and the second control current; and the feedback frequency divider is used for obtaining a feedback clock signal through frequency division of the clock output signal. According to the phase-locked loop, the advantages of the analog charge pump phase-locked loop and the full-digital phase-locked loop are combined, the generation of a high-performance clock which is small in area, high in bandwidth, stable in loop and low in quantization noise is facilitated, the applicability of the phase-locked loop to the high bandwidth requirement is facilitated, the quantization noise is reduced, and the performance of the phase-locked loop is improved. And unconditional stability of the phase-locked loop is realized theoretically.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

Aspects of the subject disclosure may include, for example, an inner clock generation circuit, including: a selectable frequency divider having: a ring of tri-state inverters; a reset gate on an output of each tri-state inverter in the ring; and a reset circuit comprising one or more selectable flip-flops; and a duty-cycle limiter that generates clock signals having a 25% duty cycle from three out of four quadrature clock signals. Other embodiments are disclosed.

A digital frequency synthesizer includes a delay-locked loop (DLL) that generates time-delayed versions of a reference clock signal, a clock divider that executes an integer-division operation on one delayed clock signal to generate an integer-divided clock signal, and control circuitry that generates fractional data for enabling a fractional division. The digital frequency synthesizer further includes a first clock selector that selects one delayed clock signal as a DLL clock signal based on the fractional data, a delay chain that generates time-delayed versions of the DLL clock signal, and a second clock selector that selects one delayed clock signal as a selected clock signal based on the fractional data. A rising edge of the integer-divided clock signal is adjusted based on the selected clock signal to generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.

The invention relates to a programmable frequency divider applied to JESD204B / C. The programmable frequency divider comprises a prescaler which realizes 1 / 2 / 4 dynamic frequency division through a closed-loop feedback structure; according to the 12-bit main frequency divider, the duty ratio of odd-even frequency division is controlled by a 11-stage asynchronous CML frequency-halving chain and a separation DFF0 module; the frequency dividing ratio N is equal to DIV Nlt; 11: 0gt; 2, the odd number frequency division duty ratio is automatically adjusted to (N + 1) / 2N; the cascade noise optimization comprises the following steps of: resampling by using an input clock fin through a retiming trigger (RetimeDFF1 / 2); according to the pulse generator, the number K of pulses output by a four-stage counter is equal to Pulsecount; 3: 0gt; a decimal value; and the output mode circuit supports three-mode direct connection. According to the programmable frequency divider, the HBT process CML unit and the emitter follower are adopted for buffering; and the high-precision clock synchronization requirements of JESD204B / C systems such as a 5G base station and a millimeter wave radar can be met.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

An amplifier includes a first amplifier circuit, and a second amplifier circuit that amplifies an output signal of the first amplifier circuit. The first amplifier circuit includes a first divider that divides an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and output an amplified signal as a third signal, a second divider that divide the second signal into a fourth signal and a fifth signal having different phases at a center frequency of an operation band, a first auxiliary amplifier that amplifies the fourth signal and outputs an amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs an amplified signal as a seventh signal, and a hybrid coupler including a first end, a second end, a third end, and a fourth end.

The invention discloses a frequency division frequency modulation control method and system for a power system containing an energy storage unit, and the method comprises the steps: building an energy storage power station comprehensive inertia control model based on an energy storage power station model; considering the influence of energy storage on frequency modulation continuous stability caused by charging and discharging, and establishing a self-adaptive frequency modulation control model considering the energy storage charge state; establishing a frequency response model of the power system based on a balance equation of a wind-light-water-fire power supply, an energy storage unit and a load in the power system; based on the response characteristics of the energy storage unit, establishing a frequency divider model; and comprehensively establishing a frequency control model considering frequency division frequency modulation of the energy storage power supply and other power supplies to realize frequency modulation control of the power system. The frequency modulation advantages that the energy storage unit is high in power supply response speed and can restrain high-frequency fluctuation are brought into play, the frequency response speed of the system is increased, and the frequency response capacity of the system is improved.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

The invention belongs to the technical field of clock chips, and discloses an intelligent calibration multi-channel clock chip system and a control method, the system comprises a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches; the clock output branch comprises a numerical control circuit and a frequency divider which are connected with each other; the initial phase-locked loop is used for receiving an input clock signal, performing frequency multiplication on the input clock signal to obtain a reference clock signal, and sending the reference clock signal to the numerical control circuit of the at least one clock output branch through the selector; and the numerical control circuit is used for eliminating the distributed transmission delay difference in the reference clock signal by adopting a digital compensation algorithm, generating a target clock signal according to the reference clock signal after the delay difference is eliminated, and sending the target clock signal to the corresponding frequency divider. According to the invention, the absolute synchronization error of each clock output branch can be reduced, and the application scene diversity and flexibility of the clock chip are improved.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

An OCC synchronization control system for cross-clock domain path scan testing is disclosed. The system comprises a first OCC and a second OCC, the first OCC is used for controlling test clock output of a first clock domain before frequency division, the second OCC is used for controlling test clock output of a second clock domain after frequency division, the first OCC receives a first high-speed clock signal, and the second OCC receives a second high-speed clock signal; the first OCC and the second OCC share the same group of trigger synchronization logic and are used for processing the synchronous trigger signal crossing the clock domain and providing synchronous control input for respective clock gating units, so that the first OCC and the second OCC generate respective test clock output under the same trigger reference. According to the OCC synchronous control system disclosed by the invention, in a circuit with a clock frequency divider, at least two OCCs are fused to share the same capture to trigger synchronous logic, so that synchronous clock pulse generation of clock domains before and after frequency division is realized, and the test coverage rate of a cross-clock path is improved.

The invention relates to a low-jitter charge pump phase-locked loop circuit. According to the circuit, a digital integral path and an analog proportion path are connected behind a phase frequency detector module, and both the digital integral path and the analog proportion path are connected with a combined voltage-controlled oscillator module; the combined voltage-controlled oscillator module is connected to the frequency divider to output a feedback clock signal and input the feedback clock signal to the phase frequency detector again; the combined voltage-controlled oscillator module comprises two voltage-controlled oscillators, one of the voltage-controlled oscillators works when the rate of frequency increasing along with voltage exceeds a linear proportion area, and the other voltage-controlled oscillator works when the rate of frequency increasing along with voltage is lower than the linear proportion area; and the output frequencies of the two voltage-controlled oscillators are processed, nonlinear characteristics are mutually suppressed, and a linear voltage-frequency characteristic is obtained. The linear output can suppress the output jitter problem, thereby further reducing the output jitter problem of the phase-locked loop.

In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

The invention relates to a sensing system based on a surface acoustic wave oscillator. The sensing system comprises two resonators, two oscillating circuits, a temperature controller, a fluid pipeline, a frequency mixer, an amplification function comparator and a frequency divider, the temperature controller, the resonators and the oscillating circuits are arranged on the fluid pipeline, the two resonators are located on the upper side and the lower side of the temperature controller respectively, and the two oscillating circuits are located on the upper side and the lower side of the two resonators respectively; the temperature controller transmits heat to the resonators on the upper side and the lower side through the fluid pipeline, the resonators adjust resonant frequencies according to temperature changes and output different frequencies to the adjacent oscillating circuits, and the two oscillating circuits are connected with the frequency mixer. The mixer outputs a difference frequency signal to the amplification function comparator, and the amplification function comparator outputs a square wave signal to the frequency divider.

The invention relates to a distortion degree measuring system and method based on correlation operation, and the system comprises a signal source which is a to-be-measured signal source for outputting a mixed waveform comprising a fundamental wave and each harmonic component; the fundamental wave extraction module is used for separating and extracting a fundamental wave component of which the waveform is a single-frequency square wave from the signal to be detected; the phase-locked loop frequency multiplication module is used for receiving the fundamental component and locking and extracting a sine wave signal containing the fundamental component and a harmonic component through a phase-locked loop containing a programmable frequency divider; the correlator module is composed of a multiplier circuit and a low-pass filtering and amplifying circuit, receives a to-be-measured signal serving as an input signal and a sine wave signal serving as a reference signal, and outputs a direct-current component; and the single chip microcomputer is configured with the programmable frequency divider, samples the direct current component output by the correlator module, calculates the relative amplitude and the total harmonic distortion degree of the fundamental wave component and the harmonic component, and outputs the total harmonic distortion degree. The beneficial effects are that the measurement system and the signal processing method are suitable for signal harmonic analysis under a complex harmonic environment and a low signal-to-noise ratio condition, a high-performance processor and a computing power requirement are not needed, and the system takes an analog circuit as a main body and has the advantages of high measurement speed, high accuracy, low system cost and the like.

A data conversion apparatus includes a conversion module, a frequency divider module electrically connected to the conversion module, and a clock selection module electrically connected to both the conversion module and the frequency divider module. The frequency divider module is configured to divide an input clock signal to obtain an output clock signal according to a bit-width m of input data and a bit-width n of output data. The clock selection module is configured to transmit the input clock signal and the output clock signal to the conversion module as a write clock signal and a read clock signal, respectively. The conversion module is configured to: receive the input data of m-bit-width according to the wire clock signal; convert the input data into the output data of n-bit-width; and output the output data according to the read clock signal.

The invention relates to a fractional frequency division all-digital phase-locked loop based on a DTC and an edge time domain compensation algorithm, and belongs to the field of radio frequency integrated circuit design. The whole circuit structure comprises a time-to-digital converter (TDC), a digital loop filter (DLF), a digital controlled oscillator (DCO), a programmable frequency divider (MMD), a Sigma-delta modulator and a digital-to-digital converter (DTC). A fractional frequency division function is realized by combining a programmable frequency divider MMD, a Sigma-delta modulator and a digital time converter DTC, a quantization noise optimization circuit is designed mainly by adopting a time domain compensation method, a low fractional spurious effect is realized by combining the DTC, and then signals of fractional frequency division are output and integrated in a phase-locked loop. In a phase-locked loop, a signal output by a Sigma-delta modulator is integrated with a frequency division signal, then a DTC performs time domain compensation according to the signal output by the Sigma-delta modulator, and then transmits the signal to a TDC for phase comparison with a reference signal to control the frequency output of a DCO, so that the high-performance all-digital phase-locked loop circuit with low decimal stray is realized.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

A clock circuit, a receiver, and a passive optical communication network system are disclosed. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust the clock frequency of an output clock signal based on a transmission protocol, the clock circuit comprises at least one clock path and a frequency divider, and the at least one clock path comprises a first clock path; wherein the first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and interpolates a conversion signal of the reference clock signal by using the reference clock signal so as to output a multi-phase clock signal; and the frequency divider receives the multi-phase clock signal and performs frequency division on the multi-phase clock signal based on a preset frequency division value, and the preset frequency division value is determined based on a transmission protocol. The clock circuit can be compatible with fast clock switching schemes of data rates of different PON protocols, so that the adaptability and the locking performance of a receiver in a burst mode are improved.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

An electronic interface device is configured for use with associated optics for employing coded light for illuminating a liquid, gaseous, or other analyte or target, such as for measuring or determining a composition or other property of the analyte or target. The arrangement can help enable a far higher level of performance, such as for spectral analysis, imaging, or both. A shared common clock on both the illumination and receive sides of the system can be included, such as together with one or more of reference detection, per-channel wavelength-dependent modulation, multiple concurrent feedback loops at different levels, orthogonal and circulant codes, phase-scrambling to better utilize ADC dynamic range, oversampling, and other signal processing can be provided. Modulation codes can optionally employ a clock divider, such as which can be configured to satisfy one or more specified constraints.

The invention provides an intermediate frequency chip and a clock generation circuit thereof, an intermediate frequency module and a broadband terminal, and the clock generation circuit comprises a phase-locked loop which is used for generating a first clock signal based on a received reference clock signal, the first clock signal is used for representing a clock signal for controlling an analog-to-digital converter to sample in a process of converting an analog signal into a digital signal by the analog-to-digital converter in the intermediate frequency chip; the first frequency divider is used for carrying out frequency division on the first clock signal to generate a second clock signal, and the second clock signal is used for representing a sampling clock signal provided by the intermediate frequency chip to the baseband chip; and the multiplexer is used for outputting a target clock signal based on the received reference clock signal and the second clock signal, and the target clock signal is at least one of the reference clock signal and the second clock signal. According to the clock generation circuit, a plurality of clock generation chips do not need to provide clock signals for the on-chip processor of the baseband chip, so that the cost and complexity of a clock scheme are reduced.

An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

The invention relates to a method and system for an injection locked frequency divider with frequency calibration. In some embodiments, a circuit system may include a series of symmetric stages, where an initial stage in the series is coupled to an input signal having a first plurality of phases and an output stage in the series couples an output signal including a second plurality of phases to a calibration engine, wherein a number of the phases in the output signal increases based at least on a number of the symmetric stages and a number of the first plurality of phases in the input signal. Additionally, the circuitry may include embodiments in which the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include embodiments in which the calibration engine outputs a current provided to the series, where the output current may be based at least on a calibration frequency.

The invention discloses a clock synchronization system. The clock synchronization system comprises a trigger group and a frequency divider group, the trigger group comprises N triggers, and the frequency divider group comprises N frequency dividers; the trigger group receives N paths of clock signals and one path of SYNC pulse signal, the N paths of clock signals are respectively transmitted to the N frequency dividers, and the N paths of pulse signals output by the trigger group are respectively transmitted to the N frequency dividers, N is a positive integer greater than 1, through the technical scheme of the invention, the risk of generating a metastable state can be reduced, and the power consumption can be reduced at the same time.

The utility model discloses a frequency offset error control device for the distance measurement of a responder, and mainly solves the problem that the modulation frequency offset error is increased in the prior art. The system comprises a transmitting channel, a receiving channel, a frequency synthesizer source module, a ramp generator loop module and a high frequency mixing module. The frequency synthesizer source module outputs in two paths, one path is connected with the ramp generator loop module through a first power divider, a frequency divider and a second power divider, and the other path is connected with the high frequency mixing module through the first power divider, a first filter and a frequency multiplier; the slope generator loop module is connected with the high frequency mixing module through the low frequency mixer and the third filter; the high frequency mixing module mixes the signal output by the frequency multiplier and the signal output by the third filter and then inputs the mixed signal to a transmitting channel for transmission; and the receiving channel receives a transmitted signal and outputs a constant difference frequency signal for distance measurement. According to the utility model, the modulation frequency offset error of the linear frequency modulation signal can be reduced, the frequency stability of the transmitted signal can be improved, and the device can be used for distance measurement based on the linear frequency modulation continuous wave signal responder.