75 results about "Digital delay line" patented technology

A clock generator including a frequency multiplier, a phase lock circuit and a frequency divider. The frequency multiplier generates a frequency multiplied clock by multiplying the frequency of an input clock. The phase lock circuit detects a phase difference between the input clock and a frequency divided clock, and generates, by delaying the frequency multiplied clock by an amount corresponding to the phase difference, a phase-locked clock with its phase locked with the input clock. The frequency divider detects in every fixed cycle a particular pulse of the phase-locked clock, and generates the frequency divided clock by dividing the phase-locked clock with reference to the particular pulse of the phase-locked clock. In particular, the frequency divider detects the particular pulse immediately previous to a falling edge of the input clock. This can reduce the phase difference between the input clock and the phase-locked clock, and hence to solve a problem of a conventional clock generator in that a delay time of a digital delay line in a phase lock circuit must be lengthened with a reduction in the multiplication number of the frequency multiplied clock, which requires a greater number of delay elements because of a large occupying area of the delay elements and a decoder, thereby increasing the circuit scale and cost of a chip to reduce the multiplication number of the frequency multiplied clock.

This invention relates to a measuring method and device of impulse form. The invention includes one constant proportion timing discriminate module and one time-to-digital conversion module. Data of time-to-digital conversion modular enter calculator for handling. Constant proportion timing discriminate module has a group of leading edge discriminator and a group of back edge discriminator, which separately discriminate a series of points where the ratio of pulse front edge and back edge voltage and spike voltage are certain worth corresponding time. multipass time-to-digital conversion module convert time interval between first time and subsequently time to digital quantity, adopt digital counting method and combine digital delay line bracketing method, realize at a piece of field programmable logic array FPGA. sending obtained data into computer for calculation to gain time interval, base on voltage peak ratio of every time to indirectly reduce impulse form, and obtain pulsewidth. The invention has low cost, small bulk, and light weight, can apply to laser range finder.

The invention provides a digital PLL (Phase-Locked Loop) based phase noise measuring device. The digital PLL based phase noise measuring device comprises a frequency power measuring unit, a phase discrimination unit, a filtering unit, a DC (Direct Current) bias compensation unit, a low-noise amplification unit, an acquisition, frequency discrimination and phase discrimination unit, a digital loop filtering unit, a phase discrimination constant detection unit, a self-adaptive digital gain control unit, a reference source unit, and a signal processing and displaying unit. According to the digital PLL based phase noise measuring device, a double-balanced mixer is adopted as a phase discriminator, the phase noise of a measured source is extracted through a digital PLL, the specific noise extraction mode is divided into frequency mixer phase discrimination and digital delay line frequency discrimination, and DC caused by a loop circuit is counteracted through a DC bias compensation circuit, so that too big DC after amplification, induced ADC saturation and induced loop lock-losing are prevented. The implementation scheme of the digital PLL based phase noise measuring device is simple, totally excellent phase noise measuring sensitivity can be realized, the realized analysis frequency spectrum range is also very wide, and phase noise testing demands of most signal sources can be satisfied.

A variable digital delay line with an insertion delay as low as a single delay element yet capable of providing a large programmable delay with a small simple control mechanism. A loop connects an input to an output through selectable first delay elements such as 2:1 muxes and selectable second delay elements such as pairs of inverters by way of a plurality of intermediate nodes having a tap. A plurality of sneak paths are available wherein the loop by passes a remainder of first delay elements and/or second delay elements by way of the taps at the intermediate nodes.

The invention relates to a digital delay phase locked loop circuit. In the circuit, a clock frequency divider and an initial delay control circuit are added; meanwhile, a shift register is improved; each delay unit of a digital delay line is controlled by an output signal of the improved shift register; a phase discriminator compares the phase of an input clock CLKIN and the phase of a delayed output clock CLKOUT; shift of the improved shift register is controlled according to a phase comparison result; the initial delay control circuit measures delay time from the input clock CLKIN to the output clock CLKOUT when started and then generates a setting signal to set the improved shift register; and the input clock CLKIN is output to serve as the input clock for the improved shift register after the frequency is divided by the clock frequency divider. The circuit solves the problems of slow locking speed and error locking of the conventional DLL structure, has a wider frequency range and is favorable for improving chip yield.

An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading. The DDL additionally comprises a decoder to generate a digital signature from the digital reading and a controller to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.

A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay line very robust pattern fault coverage. The XOR gate may consist of three current limiting inverters. A reference voltage generator generates constant voltages between a source voltage, bias voltages, and ground. These constant voltages decide the amount of current through the current limiting inverters. Selecting a different set of reference voltages programs a different current flowing in the current limiting inverters. This programmable current causes a programmable unit delay to be introduced by each XOR gate delay element.

The invention provides a co-channel interference processing system for a pulse coherent answering machine, which can solve the self-excitation problem of co-channel interference of a pulse coherent answering machine and ensure the working stability of the answering machine. The method is achieved by the following technical scheme that after the pulse answering machine antenna receives a radio frequency signal, the radio frequency signal FR enters a field amplifier module through a circulator, after the signal is filtered and amplified by the field amplifier module and then controlled by a microwave switch, the controlled radio frequency signal is mixed with a local oscillation signal to output an intermediate frequency signal, the intermediate frequency is amplified and detected by a middle amplifier module and then sent to a digital circuit module for A / D acquisition, a collected signal is stored and transmitted through a digital delay line, the timing control of the digital delay line is controlled by a sending and receiving timing control circuit, a forwarding signal is sent to a D / A converter for outputting an intermediate frequency signal which is subjected to up conversion by a transmitting channel module and then amplified by a power amplifier module, and an amplified signal FT is output by the circulator. The system solves the self-excitation problem of pulse transmit-receive same frequency.

A configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM. The DLL design and technique disclosed employs a hybrid analog/digital delay line, but does not use conventional closed loop architecture during the digital phase of the locking process.

The invention discloses a broadband beam forming method based on a multi-stage filter bank, and provides a multi-stage filter bank method to realize the delay compensation of broadband signals from the perspective of saving hardware resources and practical application according to the design difference of various delay filters. The method aims at fractional time delay filtering compensation, integer time delay can be compensated by adopting a digital delay line method, and accurate time delay compensation can be realized by carrying out hierarchical filtering on each array element receiving signal of an array. Through the structure of the multi-stage filter bank provided by the invention, the delay filtering time is realized. Due to the fact that the filtering coefficients of all sets of delay filters are only related to the sampling period of the signal, only a small number of filtering coefficients need to be stored, the whole filter bank can be designed in advance to be stored, real-time calculation of the coefficients is avoided, and the method has important value in practical application.

A delay line circuit and method to delay digital data in a main memory is provided. The delay line circuit may comprise primary delay line cache, secondary delay line cache, and a cache controller to control communication of data between the secondary delay cache and the primary delay cache. The primary delay line cache may receive digital data to be delayed from a signal processor module, and secondary delay line cache may be connected to the primary delay line cache and the main memory to send data to and receive delayed data from the main memory. Data in the secondary delay line cache may be updated with data from the main memory or with data from the primary delay line cache. The invention extends to a machine-readable medium comprising a set of instructions for executing any of the methods described herein.

The invention provides a fixed target protection-based satellite navigation signal repeater deception jamming system and a method thereof. The system comprises multiple satellites, multiple repeaters, a real target point and a set false target point, wherein the number of the repeaters is the same as that of the satellites, one repeater receives navigation satellite signals broadcasted by one satellite, the multiple repeaters receive navigation satellite signals broadcasted by multiple satellites respectively and time delay of the multiple repeaters is controlled respectively through a digital delay line technology, the multiple navigation satellite signals after certain time delay are broadcasted via the multiple repeaters respectively, and thus, an enemy weapon guided by using the navigation satellite signals in an effective jamming area is further deceived to deviate from the real target point and advance to the set false target point. The problem that the traditional repeater deception can not handle receiver inertial navigation detection can be solved, and an important role is played in protecting a fixed important target.

A method and a digital processor circuit to process digital delays are provided. The digital processor circuit may comprise circuit memory and a processor module such as a digital signal processor (DSP), a delay line module, a filter module and a sample rate converter module. The circuit memory may comprise a digital delay line memory portion to provide a plurality of digital delay lines; and a cache memory portion to perform a pre-fetch data transfer operation from the main memory to the cache memory portion. The cache memory portion may comprise a plurality of delay caches that are updated with data samples from corresponding delay lines in the main memory. The sizes (e.g., the relative sizes) of the delay line memory portion and the cache memory portion of the circuit memory may be adjustable. The sizes may be dependent upon algorithms executed by the processor module.

The invention relates to a full-waveform digital detection device comprising a constant fraction timing module, a time digital conversion module, a data interface module and a data storage module. A leading-edge discriminator set and a lagging-edge discriminator set of the constant fraction timing module discriminates that amplitude ratio of voltage, at pulse leading edge and pulse lagging edge, and peak voltage is a series of point corresponding moments of certain values. By integrating the digital counting method and digital delay line interpolation method, the time digital conversion module converts time intervals between the first time and each of the rest time into digital values so as to acquire data, then the data is sent to the data storage module through the data interface module. Implementation of the time digital conversion module and the data interface module is facilitated on an FPGA (field programmable gate array). The full-waveform digital detection device has the advantages such as high precision, integration and low cost and is applicable to the three-dimensional imaging laser scanner.

A digital delay line includes a plurality of hysteresis-based delay cells electrically connected in series. These hystersis delay units in the hysteresis-based delay cells may be similar or different. All of the hysteresis delay units respectively have an inverter mode and a hesteresis mode. The delay and resolution of the hysteresis delay unit may be derived from the time difference in the inverter mode and hysteresis mode. Such a digital delay line applied to a digital phase locked loop may reduce consumption of area and power.

The invention discloses a power equalization method and a modulator for modulation of a specific harmonic elimination multilevel radio frequency pulse width. The method comprises the steps of: decomposing a specific harmonic elimination multi-level RF-PWM signal into a plurality of 3-level RF-PWM signals with equal pulse areas by using the area equivalence principle based on a multi-level radio frequency pulse signal output from the specific harmonic elimination multi-level RF-PWM, according to the rise and fall of the pulse outputting the multi-level RF-PWM signal; driving a rear-stage SMPA unit, so that multi-level RF-PWM output pulse sequence specific harmonics are eliminated, while achieving the power equalization between the rear-stage SMPA units and between the power tubes in the unit. The radio frequency pulse width modulator is based on the power equalization method, and generates a phase shift control signal for driving a rear-stage 5-level SMPA unit by using a digital delay line unit, thereby realizing active cancellation of a 3X times specific harmonic. The power equalization method for modulation of a specific harmonic elimination multilevel radio frequency pulse widthdoes not need an additional power equalization control circuit, which simplifies the modulator structure.