41 results about "Digital clock" patented technology

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

The invention provides a data life cycle autonomous management method and system based on source data feature perception. The method comprises the following steps: defining a basic attribute of target data in the storage system as a triple theta = (t, l, i); establishing a mapping protocol of the source data and the target data; monitoring the change frequency omega of the source data in real time, and executing the following cycle matching algorithm: setting that the life cycle variable and the change frequency of the source data meet an inverse relation t = k / omega, shortening t to improve the sampling precision of the digital clock when omega is increased, and prolonging t to reduce the sampling precision when omega is reduced; and automatically converting the calculated life cycle variable value into a control instruction. According to the method, the data life cycle can be converted into a dynamically programmable variable, low-power-consumption and high-precision response can be realized through hardware acceleration, or a flexible and low-cost management scheme can be realized through software scheduling.

1. Name of the product in this design: Graphical User Interface for a Digital Clock in Electronic Devices. 2. Purpose of this design: An electronic device. 3. The key design feature of this product is its graphical user interface. 4. The image or photograph that best illustrates the design's key features: the front view. 5. Purpose of the graphical user interface: This graphical user interface is used for displaying primary / secondary time zones, monitoring environmental data, and providing schedule reminders. 6. Human-computer interaction methods of graphical user interface: Click to exit the main view; long press the main time zone area to enter the settings interface (modify the time zone, calibrate the time alarm, etc.); swipe left on the main view to turn pages and switch time zones, then swipe right to return to the main view; swipe right on the main view to enter the alarm settings page; swipe down on the main view to enter the settings menu interface (screen brightness, button layout).

The invention relates to the technical field of digital clock signal processing, in particular to a clock frequency detection system and method based on clock edge alignment detection, and the system comprises a working state monitoring module, a sampling period counting module, a clock sampling module, a state judgment and change module, and an index generation and output module. A signal of the system in a normal working state is released through the working state monitoring module, a high-frequency clock signal is input to the working state monitoring module, and the system controls a sampling period through a low-frequency clock, periodically samples the high-frequency clock, counts the number of high levels in the sampling period and judges the state change of the high-frequency clock. And judging that the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, and outputting a corresponding phase index value. The device is realized by adopting pure digital logic, has anti-jitter capability, can accurately identify the phase of the high-frequency clock, and has the advantages of simple structure, high precision and strong transportability.

The invention discloses a clock display method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of electronic equipment. The method comprises the steps that an interface comprising a digital clock of a first display form is displayed, if a touch operation acting on the digital clock of the first display form is detected, a clock selection panel is displayed on the interface, the clock selection panel comprises digital clocks of multiple display forms, the multiple display forms comprise the first display form, and the first display form is a touch operation acting on the digital clock of the first display form. If a touch operation acting on a digital clock of a second display form in the clock selection panel is detected, the digital clock of the first display form is switched into the digital clock of the second display form in the interface, and the second display form is any one of the multiple display forms except the first display form. According to the invention, the digital clock with multiple display forms is designed and provided for the user to select and set, so that the user-defined layout experience and interaction experience of the user are ensured.

The application provides a digital clock jitter measurement circuit and a measurement method. The measurement circuit comprises a delay module, which receives a clock signal to be measured and generates a first clock signal and a second clock signal, and the phase difference between the first clock signal and the second clock signal is one clock cycle; a measurement module, which comprises a sampling unit, an oscillator control unit, a measurement unit and a counter unit. The measurement unit comprises a slow-frequency oscillator, an intermediate-frequency oscillator and a high-frequency oscillator, and a first edge detector and a second edge detector, the first edge detector being connected with the slow-frequency oscillator and the intermediate-frequency oscillator, and the second edge detector being connected with the intermediate-frequency oscillator and the high-frequency oscillator. The clock jitter measurement circuit and the measurement method provided by the application can automatically select a matched oscillator according to the phase relationship between the first clock signal and the second clock signal, thereby realizing automatic measurement of clock jitter.

The invention discloses a circuit and method for resisting white noise interference of an ultrasonic water meter. The circuit comprises a transmitting end ultrasonic transducer, a transmitting coding circuit, a digital clock chip, a microprocessor unit, a receiving coding circuit and a receiving end ultrasonic transducer. The digital clock chip is connected with the transmitting end ultrasonic transducer through the microprocessor unit and the transmitting coding circuit in sequence; the microprocessor unit is connected with a receiving end ultrasonic transducer through a receiving coding circuit in sequence; the digital clock chip is respectively connected with the transmitting end ultrasonic transducer, the transmitting coding circuit, the receiving coding circuit and the receiving end ultrasonic transducer. The white noise interference resistance of the ultrasonic water meter is improved.

The invention discloses a slope calibration method of a driving circuit, a circuit, a chip, equipment and a readable storage medium, and the method comprises the steps: enabling a frequency-adjustable oscillator in a slope calibration stage, and measuring the output clock frequency of the oscillator, the output clock frequency being adjusted by a calibration code; based on a comparison result of the output clock frequency and a target frequency range, adjusting a calibration code to calibrate the output clock frequency to the target frequency range, and obtaining a corresponding target calibration code; and applying the target calibration code to the driving circuit to calibrate an output signal slope of the driving circuit. According to the application, the slope of the output signal of the analog drive circuit can be indirectly, accurately and efficiently calibrated by measuring and calibrating the frequency of the digital clock, and the problems of sensitive load configuration, large influence of parasitic parameters of a test board, harsh measurement precision requirements, long test time and the like existing in direct slope measurement are avoided.

The invention provides a digital clock recovery system and method, and relates to the technical field of digital signal processing. The system comprises an interpolator, a timing error detector, a loop filter and a numerically controlled oscillator which form a feedback loop. Wherein the interpolator is a polynomial interpolator and is used for obtaining an interpolation result or an intermediate value by inquiring a pre-calculation module so as to reduce the operation complexity; a digitally controlled oscillator determines a base point and a fractional interval for interpolation by operating bits on an internal phase accumulator value to avoid division operations. The method comprises the following steps: performing polynomial interpolation by querying a pre-calculation module; detecting a timing error; filtering the error; and updating the timing information by performing a bit operation on the phase accumulator value. By means of the scheme, unification of high precision and low delay is achieved, loop performance is improved, and system resource consumption is reduced.

1. Name of the product in this design: Socket with table lamp (digital clock version). 2. Purpose of this design: A multi-functional socket for providing lighting. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

Certain aspects of the present disclosure provide a relatively compact frequency- locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

The invention relates to the technical field of visible light communication, and provides an optical wireless FDM signal generation method and system for LIFI, and the method comprises the steps: receiving a unique clock signal and a to-be-transmitted digital bit stream through an FPGA, and generating multiple paths of synchronous digital clock signals based on the clock signal; distributing a digital bit stream to be transmitted to a corresponding FDM channel in the FPGA, and performing synchronization processing by using a digital clock signal; modulating a to-be-transmitted digital bit stream of each FDM channel to a corresponding subcarrier frequency to obtain multiple paths of digital domain FDM signals, and performing filtering and superposition processing on the multiple paths of digital domain FDM signals to obtain multiple paths of analog signals; and combining the multiple paths of analog signals in an analog domain to obtain a composite analog signal, and inputting the composite analog signal into an LED to emit a composite light FDM signal. According to the scheme, the problems of high hardware complexity, large PAPR and difficult channel synchronization in the existing LiFi system are solved.

A method, system, and apparatus for digital clock and data recovery (CDR) with analog signal that samples blindly (i.e., independent of the baud rate). The CDR further has a digital monolithic circuit that includes an interpolator circuit, and a fully digital clock (FDC) that recovers the digital data from the analog signal.

A level shift assembly, a method for over-current protection, and a display apparatus. The level shift assembly includes a level shift module, which includes a control unit, a current detection unit, a level shift unit, and an over-current protection unit. The controller determines, at a first falling edge of a digital clock signal, a first analog clock signal among a plurality of analog clock signals which corresponds to the first falling edge based on a correspondence of a current display mode; the current detection unit detects a current of the first analog clock signal; and a moment, at which a falling edge of the digital clock signal is present, is within a last line of a corresponding analog clock signal, and an over-current signal is sent to the over-current protection unit when the current of the first analog clock signal is not within a current threshold range.

For example, an apparatus may include a digitally-controlled frequency multiplier, which may be controllable according to a digital control input, to generate an output frequency signal having an output frequency, for example, by multiplying an input frequency of an input frequency signal. For example, the digitally-controlled frequency multiplier may include a phase generator configured to generate a plurality of phase-shifted signal groups corresponding to a respective plurality of first phase-shifts applied to the input frequency signal, a plurality of digital clock multipliers controllable according to the digital control input to generate a respective plurality of frequency-multiplied signals based on the plurality of phase-shifted signal groups, and a combiner to generate the output frequency signal based on a combination of the plurality of frequency-multiplied signals.

A rate estimator circuit is provided for adjusting the sampling rate filter of a sampling rate converter circuit. The rate estimator circuit includes a first integrator clocked by a first clock signal having a first sampling frequency and a second integrator clocked by a second clock signal having a second sampling frequency; a resolution upscaling circuit including a third integrator clocked by a system clock signal; a digital clock multiplier circuit including the second integrator and a multiplier loop circuit having a fourth integrator; a multiplier output stage connected to the output of the fourth integrator; and a rate estimator circuit including the first integrator and an estimator loop circuit having a fifth integrator.

1. Name of the product in this design: Graphical User Interface for a Digital Clock in Electronic Devices. 2. Purpose of this design: An electronic device. 3. The key design feature of this product is its graphical user interface. 4. The image or photograph that best illustrates the design's key features: the front view. 5. Purpose of the graphical user interface: This graphical user interface is used for displaying primary / secondary time zones, monitoring environmental data, and providing schedule reminders. 6. Human-computer interaction methods of graphical user interface: Click to exit the main view; long press the main time zone area to enter the settings interface (modify the time zone, calibrate the time alarm, etc.); swipe left on the main view to turn pages and switch time zones, then swipe right to return to the main view; swipe right on the main view to enter the alarm settings page; swipe down on the main view to enter the settings menu interface (screen brightness, button layout).

In one aspect, an apparatus includes: radio frequency (RF) circuitry to transmit and receive RF signals, the RF circuitry to operate with a local oscillator (LO) clock signal; clock circuitry to receive the LO clock signal and generate an LO-derived clock signal therefrom; first digital circuitry to communicate data according to a first digital clock signal; and a controller coupled to the first digital circuitry to select one of the LO-derived clock signal or a source clock signal to provide to the first digital circuitry as the first digital clock signal.

The application discloses an ASK 100% modulation communication system and method applied to a passive NFC tag. The application generates a recovered clock signal by introducing a high-precision digital control oscillator circuit, uses a carrier clock signal for timing control in a signal receiving process of the NFC tag, and switches to the recovered clock signal for timing control in a signal sending process, so that the passive NFC tag has a stable clock source during clock loss of ASK 100% modulation, and the normal work of a digital circuit can be ensured. Meanwhile, the application also introduces a digital clock calibration circuit, has relatively small area and power consumption under the premise of ensuring calibration frequency, and is more suitable for the development trend and requirement of low power consumption and low cost of the passive NFC tag. The application realizes the communication of the passive NFC tag with a PCD by using ASK 100% for load modulation, greatly improves the anti-interference ability of a signal, can optimize the requirement for a minimum antenna coupling coefficient k, optimizes the geometric alignment requirement of an antenna, and improves the long-distance communication ability of the tag.

The invention provides a digital clock data recovery circuit and method. The digital clock data recovery circuit comprises an analog-to-digital converter used for sampling an analog input signal under the control of a sampling clock signal and converting the sampled signal into a digital signal; the error detector is used for carrying out phase error detection according to the digital signal to obtain a phase error estimation value; the frequency deviation detector is used for acquiring a frequency deviation estimation value according to the phase error estimation value; the loop filter is used for filtering according to the phase error estimation value and the frequency deviation estimation value and outputting a filtering signal; the phase code generator is used for generating a phase code according to the filtering signal; and the phase interpolator is used for generating the sampling clock signal according to the phase code so as to control the sampling phase of the analog-to-digital converter. The digital clock data recovery circuit can quickly capture clock frequency deviation.

In one embodiment, a syntonization system includes a device including a dedicated clock signal input interface to be connected by a clock connection to a remote device and to receive a remote clock signal from the remote device, the remote device being external to the device, and clock circuitry to generate a local clock signal, and a digital clock controller to generate digital control signals to control the clock circuitry to syntonize the local clock signal according to the remote clock signal based on a difference between frequencies of the remote clock signal and the local clock signal, and provide the digital control signals to the clock circuitry, wherein the clock circuitry is to adjust the frequency of the local clock signal based on the digital control signals.

The application provides a satellite broadcast audio clock synchronization method, device, medium and product, relates to the technical field of digital clock synchronization, and the method comprises the steps of extracting a PCR time stamp from a satellite TS stream and decoding PCM audio data; calculating the difference between the PCR time stamp and a local numerical control oscillator counter as a time error value; inputting the time error value into a PI controller for proportional integral operation, and performing smoothing processing on the output of the PI controller through an IIR low-pass filter to obtain a frequency adjustment amount; writing the frequency adjustment amount into the local numerical control oscillator to adjust the frequency, so that the restored PCR clock signal is obtained through convergence; phase-locked frequency division of the restored PCR clock signal to generate an audio output clock signal, and synchronization output of the PCM audio data is realized based on the audio output clock signal. The problem that loud noise and broken noise are prone to occurring during master-backup switching due to large clock restoration jitter when the existing satellite broadcast receiving device operates independently without external synchronization source is solved.

1. The name of the design product: socket (T32 digital clock USB). 2. The use of the design product: for socket. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: design 1 perspective view. 5. Design 1 is designated as the basic design.

The present invention provides a method and system to correctly sample, at a central location, a signal at a second clock frequency from a remote antenna when the signal is at a first clock frequency. The present invention provides an improved method of incoherent clocking to correctly sample a signal from a remote antenna at a clock frequency of a central location, such as a central site of a radio telescope array. The signal contains a “tracer” which is related to the frequency of the remote antenna. The tracer phase is written into a dual-port memory at the first clock frequency and then read from the memory at the second clock frequency. The tracer phase is transferred across digital clock domains using Gray-doe methods so that phase coding errors do not occur.

A circuit and a method for digital clock data recovery are provided. The circuit comprises an analog-to-digital converter, an error detector, a frequency deviation detector, a loop filter, a phase code generator, and a phase interpolator. The analog-to-digital converter samples an analog input signal under the control of a sampling clock signal to obtain a sampled signal, and converts the sampled signal into a digital signal. The error detector performs phase error detection based on the digital signal to obtain phase error estimation values. The frequency deviation detector obtains a frequency deviation estimation value based on the phase error estimation values. The loop filter filters and outputs a filtered signal based on the phase error estimation values and the frequency deviation estimation value. The phase code generator generates a phase code based on the filtered signal. The phase interpolator generates the sampling clock signal based on the phase code.

The invention relates to a digital clock generation circuit capable of realizing fast frequency calibration, comprising a digital RC oscillator which is provided with a control bus input end and a clock signal output end and is used for generating a digital clock signal CKOSC according to an input control value RFT; the frequency divider is provided with a control bus, a clock signal input end and a clock signal output end, and is used for carrying out frequency division on the CKOSC according to an input control value NFT to generate a final digital clock output signal CKO; the counting sampling module is provided with a first clock signal input end, a second clock signal input end, a data bus and a trigger signal output end, and is used for counting edges of the CKO and outputting a counting value SMP and a trigger digital signal CKSMP under the driving of the reference clock signal CKP; and the frequency calibration module is provided with a clock signal, a trigger signal, a data bus input end and at least two control bus output ends, and is used for calculating adjustment amounts of the RFT and the NFT according to the SMP and a preset target count value CN, and adjusting the RFT and the NFT according to the triggering of the CKSMP so as to calibrate the frequency of the final output CKO.

The invention provides a digital clock phase measurement method and system based on a direct sampling technology, and the method comprises the steps: triggering a first counter based on the edge of a first to-be-measured clock signal, sampling a value signal of the first counter through a preset sampling clock signal, and taking the value signal as a first timestamp signal, the first timestamp signal is used for representing the phase of the first to-be-measured clock signal; triggering a second counter based on the edge of a second to-be-tested clock signal, and sampling a numerical value signal of the second counter by using the sampling clock signal as a second timestamp signal; based on the first timestamp signal and the second timestamp signal, the difference value of the numerical value signals of each sampling point is calculated, the phase difference value of the first to-be-tested clock signal and the second to-be-tested clock signal of each sampling point is obtained, and the symbol of the phase difference value represents a phase leading relation; and performing statistical analysis on the calculated phase difference value, and determining the phase difference between the first to-be-tested clock signal and the second to-be-tested clock signal according to a statistical analysis result.

A sleep training clock can be configured to assist in sleep training. The sleep training clock is shaped like a robot having a face, a torso, and two legs; two LEDs disposed in the face and three LEDs disposed in the torso; and a digital clock face disposed in the torso. Additionally, circuitry for performing sleep training is configured to determine whether the electronic device is in a wake state and turn on the two LEDs disposed in the face and turn off the three LEDs disposed in the torso in response, determine whether the electronic device is in a sleep state and turn off the two LEDs disposed in the face and turn on the three LEDs disposed in the torso in response.

This application provides a digital clock jitter measurement circuit and method. The measurement circuit includes: a delay unit comprising an edge detection unit and multiple coarse-grained delay units and multiple fine-grained delay units connected in series; the delay units receive a signal to be measured and generate a first clock signal and a second clock signal; an adjustment control unit configured to adjust the delay of the second clock signal by controlling the coarse-grained and fine-grained delay units; and a measurement unit comprising a first ring oscillator, a second ring oscillator, a phase detector, and a counter. The clock jitter measurement circuit and method provided in this application can accurately measure clock jitter integrated within a chip, avoiding the inconvenience of requiring large instruments in existing technologies.

To provide a physical layer device and method for selecting a sample phase of a signal.SOLUTION: A physical layer device 1000 includes: sampling circuitry 1006 configured to receive a signal 1002, which may be delivered to an input 1004 of the physical layer device 1000 from a shared transmission medium 106, and measure sample values 1008 at a plurality of different sample phases 1022; an edge detector 1010 configured to determine an edge sample phase 1012 of the different sample phases corresponding to an edge of a symbol, based on the sample values; a center detector 1014 configured to determine a center sample phase 1016 of the different sample phases, based on the determined edge sample phase; and sampling circuitry 1018 configured to determine center sample values 1020 using the determined center sample phase.SELECTED DRAWING: Figure 10