81 results about "Digital clock" patented technology

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

The invention provides a digital clock remote metering method based on network delay suppression, which comprises the following steps of: constructing a layered synchronous architecture, deploying a main clock source, a plurality of regional clock servers and a plurality of terminal devices, connecting the plurality of regional clock servers with the main clock source through optical fiber special lines to obtain reference time, each regional clock server is connected with a plurality of terminal devices through a 5G / industrial Ethernet to form a three-level synchronous network; rTT data of the terminal device and a regional server are obtained through bidirectional timestamp interaction, and message screening is carried out according to a preset rule; calculating a final time delay compensation value by adopting a mixed time delay compensation algorithm, and calibrating a terminal clock by adopting the final time delay compensation value; and adopting a time selection algorithm to obtain an optimal reference source for data synchronous analysis. According to the invention, the time deviation problem between the current time indicating value of the digital clock and the standard time and the data synchronization analysis problem can be solved.

A level conversion assembly (50), an overcurrent protection method and a display device, the level conversion assembly (50) comprising a level conversion module (51), the level conversion module (51) comprising a control unit (511), a current detection unit (512), a level conversion unit (513) and an overcurrent protection unit (514). When a control unit (511) is at a first falling edge of a digital clock signal (CPV), a first analog clock signal corresponding to the first falling edge in a plurality of analog clock signals (CLK1-CLK8) is determined based on the corresponding relation of the current display mode, and a current detection unit (512) is controlled to detect the current of the first analog clock signal. Since the moment of the falling edge of the digital clock signal (CPV) is located in the last row of the high level period or the low level period in the corresponding analog clock signal, the current detection unit (512) can send an overcurrent signal to the overcurrent protection unit (514) when the current of the first analog clock signal is not located in the current threshold range. The effect of improving the accuracy of over-current phenomenon detection is achieved.

The invention relates to an improved ABSPD clock recovery method under single Baud rate sampling, clock synchronization of receiving and transmitting end signals is realized through a clock recovery loop based on a full number font, and when a provided timing error detector calculates a timing error e, symbol judgment and shift operation are used for replacing numerical multiplication; after a timing error e is calculated by the timing error detector, the timing error e is input into a loop filter for noise filtering, and a control word W is obtained; controlling the numerically controlled oscillator by using the control word W, and calculating a fractional interval mu k according to the output NCO of the numerically controlled oscillator and the control word W; and carrying out interpolation on the received signal in an interpolation filter by utilizing the integer mark mk of the symbol and the calculated fractional interval mu k so as to calculate and obtain data with correct timing. According to the invention, ABSPD clock recovery under single Baud rate sampling without multiplication operation is realized, and the complexity of the whole clock recovery loop is obviously reduced.

The invention relates to a digital array antenna and digital circuit synchronization method, device, equipment and medium, and the digital array antenna and digital circuit synchronization method comprises the steps: carrying out the module preprocessing of a master module and a slave module, and the module preprocessing comprises the configuration of FPGA codes for the master module and the slave module and the initialization of a radio frequency transceiver; the master module triggers a module handshake request to the slave module, and obtains a signal receiving state of the slave module according to the module handshake request; the master module sends a synchronous trigger signal, a synchronous pulse generator is triggered to generate a synchronous pulse signal, and the master module and all the slave modules perform radio frequency transceiver local oscillator phase synchronization through a clock signal and a first pulse of the synchronous pulse signal; and the master module and all the slave modules perform sampling clock synchronization, digital clock synchronization and interface synchronization of the A / D converter and the D / A converter through the clock signal and the second pulse of the synchronization pulse signal to complete synchronization. According to the invention, the digital array antenna and the digital circuit can be synchronized.

The embodiments of the present application provide a PMIC digital clock anomaly detection method, device, and chip, which belong to the technical field of integrated power management, including: providing a digital jitter control module, the digital jitter control module being configured to generate a counting window in the digital clock domain, the counting window crossing the clock domain to the analog clock domain to detect the digital clock by counting the number of analog clock cycles, obtaining a detection result of the digital clock, judging whether the detection result is consistent with a preset range, and outputting a corresponding judgment result. The PMIC digital clock anomaly detection method provided in the embodiments of the present application realizes high-precision and low-cost clock monitoring by coordinating digital and analog signals, performing cross-clock domain collaborative detection on the analog clock ana_clk and the digital clock dig_clk, performing dynamic counting, judging the error between the counting window and the cross-clock domain, and performing corresponding processing.

The invention provides a data life cycle autonomous management method and system based on source data feature perception. The method comprises the following steps: defining a basic attribute of target data in the storage system as a triple theta = (t, l, i); establishing a mapping protocol of the source data and the target data; monitoring the change frequency omega of the source data in real time, and executing the following cycle matching algorithm: setting that the life cycle variable and the change frequency of the source data meet an inverse relation t = k / omega, shortening t to improve the sampling precision of the digital clock when omega is increased, and prolonging t to reduce the sampling precision when omega is reduced; and automatically converting the calculated life cycle variable value into a control instruction. According to the method, the data life cycle can be converted into a dynamically programmable variable, low-power-consumption and high-precision response can be realized through hardware acceleration, or a flexible and low-cost management scheme can be realized through software scheduling.

1. Name of the product in this design: Graphical User Interface for a Digital Clock in Electronic Devices. 2. Purpose of this design: An electronic device. 3. The key design feature of this product is its graphical user interface. 4. The image or photograph that best illustrates the design's key features: the front view. 5. Purpose of the graphical user interface: This graphical user interface is used for displaying primary / secondary time zones, monitoring environmental data, and providing schedule reminders. 6. Human-computer interaction methods of graphical user interface: Click to exit the main view; long press the main time zone area to enter the settings interface (modify the time zone, calibrate the time alarm, etc.); swipe left on the main view to turn pages and switch time zones, then swipe right to return to the main view; swipe right on the main view to enter the alarm settings page; swipe down on the main view to enter the settings menu interface (screen brightness, button layout).

The invention relates to the technical field of digital clock signal processing, in particular to a clock frequency detection system and method based on clock edge alignment detection, and the system comprises a working state monitoring module, a sampling period counting module, a clock sampling module, a state judgment and change module, and an index generation and output module. A signal of the system in a normal working state is released through the working state monitoring module, a high-frequency clock signal is input to the working state monitoring module, and the system controls a sampling period through a low-frequency clock, periodically samples the high-frequency clock, counts the number of high levels in the sampling period and judges the state change of the high-frequency clock. And judging that the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, and outputting a corresponding phase index value. The device is realized by adopting pure digital logic, has anti-jitter capability, can accurately identify the phase of the high-frequency clock, and has the advantages of simple structure, high precision and strong transportability.

In one aspect, an apparatus includes: radio frequency (RF) circuitry to transmit and receive RF signals, the RF circuitry to operate with a local oscillator (LO) clock signal; clock circuitry to receive the LO clock signal and generate an LO-derived clock signal therefrom; first digital circuitry to communicate data according to a first digital clock signal; and a controller coupled to the first digital circuitry to select one of the LO-derived clock signal or a source clock signal to provide to the first digital circuitry as the first digital clock signal.

The invention discloses a clock display method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of electronic equipment. The method comprises the steps that an interface comprising a digital clock of a first display form is displayed, if a touch operation acting on the digital clock of the first display form is detected, a clock selection panel is displayed on the interface, the clock selection panel comprises digital clocks of multiple display forms, the multiple display forms comprise the first display form, and the first display form is a touch operation acting on the digital clock of the first display form. If a touch operation acting on a digital clock of a second display form in the clock selection panel is detected, the digital clock of the first display form is switched into the digital clock of the second display form in the interface, and the second display form is any one of the multiple display forms except the first display form. According to the invention, the digital clock with multiple display forms is designed and provided for the user to select and set, so that the user-defined layout experience and interaction experience of the user are ensured.

The present invention belongs to the technical field of signal transmission, and discloses a remote transmission method and device based on a short-range transmission protocol data frame. The present invention performs digital design of digital signals by moving the high level of the idle period and the period of sending data 1 in the short-range transmission protocol data frame to the high-frequency digital carrier frequency for transmission, and not sending the digital carrier in the low-level period when sending data 0. The receiving end first samples the received modulated signal twice within a digital carrier cycle using a digital clock signal that is twice the digital carrier frequency of the transmitting end, and then performs an XOR operation on the two sampled values, thereby restoring the high level and low level in the short-range transmission protocol data frame, and realizing that the remote transmission signal receiving end directly demodulates the digital carrier signal without using relevant or non-related demodulation means and filters, thereby greatly simplifying the digital demodulation circuit.

The application provides a digital clock jitter measurement circuit and a measurement method. The measurement circuit comprises a delay module, which receives a clock signal to be measured and generates a first clock signal and a second clock signal, and the phase difference between the first clock signal and the second clock signal is one clock cycle; a measurement module, which comprises a sampling unit, an oscillator control unit, a measurement unit and a counter unit. The measurement unit comprises a slow-frequency oscillator, an intermediate-frequency oscillator and a high-frequency oscillator, and a first edge detector and a second edge detector, the first edge detector being connected with the slow-frequency oscillator and the intermediate-frequency oscillator, and the second edge detector being connected with the intermediate-frequency oscillator and the high-frequency oscillator. The clock jitter measurement circuit and the measurement method provided by the application can automatically select a matched oscillator according to the phase relationship between the first clock signal and the second clock signal, thereby realizing automatic measurement of clock jitter.

The invention provides a segmented timing circuit and a low-dropout voltage stabilizing circuit, and the segmented timing circuit comprises a timing module and a control module. The timing module comprises a first timing unit and a second timing unit; the first timing unit comprises a first current source, a first capacitor and a first single-pole single-throw switch; the second timing unit comprises a second current source, a second capacitor and a second single-pole single-throw switch; the control module comprises a first comparator, a second comparator, a plurality of first AND gates, a plurality of second AND gates, a plurality of first triggers, a plurality of second triggers, a power-on detection unit, a signal generation unit, a first NOR gate and a second NOR gate; the signal generation unit comprises a plurality of first signal generation circuits and a plurality of second signal generation circuits. The segmented timing circuit provided by the invention not only can reduce the consumption of the digital unit, but also does not need the cooperation of an external digital clock and a digital-to-analog converter, thereby greatly reducing the resource consumption of the digital-to-analog converter.

The invention discloses a receiving circuit and communication equipment, and belongs to the field of communication. The receiving circuit comprises an analog circuit and a digital circuit; the analog circuit comprises a numerical control delay module; the digital circuit comprises a frequency detection module, a parameter management module and a data receiving module; the frequency detection module is used for detecting the frequency of the target clock signal to obtain a frequency detection result and transmitting the frequency detection result to the parameter management module; the parameter management module is used for obtaining the optimal value of the target receiving parameter based on the frequency detection result, and transmitting the optimal value of the target receiving parameter to the numerical control delay module and the data receiving module; the numerical control delay module is used for calibrating the digital clock signal according to the optimal numerical value of the target receiving parameter to obtain a calibrated digital clock signal; the data receiving module is used for receiving target data according to the optimal numerical value of the target receiving parameter; the target data is obtained by sampling the data from the transmitting end according to the calibrated digital clock signal by the analog circuit.

1. The name of this design product: LED digital clock housing. 2. Purpose of this design product: to provide an installation carrier and protection for digital clocks of electronic devices. 3. The key point of the design of this product lies in its shape. 4. The picture or photo that best illustrates the design points: Stereoscopic drawing 1.

The invention discloses a circuit and method for resisting white noise interference of an ultrasonic water meter. The circuit comprises a transmitting end ultrasonic transducer, a transmitting coding circuit, a digital clock chip, a microprocessor unit, a receiving coding circuit and a receiving end ultrasonic transducer. The digital clock chip is connected with the transmitting end ultrasonic transducer through the microprocessor unit and the transmitting coding circuit in sequence; the microprocessor unit is connected with a receiving end ultrasonic transducer through a receiving coding circuit in sequence; the digital clock chip is respectively connected with the transmitting end ultrasonic transducer, the transmitting coding circuit, the receiving coding circuit and the receiving end ultrasonic transducer. The white noise interference resistance of the ultrasonic water meter is improved.

The invention discloses a slope calibration method of a driving circuit, a circuit, a chip, equipment and a readable storage medium, and the method comprises the steps: enabling a frequency-adjustable oscillator in a slope calibration stage, and measuring the output clock frequency of the oscillator, the output clock frequency being adjusted by a calibration code; based on a comparison result of the output clock frequency and a target frequency range, adjusting a calibration code to calibrate the output clock frequency to the target frequency range, and obtaining a corresponding target calibration code; and applying the target calibration code to the driving circuit to calibrate an output signal slope of the driving circuit. According to the application, the slope of the output signal of the analog drive circuit can be indirectly, accurately and efficiently calibrated by measuring and calibrating the frequency of the digital clock, and the problems of sensitive load configuration, large influence of parasitic parameters of a test board, harsh measurement precision requirements, long test time and the like existing in direct slope measurement are avoided.

The invention provides a digital clock recovery system and method, and relates to the technical field of digital signal processing. The system comprises an interpolator, a timing error detector, a loop filter and a numerically controlled oscillator which form a feedback loop. Wherein the interpolator is a polynomial interpolator and is used for obtaining an interpolation result or an intermediate value by inquiring a pre-calculation module so as to reduce the operation complexity; a digitally controlled oscillator determines a base point and a fractional interval for interpolation by operating bits on an internal phase accumulator value to avoid division operations. The method comprises the following steps: performing polynomial interpolation by querying a pre-calculation module; detecting a timing error; filtering the error; and updating the timing information by performing a bit operation on the phase accumulator value. By means of the scheme, unification of high precision and low delay is achieved, loop performance is improved, and system resource consumption is reduced.

This invention provides a digital clock remote metering method based on network delay suppression. The method includes the following steps: constructing a hierarchical synchronization architecture, deploying a master clock source, multiple regional clock servers, and multiple terminal devices. The multiple regional clock servers are connected to the master clock source via dedicated fiber optic lines to obtain a reference time. Each regional clock server is connected to multiple terminal devices via 5G / Industrial Ethernet, forming a three-level synchronization network. Retrieval time (RTT) data between the terminal device and a regional server is obtained through bidirectional timestamp interaction, and messages are filtered according to preset rules. A hybrid delay compensation algorithm is used to calculate a final delay compensation value, which is used to calibrate the terminal clock. Finally, a time selection algorithm is used to obtain an optimal reference source for data synchronization analysis. This invention can solve the time deviation problem between the current time indication of a digital clock and the standard time, as well as data synchronization analysis issues.

1. Name of the product in this design: Socket with table lamp (digital clock version). 2. Purpose of this design: A multi-functional socket for providing lighting. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

1. Name of the product in this design: Electronic Clock (Long). 2. Application of this design: This design is intended for use in alarm clocks and timers. 3. The key point of the design of this product lies in its shape. 4. The picture or photo that best illustrates the design points: Stereoscopic drawing 1.

Certain aspects of the present disclosure provide a relatively compact frequency- locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

The invention relates to the technical field of visible light communication, and provides an optical wireless FDM signal generation method and system for LIFI, and the method comprises the steps: receiving a unique clock signal and a to-be-transmitted digital bit stream through an FPGA, and generating multiple paths of synchronous digital clock signals based on the clock signal; distributing a digital bit stream to be transmitted to a corresponding FDM channel in the FPGA, and performing synchronization processing by using a digital clock signal; modulating a to-be-transmitted digital bit stream of each FDM channel to a corresponding subcarrier frequency to obtain multiple paths of digital domain FDM signals, and performing filtering and superposition processing on the multiple paths of digital domain FDM signals to obtain multiple paths of analog signals; and combining the multiple paths of analog signals in an analog domain to obtain a composite analog signal, and inputting the composite analog signal into an LED to emit a composite light FDM signal. According to the scheme, the problems of high hardware complexity, large PAPR and difficult channel synchronization in the existing LiFi system are solved.

The invention discloses a digital clock measuring system embedded with a standard digital clock, and relates to the technical field of digital clock metering, and the measuring system comprises a main lens, a standard digital clock embedding unit and a camera. The main lens is used for capturing a tested digital clock, the standard digital clock embedding unit is located on an emergent light path of the main lens, and the camera is located on an emergent light path of the standard digital clock embedding unit. The standard digital clock and the measured digital clock are displayed at the same time through the standard digital clock embedding unit embedded with the standard digital clock, secondary imaging is carried out on an optical image, a target image is obtained, an external standard digital clock does not need to be arranged and installed in the measurement process, and the measurement accuracy is improved. The target image can contain effective information of the two digital clocks at the same time only by performing imaging adjustment on the measured digital clock, measurement can be completed after identification processing, the test adjustment process is simplified, the application range of the digital clock measurement system is expanded, and the measurement accuracy and the measurement efficiency are improved.

A method, system, and apparatus for digital clock and data recovery (CDR) with analog signal that samples blindly (i.e., independent of the baud rate). The CDR further has a digital monolithic circuit that includes an interpolator circuit, and a fully digital clock (FDC) that recovers the digital data from the analog signal.

A level shift assembly, a method for over-current protection, and a display apparatus. The level shift assembly includes a level shift module, which includes a control unit, a current detection unit, a level shift unit, and an over-current protection unit. The controller determines, at a first falling edge of a digital clock signal, a first analog clock signal among a plurality of analog clock signals which corresponds to the first falling edge based on a correspondence of a current display mode; the current detection unit detects a current of the first analog clock signal; and a moment, at which a falling edge of the digital clock signal is present, is within a last line of a corresponding analog clock signal, and an over-current signal is sent to the over-current protection unit when the current of the first analog clock signal is not within a current threshold range.

For example, an apparatus may include a digitally-controlled frequency multiplier, which may be controllable according to a digital control input, to generate an output frequency signal having an output frequency, for example, by multiplying an input frequency of an input frequency signal. For example, the digitally-controlled frequency multiplier may include a phase generator configured to generate a plurality of phase-shifted signal groups corresponding to a respective plurality of first phase-shifts applied to the input frequency signal, a plurality of digital clock multipliers controllable according to the digital control input to generate a respective plurality of frequency-multiplied signals based on the plurality of phase-shifted signal groups, and a combiner to generate the output frequency signal based on a combination of the plurality of frequency-multiplied signals.

A rate estimator circuit is provided for adjusting the sampling rate filter of a sampling rate converter circuit. The rate estimator circuit includes a first integrator clocked by a first clock signal having a first sampling frequency and a second integrator clocked by a second clock signal having a second sampling frequency; a resolution upscaling circuit including a third integrator clocked by a system clock signal; a digital clock multiplier circuit including the second integrator and a multiplier loop circuit having a fourth integrator; a multiplier output stage connected to the output of the fourth integrator; and a rate estimator circuit including the first integrator and an estimator loop circuit having a fifth integrator.

A digital clock data recovery device for recovering a clock and data in a data signal includes a phase difference compensation unit configured to selectively output an upper bit value and a lower bit value of a phase difference value between a first input signal and a second input signal according to a condition based on a range of the phase difference value, a digital loop filter configured to receive an output of the phase difference compensation unit; and a digital controlled oscillator configured to transfer a feedback signal to the phase difference compensation unit based on an output value of the digital loop filter.