6 results about "Digital tuning" patented technology

The application relates to the technical field of integrated circuits, and discloses a digital auxiliary adaptive zero-crossing detection circuit. The circuit comprises a digital auxiliary comparator module, a digital logic module, a detection discrimination module and a counter module. The digital auxiliary comparator module compares a switch node voltage signal with a power ground signal to generate a first output signal; the digital logic module processes the first output signal to generate a zero-crossing detection signal and control the turn-off of a power tube; the detection discrimination module receives a second output signal of the digital logic module and the zero-crossing detection signal to generate a digital tuning signal; and the counter module receives the digital tuning signal to generate a six-digit digital signal, dynamically adjusts a resistance array in the digital auxiliary comparator module, adaptively adjusts the flip offset of the comparator by changing the resistance value of the resistance array, and thus changes the turn-off timing of the power tube. The application can accurately control the turn-off timing of a synchronous rectification power tube, reduce the reverse current and reduce the dynamic power consumption.

A system and method to generate and implement digital tuning files based on p-smooth number sequences for use with a digital musical instrument is provided. A p-smooth number sequence is generated and a subset of p-smooth numbers from the sequence is chosen as a musical octave of musical note frequencies. Each note within the octave is designated as a tonic, and each tonic is used to generate additional musical octaves and corresponding musical note notations. The musical octaves and corresponding musical note notations are stored into the digital memory of the digital musical instrument, and the instrument's native musical note mappings are remapped to the musical octaves and corresponding musical note notations from the digital file.

The present invention provides host cells and vector systems that allow precise tuning of expression of selectable marker expression and increased integrated copy number of product genes so that host cell growth and expression of desired proteins or nucleic acid products from the host cell can be optimized.

The invention provides a low-power-consumption numerically-controlled oscillator, relates to the technical field of integrated circuits, and comprises a resonant cavity module used for generating a high-frequency resonant signal based on a resonator; the input end of the complementary cross-coupled oscillation module is connected with the resonant cavity module, and the complementary cross-coupled oscillation module is used for receiving high-frequency resonant signals and generating continuous oscillation; a capacitor array of the segmented numerical control capacitor tuning module is connected in parallel to two ends of the resonant cavity module and is used for receiving external numerical control signals and changing equivalent capacitance of a resonant network, so that wide-range and high-precision digital tuning is carried out on oscillation frequency; the parasitic oscillation suppression module is integrated in an internal feedback path of the complementary cross-coupled oscillation module and is used for suppressing direct-current positive feedback and attenuating low-frequency loop gain so as to eliminate direct-current locking and low-frequency parasitic oscillation; the input end of the output buffer module is connected with the output node of the complementary cross-coupling oscillation module, and the output buffer module is used for shaping and driving the oscillation signal and then outputting the signal. In the mode, wide tuning, ultra-low power consumption, high stability and high-precision tuning are realized, meanwhile, the phase noise performance and the mass production feasibility are improved, and the strict requirements of the battery-free Internet of Things node are met.

The utility model provides a radio frequency energy bidirectional digital tuning circuit and a radio frequency energy acquisition system, and relates to the technical field of integrated circuits, and the radio frequency energy bidirectional digital tuning circuit comprises a capacitance increasing circuit, a capacitance reducing circuit and a finite-state machine. Wherein a first port of the capacitance increasing circuit and a third port of the capacitance reducing circuit are connected in parallel; a second port of the capacitance increasing circuit and a fourth port of the capacitance reducing circuit are connected in parallel; the finite-state machine is respectively connected with a bias voltage end of the capacitance increasing circuit and a bias voltage end of the capacitance reducing circuit, and is used for providing bias voltage for the capacitance increasing circuit and the capacitance reducing circuit; the capacitance increasing circuit is used for increasing the capacitance of the radio frequency energy bidirectional digital tuning circuit; and the capacitance reduction circuit is used for reducing the capacitance of the radio frequency energy bidirectional digital tuning circuit. According to the technical scheme of the embodiment of the utility model, bidirectional tuning can be realized, and the working bandwidth of the tuning circuit is expanded.

The disclosure relates to a radar unit for use in a distributed coherent DCR automotive radar system. The radar unit includes: a local clock circuit including: an oscillator; and a digital tuning circuit in parallel with the oscillator and comprising a plurality of switchable capacitors; a tuning controller configured to adjust an operation frequency of the local clock circuit by controlling the plurality of switchable capacitors during a non-transmission operation period of the radar unit; and a communication unit configured to transmit and receive data from the central processor unit; wherein the tuning controller is configured to adjust the operating frequency of the local clock circuit in response to the communication unit receiving frequency offset data from the central processor unit, the frequency difference between the operating frequency of the local clock circuit and the operating frequency of a remote clock circuit of the DCR automotive radar system is reduced.