149 results about "Digital tuning" patented technology

An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (K_DCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δf_max) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion

can then be applied to a control input of switchable devices within the digitally controlled oscillator.

A radio transmitter is structured to provide frequency hopping of transmitted leakage signals in addition to RF hopping of the RF output signal. A digital computer controls a digital tuner, a TLO, a FLO, and an IF unit to provide the RF hopping and to provide digital-tuner frequency hopping and IF hopping thereby enabling the frequency hopping of transmitted leakage digital tuner and IF signals.

An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (K_DCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δf_max) in the oscillating frequency; (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (d_k^TF) can then be applied to a control input of switchable devices within the digitally controlled oscillator; and (3) a non-linear differential term (187, 331) can be used to expedite correction of the digitally controlled oscillator when large phase error changes (335) occur.

Provided are a voltage controlled digital analog oscillator and a frequency synthesizer using the same, the oscillator comprising an oscillator having a frequency of an output signal being determined by a voltage inputted to an analog input end and a digital value inputted to a digital input end; and a digital tuner for comparing the voltage inputted to the analog input end to first and second threshold voltages and changing the digital value inputted to the digital input end according to the result, whereby it is possible to obtain a broadband frequency output with less noise.

A power-saving channel scanning system and a method thereof for multi-channel broadcasting stops the scanning operation of a digital tuner installed in a broadcast receiving device (Set-Top Box (STB)) and switches to a power-saving mode when a cable is cut off or no signal is received in a multi-channel broadcasting system. The power-saving channel scanning system includes a broadcast receiving terminal measuring broadcasting channel powers in order and switching from a normal mode to a power-saving mode when the powers of all of the measured channels are outside the range of a predetermined normal channel power.

An image display apparatus equipped with an analog tuner and a digital tuner includes a key input unit for enabling a user to input an automatic channel scan command and other requests; a controller for conducting channel scan in response to the automatic channel scan command inputted through the key input unit, the channel scan first being conducted on analog channels and then digital channels by using the analog tuner and the digital tuner, or first being conducted on digital channels and then analog channels by using the digital tuner and the analog tuner, wherein the comparison of the number of channels scanned first with a predetermined number of channels determines a channel scan method; and a memory for storing analog channels/digital channels being automatically scanned.

A digitally-tunable RF MEMS filter includes a substrate and a plurality of mechanically coupled resonators, wherein a first and a last resonator of the plurality of mechanically coupled resonators are configured to be electrostatically transduced. One or more of the plurality of mechanically coupled resonators are configured to be biased relative to the substrate such that the one or more biased resonators may be brought substantially in contact with the substrate. In a method of digitally tuning an RF MEMS filter having a mechanically coupled resonator array, a DC bias voltage is applied to at least a first resonator and a last resonator of the mechanically coupled resonator array such that motional boundary conditions for the at least first resonator and last resonator are selectable in proportion to the DC bias voltage.

A transceiver having an RF receiver, in particular VHF receiver, with digital signal processing in a digital part. The transceiver having an input part, at least one mixer and an intermediate frequency/baseband processing device, having a local channel oscillator, to which a first phase locked loop with a phase discriminator and an adjustable first frequency converter are assigned, and having a reference oscillator for the phase locked loop and the control clock of the digital signal processing device, in which, in order to acquire the control clock, a digital clock synthesizer is provided to which an output signal of the reference oscillator is supplied, and a control signal is supplied by the digital part in the form of a digital tuning word, the frequency of the reference oscillator being selected such that its order of magnitude is at least equal to the bandwidth of one or more of the reception bands used, and none of its harmonics occur in a reception channel.

A digital tuner has an input tuning range with lower and upper limit frequencies. An up converter converts an input signal to an intermediate frequency signal whose frequency is higher than the upper frequency limit of the input range. A downconverter is a zero intermediate frequency quadrature converter which converts the intermediate frequency signal to in-phase and quadrature baseband signals. The upconverter has a local oscillator fundamental frequency which is greater than the upper frequency limit of the input tuning range.

A digital tuning system (250) for changing a cutoff frequency of an analog filter (132) includes digital synthesizers (292 and 294) for producing a two-tone calibration signal (196) applied to an input of the filter after a quality factor of the filter is increased. The filter includes at least one R/C circuit with two resistors (304 and 306) for changing the quality factor and arrays (308 and 310) of capacitors for changing the cutoff frequency. The amplitude of the magnitude responses (409 and 411) of the filter to each tone (405 and 407) is measured by a two discrete Fourier transform single-frequency bin power detection circuits (253 and 254) while the filter is sequenced through a plurality of capacitance settings. An optimal capacitance for the R/C circuit is selected by comparing, to a pre-selected value, a difference between the responses of the filter to each tone, for each capacitance setting.

A television apparatus having digital serial bus ports allows a user to select a user-designated digital video content source input such as a digital tuner of the television apparatus and digital serial bus compliant components connected to the television apparatus via the digital serial bus ports of the television apparatus, and to cause digital content from the user-designated digital content source device to be recorded onto a digital recording device connected to the television apparatus via the digital serial bus ports. The present invention allows a user to continuously record digital content onto a digital recording device (e.g. an AVHDD), whether from the TV's digital tuner or from another digital serial bus compliant device in a peer to peer arrangement. The connection is always recording, but allows the user to select or designate a digital (i.e. MPEG2) source (i.e. the TV tuner or another digital serial bus compliant device), in addition to displaying the selected content.

The invention relates to the field of electronics and more particularly to the tuning and injection locking of voltage controlled oscillators (VCOs). An improved injection locking circuit is provided which allows the VCO to injection lock with a smaller reference signal and therefore a smaller locking bandwidth (LBW). In order to allow the VCO to injection lock with a lower power reference signal, this invention includes a pre-tuning algorithm to place the VCO frequency such that the desired frequency is in the LBW. Tuning of the VCO is achieved using direct digital tuning that does not require an input reference. Injection locking is performed using a low frequency clock harmonic as the reference signal. More specifically, tuning is accomplished by sub-sampling and digitizing the output signal of the VCO, determining the center frequency, and adjusting the VCO control voltage.

A system and method for programming a digitally tunable oscillator is provided. A desired output frequency is received. A tuning effect of a set of digital tuning words on a crystal resonant frequency is determined, and valid parameters of an algorithm for translating and tuning the crystal resonant frequency to a value within an error tolerance of the desired frequency, based on the determined tuning effect are calculated. Valid parameters are preferably calculated based on an intermediate tuning value, sorted by ascending divide parameter of the algorithm, and then evaluated in sorted order for ability of a tuning effect to null frequency error to within the error tolerance. The valid set of calculated parameters are then programmed into a nonvolatile memory. The oscillator control parameters may remain unprogrammed until all necessary parameters are defined. Because the device may be programmed in a single step, without intermediate presumption of nominal crystal frequency, the final plate process may be unnecessary. A high accuracy may be obtained by searching through the complete set of available parameters for a set that meets a frequency and tolerance specification. The oscillator is preferably a Cypress CY2037 device alone or in combination with a Micro Analog Systems MAS1175 device.

According to one embodiment, an information processor comprises an error detection circuit having at least one of a synchronous byte interval detection circuit, a synchronous byte comparison circuit and an error indication comparison circuit which receives digital information, transmitted as packet data, by a digital tuner unit and detects packet data having defects as an error in the sequentially received packet data from intervals of synchronous bytes, values of the synchronous bytes or values of error indications, and mounts a digital broadcast receiver to reproduce information from the packet data from which the packet data having the defects have been removed.

A digital phase-locked loop apparatus using FSK includes a PFD detecting phase differences between a reference clock and a frequency-divided signal, and a first adder for generating first digital control codes by adding first digital codes, second digital codes, and channel frequency codes including channel information to each other, the first digital codes being converted from time differences between first and second pulses. The apparatus further includes a digital filter correcting errors of the first digital control codes to generate second digital control codes, a DCO for varying an oscillating frequency in accordance with a digital tuning word based on the second digital control codes, and a dual modulus division unit dividing the oscillating frequency into a frequency-divided signal.