40 results about "Digital memory" patented technology

The invention relates to a method for monitoring a robot system comprising a robot arm and a peripheral device, the method comprising the steps of: providing a communicative peripheral connection between the peripheral device and a robot controller; establishing an operation signal history in a digital storage wherein the operation signal history is based on operation representations; executing a robot operation process on the robot controller; establishing a peripheral signal associated with the peripheral connection; recording the peripheral signal to obtain a peripheral signal representation; updating the operation signal history by providing the peripheral signal representation as an operation representation of the operation representations; and tracking operation of the robot system based on the operation signal history. The invention further relates to a robot system.

A mixed analog / digital in-memory computing device implements matrix vector multiplication with reduced noise for use by a deep neural network (DNN). For each row of a cross-bar array a digital multiplier is split into a least significant (LS) portion and a most significant (MS) portion of different sizes that are preloaded into two cells on one row and two different columns of the cross-bar array. An input activation (IA) value is driven onto input conductors of each row and an analog-to-digital converter (ADC) converts output signals from the two columns as a MS partial sum and a LS partial sum. A gain is applied to the MS partial sum and added to the LS partial sum to form a resulting value for one node of the DNN.

The invention discloses a digital in-memory computing accelerator, an instruction set architecture and a data processing method thereof, and belongs to the technical field of in-memory computing. The digital memory computing accelerator comprises a chip-level module, a core-level module and a unit-level module, the chip-level module is used for acquiring a target calculation task, splitting the target calculation task into a plurality of core-level calculation tasks according to a load distribution strategy and distributing the core-level calculation tasks to the core-level module; the core-level module comprises a control unit, a calculation unit and a cache unit, and the control unit comprises an instruction fetching module, a decoding module and an instruction scheduler; an instruction fetching module reads a to-be-executed instruction corresponding to the core-level calculation task, a decoding module decodes the to-be-executed instruction to generate a control signal and sends the control signal to a calculation unit, and the to-be-executed instruction is an instruction of a calculation instruction set architecture in a digital memory; the calculation unit executes corresponding calculation operation according to the control signal; the cache unit caches intermediate data generated by executing the corresponding calculation operation.

A neural network accelerator can perform energy-efficient multiply-and-accumulate operations of a neural network by Booth encoding a stationary operand, such as weights, before a compute phase. The Booth-encoding circuitry generates and stores Booth encoded multipliers in a Booth encoded multiplier storage and a precomputed compensation value representing a sum of the compensation bits of the Booth encoded multipliers in a Booth compensation storage. Per-cycle Booth encoding and compute of the sum of the compensation bits are avoided during multiply-accumulate operations because Booth encoding is applied to stationary operands. The Booth encoder can be located at the periphery where the multiplicands are loaded onto the accelerator shared across multiple compute columns and / or tiles to amortize the Booth encoder area overhead. The Booth encoder supports reconfigurable operand bit widths (e.g., 16-, 8-, 4-, and 2-bit). The approach is applicable to single-instruction-multiple data (SIMD) arrays, systolic arrays, and analog / digital compute-in-memory arrays.

A computer assisted method for classifying digital audio files based on features of a digital audio signal comprised in the file, comprising: storing the audio file in a digital memory; determining a portion (p) of drop of the audio file, for example the portion with the highest subjective loudness; classifying said audio file based on features of said drop.

A mixed analog / digital in-memory computing device implements matrix vector multiplication with reduced noise for use by a deep neural network (DNN). For each row of a cross-bar array a multiplier is split into at least a most significant (MS) portion and a least significant (LS) portion and preloaded into at least two cells on one row and at least two different columns of the cross-bar array. An input activation (IA) value is driven onto input conductors of each row and an analog-to-digital converter (ADC) converts output signals from the two columns as a truncated MS partial sum and a truncated LS partial sum. A gain is applied to the truncated MS partial sum and added to the truncated LS partial sum to form a resulting value for one node of the DNN.

To provide a memory service, tags are associated with content including photos / videos as well as messages, links, files, call transcripts, payment transaction information, location history, contacts, and / or activity information in an electronic device. Connections are determined between items of the content and photos / videos. A memory is identified as meaningful for a user according to characteristics of a relationship between the user and another person; frequency of communication between the user and the person; content of communication between the user and the person; characteristics of an event or an activity associated with the memory; and characteristics of a location associated with the memory. Digital content aggregated for the meaningful memory includes at least some of the tagged content and at least some of the photos / videos. Based on the aggregated digital content, a digital memory is created allowing the user to reexperience the meaningful memory.

The invention provides a time backflow type digital memory presentation method, and relates to the technical field of mobile internet, and the method comprises the steps: obtaining a starting time point and an ending time point which represent a to-be-presented memory time range; calculating to obtain a total time difference through the starting time point and the ending time point; based on the total time difference, setting a total step number required for realizing the reverse animation and an execution interval of each step, and obtaining an animation progress parameter according to the total step number and the execution interval; the animation progress parameter is initialized, so that the animation progress parameter is linearly changed from an initial value to a final value in an animation execution process; when each step of the animation is executed, obtaining a current value of an animation progress parameter as input; and applying the input current value to a preset slow motion function for calculation so as to obtain a nonlinear progress parameter with an S-shaped change curve. According to the invention, immersion, emotional resonance and visual fluency of memory presentation are improved.

A system and method for automatically detecting a type of memory card inserted into a portable computing device. The system may include a system on chip capable of detecting a first type of memory card and a second type of memory card. For this detection, the system on chip does not have / does not use an analog switch. The first memory card may be a secure digital express memory card. Meanwhile, the second memory card may be a secure digital memory card. The system on chip may include a general purpose input / output pin. The general purpose input / output pin may activate a first communication bus protocol associated with the secure digital express memory card in response to receiving a first signal. The first signal may be generated by a reserved for future use pin on the first type of memory card.

A machine learning and inference system for generating personalized activity plans includes: a trained world context knowledge base; a trained personal digital memory bank; the target engine is used for establishing a moving target; an activity decomposition engine to decompose the activity into connected logically consistent sub-activities; a weight allocation engine to allocate value weights to the potential sub-activities; a graphics generation engine to generate a multi-layer weighted graph to train a model of personalized results of the sub-activities according to value weights; a scene generation engine to analyze a network of logically consistent potential sub-activities connected by paths to determine a selected scene path to the activity target according to a model that at least personalizes the user results; a feedback engine to apply learning from the scene generation engine to a world context knowledge base and / or a personal digital memory bank; and an output channel for outputting a personalized activity plan comprising recommended actions for implementing the selected scene path.

A care management system for routing one or more tasks related to medical care for at least one patient includes a server, a hub configured for communication with the server, and a plurality of smart devices configured for communication with the hub. Each of the plurality of smart devices includes (i) a wireless transceiver for performing wireless communication with the hub, and (ii) a processor coupled to the wireless transceiver. The processor is configured for receiving, via the wireless transceiver, information transmitted to the plurality of smart devices from the server. The processor is also configured to perform a plurality of operations in accordance with machine readable instructions stored in a digital memory. The plurality of operations includes generating output information based on a predictive analysis of a plurality of patient care parameters. The output information includes a recommended sequence for performing the one or more tasks.

The application provides a push-training integrated SRAM digital memory computing system, which comprises a push-training integrated SRAM digital memory computing core module, a WL driving & forward-input driving module, a BL driving module, a forward-output module, a reverse-input exchange switch module, a reverse-input driving module, a reverse-output module and a control module. The push-training integrated SRAM digital memory computing core module is composed of a plurality of transpose SRAM digital memory computing modules and is used for matrix multiplication and addition calculation and supports forward calculation and reverse calculation at the same time. The reverse-input exchange switch module is used for exchanging input data and realizing reverse input exchange operation of a corresponding transpose weight matrix. Through multiplexing the push-training integrated SRAM digital memory computing core module, the application solves the balance problem of the calculation density and the storage density of the forward and reverse propagation, realizes efficient switching of training and reasoning, optimizes the calculation energy efficiency and area efficiency, and improves the efficiency of training and reasoning.

The invention provides a work memory ability training method based on electroencephalogram neural feedback, a storage medium and equipment, and the method comprises the steps: obtaining electroencephalogram signal data of a tested object in a process of executing a training task, and obtaining task execution result data of the tested object, the training task at least comprising a digital memory breadth task and a spatial memory breadth task; extracting physiological features of the electroencephalogram signal data, and calculating a cognitive state index and a global cognitive ability index according to the physiological features and the task execution result data; the training task is adjusted according to the global cognitive ability index, and the tested object is trained again according to the adjusted training task; and when it is judged that at least one of the training times, the global cognitive ability index and the cognitive state index meets a preset training condition, generating a training report at least including the cognitive state index of the tested object during each training. The computing resource consumption, the training delay and the deployment cost in the multi-dimensional training of the working memory ability are reduced.

A system and method to generate and implement digital tuning files based on p-smooth number sequences for use with a digital musical instrument is provided. A p-smooth number sequence is generated and a subset of p-smooth numbers from the sequence is chosen as a musical octave of musical note frequencies. Each note within the octave is designated as a tonic, and each tonic is used to generate additional musical octaves and corresponding musical note notations. The musical octaves and corresponding musical note notations are stored into the digital memory of the digital musical instrument, and the instrument's native musical note mappings are remapped to the musical octaves and corresponding musical note notations from the digital file.

The present invention relates to a content gift memory system and method, and a providing platform and method thereof, and more particularly, to: a system and method for sharing multimedia content (digital content) by presenting an accessory, jewelry, or the like ("NFC item") having an NFC chip embedded therein, which is used as an access authority key of a web application (app), to another person, and generating a memory obtained by capturing the gift and the content as an asset protected by a blockchain; and a providing platform and method thereof. A content gift memory system according to an embodiment of the present invention comprises: a user terminal capturing and uploading multimedia content; a module analyzing and upgrading the multimedia content (digital memory) captured by the user terminal; a storage means such as a memory or a blockchain network storing and protecting digital assets; and a smart contract module managing digital gifts and memories including the multimedia content.

The invention belongs to the technical field of digital in-memory computing, and discloses a low-power-consumption digital in-memory computing circuit based on dynamic row and column sparse configuration, a memory and a chip, which are characterized in that in a column dimension, 2-bit configuration signals are introduced, each column is supported to be independently configured into three modes of normal computing, weight reuse or full idle, and in a row dimension, the 2-bit configuration signals are used for configuring the 2-bit configuration signals into three modes of normal computing, weight reuse or full idle; a dynamic sparse gating mechanism is integrated, an input zero value or an unmapped row can be detected in real time, then a word line driving signal is directly pulled down to prohibit data loading, a connection switch of an isolation local bit line (LBL) and a global bit line (GBL) is controlled, and invalid coupling power consumption caused by global signal fluctuation is prevented; according to the method, the array power consumption strictly depends on the actual effective calculation amount instead of the physical array size through a software-hardware combined dynamic configuration strategy, so that the dynamic and static power consumption is remarkably reduced while high-performance calculation is ensured.

The invention relates to an in-digital memory computing system and an in-digital memory computing compiler. The in-digital memory computing (DCIM) system includes memory cells, multipliers and adder trees in a first region of a semiconductor die. The memory cells and the multipliers are configured to organize paired corresponding two-dimensional weighted arrays (two-dimensional matrices) and multiplication arrays. Each of the multiplication arrays is coupled to each of input rows (input channels) of the input matrix. For each of the pairs and for a selected weight row (one-dimensional weight vector) of the corresponding weighted array, the selected weight row is multicast to each of the multipliers in the multiplication array of the pair. Each of the multiplication arrays is configured to perform multiplication of an input matrix and a weight vector to produce a combined effect of products corresponding to the input channels for the CIM system.

The present invention relates to an AI-integrated cross-platform digital legacy preservation platform configured to record, preserve and transmit personal stories and memories through artificial intelligence-assisted storytelling and secure posthumous communication. The platform integrates multiple modules including user registration, AI-driven biography generation, executor-managed legacy control, family tree visualization, synchronized photo albums, multilingual interface and QR-linked memorial access. The platform enables users to chronologically document their lives through videos, photos and text, while allowing designated executors to manage legacy release after death verification. The system further supports CRM synchronization, sales management and personalized digital avatars for enhanced emotional interaction. The invention offers significant advantages in ensuring data integrity, emotional continuity and accessibility across generations. The scope of the invention extends to personal, familial and institutional applications establishing a unified and secure ecosystem for long-term digital memory preservation and interactive legacy sharing.

Certain embodiments provide apparatuses for performing machine learning tasks, specifically, for in-memory computation (CIM) architectures. One embodiment provides a method for in-memory computation. The method generally comprises the step of accumulating output signals on each of a number of columns of memory through each of a number of digital counters, wherein a number of memory cells are on each of the number of columns, and the number of memory cells store a number of bits representing the weights of a neural network, and the number of memory cells on each of the number of columns correspond to different word lines of memory; the step of adding the output signals of the number of digital counters through an adder circuit; and the step of accumulating the output signals of the adder circuit through an accumulator.

The present invention relates to a versatile, adjustable, non-rotating axle device engineered to enhance flexibility and ergonomic comfort in diverse work and living environments. This device supports various platform surfaces, enabling smooth, secure vertical adjustments to accommodate different user postures—from seated to standing or any intermediate position. It incorporates a choice of gas-spring or electric lift mechanisms for precise, controlled movement, along with integrated safety stops and vibration-damping features to ensure stability and user safety. An optional digital memory interface allows for personalized ergonomic settings, facilitating quick and repeatable height adjustments. Designed to function without reliance on specialized mounting arms, the axle device offers a universal solution for adaptable, ergonomically optimized setups across a broad spectrum of applications.

Stapler (1, 1.1) for physically holding together material to be stapled with a stapler body (2) to which a stapling mechanism (6) having at least two stapler bars (7, 7.1) for penetrating material to be stapled is attached, characterized in that the stapler (1, 1.1) comprises a digital memory (10, 13, 14) permanently attached to the stapler body (2), which a user can read and write with a digital reading device, such as a PC.

The invention relates to random data polarity inversion of computational weight data in a computational processing system in digital memory. Computation weight data for in-memory computation operations is written to memory cells in a memory array by randomly selected polarity inversion. During execution of a compute operation in memory, compute weight data is read from memory cells in a memory array. A polarity inversion is applied to the read computational weight data when the read computational weight data is written to a memory cell in the memory array by a randomly selected polarity inversion.

The invention relates to a method for detaching a stack of partial stacks of flat products, in which geometric data of the stack and / or of the partial stacks are optically captured, the partial stacks are picked up from the stacks individually or in groups in sequence using a robotic arm that can be moved in a controlled manner and using geometric data for the movement control of the robotic arm. At least one of the partial stacks is provided with a code printed on the upper flat product of the partial stack, which code is optically captured by a capture device, in which code geometric data is stored and read for motion control of the robot arm, and / or in which code identification data for geometric data is stored and read for motion control of the robot arm. And invoking geometric data stored in a digital memory in correspondence with the identification data for motion control of the robot arm. According to the invention, stacks formed by partial stacks of flat products can be quickly, safely and accurately disassembled without errors, and the partial stacks can also be well conveyed to subsequent processing links.

In order to support a flexible N: M sparsity mode in a DCiM macro, the DCiM macro is subdivided into a plurality of sub-macros according to a partition factor P. Each sub-macro can support a 1: 2 sparsity ratio. By fully utilizing the partition design, the sub-macros can be grouped together to support different N: M sparsity modes. In order to determine an optimal N: M sparsity pattern for each layer of the neural network, the algorithm can determine a value A in a sparsity ratio A / B based on a number of exterior points in the layer, and determine a value B in the sparsity ratio A / B based on locality measurements of exterior points representing a sparsity distribution of the exterior points. In addition, the optimal N: M sparsity pattern aligned with the determined sparsity ratio A / B can be selected based on prioritizing delay or accuracy or balancing both delay and accuracy.

In one example disclosed herein, the system comprises an analog memory-based computation engine for performing operations in a first layer of a neural network, and a digital memory-based computation engine for performing operations in a second layer of the neural network distinct from the first layer. The system optionally comprises a dynamic weight engine for performing operations in a third layer of the neural network distinct from the first and second layers.

The invention discloses a digital memory function evaluation system and method based on a structured story scene. The system comprises a structured story scene library in which a story template comprising a plurality of logically coherent life scenes is pre-stored, and each scene defines a key information point; the multi-modal material library is used for storing a plurality of replaceable materials corresponding to the key information points; the evaluation execution module is used for calling the story template in single evaluation, selecting and loading materials for key information points through random extraction logic, generating personalized test content, and then presenting the personalized test content to a subject and collecting response data of the subject; and the memory evaluation module is used for calculating a memory function index according to the response data so as to evaluate the memory level. According to the method, through combination of the structured story scene and the multi-modal material random replacement, test contents with different contents and similar structural difficulty can be generated, the learning effect in repeated tests is effectively overcome, and the ecological validity and the retest reliability are remarkably improved.

A method for flexible bank addressing in digital computing-in-memory (DCIM). The method includes providing bank groups, each of the bank groups comprising a respective number of memory banks, each memory bank configured to store a corresponding portion of input feature map data. The method includes reading, during a first clock cycle, a first portion of the input feature map data from a first one of the bank groups and a second portion of the input feature map data from a second one of the bank groups. The method includes performing a first multiply—accumulate operation using the first portion and the second portion. The method includes reading, during a second clock cycle, a third portion of the input feature map data from the first bank group. The method includes performing a second multiply—accumulate operation using the second portion and the third portion.

A digital assistant system includes a digital memory configured to collecting data pertaining to a user from a plurality of user information sources, to extract relevant pieces of information from the collected data, and to generate new user data elements using an information extraction component, the new user data elements including the extracted relevant pieces of information. The new user data elements are tagged with content classification tags which indicate a type of content of the extracted pieces of information in the new user data elements and retention period tags which indicate retention periods for the new user data elements. Information from the user data elements is retrieved in response to receiving a prompt from a digital assistant artificial intelligence (AI) component. The retrieved information is provided to the digital assistant AI as user context information.

An event sensor including a pixel array and configured to produce a signal stream comprising event data in reaction to light incident on the pixel array. The event sensor includes: for each pixel of the pixel array a photovoltaic converter and an electronic converter connected to the photovoltaic converter. The photovoltaic converter and the electronic converter are configured to produce and store a digital current pixel value, which is dependent on the intensity of light incident on the photovoltaic converter; for each pixel of the pixel array a corresponding multi-bit digital storage configured to store a previous pixel value; and a readout processor connected to the electronic converter and the multi-bit digital storage and configured to generate a pixel event value of the event data based on a pixel subtraction result of subtracting the previous pixel value from the current pixel value.

A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports: a first mode where only one word line in the memory array is actuated during a column multiplexed memory access operation; and a second mode where one word line per sub-array is simultaneously actuated during an in-memory computation operation. An input / output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs to provide data read from the array in the first mode, and a sub-array data output coupled to each bit line input to provide weight data read from the array in the second mode. A computational circuit executes the in-memory computation as a function of feature data and the read weight data.