67 results about "Analog memory" patented technology

Analog memory-based activation functions for artificial neural networks may be provided. An apparatus may include at least two non-volatile memory devices connected in parallel such that a current may flow through one of the two non-volatile memory devices according to a voltage level of a drive current. To control which branch the input current flows through, each of the two non-volatile memory devices may be connected to a circuit element that may function as a switch, for example, a diode such as a semiconductor diode, a transistor, or other circuit element. Such an apparatus may implement analog memory-based activation functions, e.g., for analog memory-based artificial neural networks.

An image sensor pixel is provided that includes a single-photon avalanche diode (SPAD), an analog counter coupled to a cathode terminal of the SPAD, and a comparator having a first input coupled to a floating diffusion node in the analog counter, a second input configured to receive a reference voltage, and a clock input configured to receive a comparator clock signal from the analog counter. The image sensor pixel can further include an analog memory circuit selectively coupled to an output of the comparator. The analog memory circuit can include a read enable switch coupled between the output of the comparator and a storage node and a plurality of capacitors coupled to the storage node via respective switches.

Analog memory-based activation function for an artificial neural network can be provided. An apparatus can include at least two non-volatile memory devices connected in parallel such that the current

In one example, a method comprises determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal; and applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.

A pipeline of an analog memory based neural network with global partial storage is provided. A first synapse array in a hidden layer receives an input array from a previous layer during a feedforward operation. The input array is stored by the first synapse array during the feedforward operation. An input array is received by a second synapse array in the hidden layer during the feedforward operation. The second synapse array computes an output from the input array during the feedforward operation based on weights of the second synapse array. The stored input array is provided to the second synapse array from the first synapse array during a backpropagation operation. A correction value is received by the second synapse array during the backpropagation operation. The weights of the second synapse array are updated based on the correction value and the stored input array.

This application provides a calibration method and storage system for a memory and its internal detection circuit, belonging to the field of storage technology. In the solution provided by this application, the control circuit in the calibration circuit can control the word line driving circuit to charge or discharge the charging circuit, and can form a current path between the charging circuit and the ground terminal through a resistor configuration circuit to simulate the voltage change process on the word lines in the memory. During the simulation of voltage change, the control circuit can also acquire the detection result obtained by the internal detection circuit detecting the voltage of the detection node. Since this detection result reflects the detection sensitivity of the internal detection circuit to the voltage of the detection node, the detection parameters of the internal detection circuit when performing leakage current detection on the word lines in the memory can be calibrated based on this detection result. Therefore, the problem of inaccurate leakage current detection results due to differences in the detection sensitivity of the internal detection circuit itself can be effectively avoided.

A circuit includes a first pulse width modulator configured to generate a first pulse based on a first input; a second pulse width modulator configured to generate a second pulse based on a second input; a first differential circuit including a first transistor, a second transistor, a first resistor, and a second resistor; and a second differential circuit including a first transistor, a second transistor, a first resistor, and a second resistor. The gate of the first transistor of the first differential circuit is connected with the gate of the second transistor of the first differential circuit, and the gate of the first transistor of the second differential circuit is connected with the gate of the second transistor of the second differential circuit. The first pulse width modulator and the second pulse width modulator are configured to be controlled based on the first input and the second input.

Analog memory-based activation function for an artificial neural network can be provided. An apparatus can include at least two non-volatile memory devices connected in parallel such that the current

A memory computing system includes a cross array of storage cells, each having a cell transistor and a memristor connected in series between a select line and a bit line. A set of programming transistors is located outside the cross array and in a number less than the storage cells, selectively connected in parallel with the cell transistors in a common row in a write mode and isolated in a read mode. This configuration increases programming current without increasing cross array footprint, enables multi-level conductance states, and improves signal-to-noise ratio for analog memory computing. In some embodiments, the memory computing system is integrated with an image sensor die for on-sensor inferencing.

An analog memory device includes a first node and a second node. The first node includes a first floating gate, a second floating gate, and a capacitor. The first node first floating gate is connected to the first node second floating gate via the capacitor. The second node includes a first floating gate, a second floating gate, and a capacitor. The second node first floating gate is connected to the second node second floating gate via the capacitor. The second node is connected to the first node, and an analog state of the first node and an analog state of the second node continuously and synchronously decay with respect to time.

A digital-analog memory integrated deep learning accelerator system may include: a main digital device including a first array, the first array having digital circuits and configured to store weights for on-chip learning; an analog device including a second array, the second array having analog circuits and configured to update and store gradient information about the weights during the on-chip learning; and a sub-digital device including a third array, the third array having digital circuits and configured to store values read from the second array and to transfer a value exceeding a threshold to the first array. The digital-analog memory integrated deep learning accelerator system may perform a matrix-level learning process through an array set including the first array, the second array, and the third array. An artificial neural network learning method for a digital-analog memory integrated deep learning accelerator system is also disclosed.

The invention provides a loading method and device of a system and electronic equipment, the system comprises a programmable chip and a first memory, and the loading method of the system comprises the following steps: when the system enters an initialization state, controlling the programmable chip to enter an analog memory state; when the system completes the initialization state, sending a program loading instruction to the programmable chip; and according to the program loading instruction, controlling the programmable chip to cache the program data in the first memory, and loading the program data to the system. The first memory supported by the first processor is simulated through the programmable chip, interface configuration is completed, program data is loaded to the system, the support range of the processor guiding device is expanded, and the processor guiding device is suitable for providing a wider-range guiding FLASH memory for a specific processor and expanding the support range of the specific processor.

A method for optimizing the suppression of FMCW radar transceiver leakage and stationary clutter is provided, wherein the analog anti-interference signal generated after analog memory calibration and the real-time intermediate frequency signal are subjected to difference and amplification processing in the analog domain as analog memory compensation; the digital anti-interference signal generated after digital memory calibration and the real-time digital intermediate frequency signal after analog memory compensation are subjected to difference processing in the digital domain as digital memory compensation, thereby finally achieving deep compensation for transceiver leakage and stationary clutter. The present invention utilizes the characteristics that the transceiver leakage and environmental clutter of the FMCW radar are superimposed on the intermediate frequency signal, and realizes comprehensive and deep suppression of transceiver leakage and environmental clutter at the same time by performing analog memory feedback compensation and digital memory feedback compensation on the intermediate frequency signal.

Disclosed is an apparatus for computationally intensive applications, such as information technology applications requiring computational power. Disclosed is an apparatus arranged to provide an analog signal to at least one input of an analog compute-in-memory resistive matrix comprised in said apparatus, and to receive a digital signal from at least one direct-drive analog-to-digital converter in the output of said at least one analog compute-in-memory resistive matrix.

The invention belongs to the technical field of modulation carrier systems, and relates to a storage and calculation integrated energized radio frequency signal demodulation method and system, and the method comprises the following steps: inputting a to-be-tested analog radio frequency signal, and obtaining a sampling voltage vector; determining a signal center frequency according to the sampling voltage vector; constructing a down-conversion matrix according to the signal center frequency; and multiplying the down-conversion matrix by a low-pass filtering matrix to obtain an I / Q demodulation matrix, and mapping the I / Q demodulation matrix to a memristor cross array in a conductance form so as to demodulate the analog radio frequency signal to be detected. According to the invention, frequency mixing and low-pass signal demodulation are realized in a cross array through the simulation memory calculation capability of devices such as memristors.

A hybrid digital-analog memory device for secure storage and computation and an operating method thereof are disclosed. A nonvolatile memory device according to an embodiment includes a plurality of memory cells arranged in a matrix form; a plurality of word lines extending in a first direction, wherein each memory cell is connected with one of the plurality of word lines; a plurality of bit lines extending in a second direction different from the first direction, wherein each memory cell is connected with one of the plurality of bit lines; a word line control circuit connected with the word lines and configured to control the word lines; a first bit line control circuit configured to control the bit lines, wherein the first bit line control circuit is connected with a first end of each bit line; and a second bit line control circuit configured to control the bit lines, wherein the second bit line control circuit is connected with a second end of each bit line, the second end being opposite to the first end.

The application relates to the technical field of neural network hardware acceleration, in particular to a high-precision automatic deployment method for an analog memory-computation integrated accelerator; the method comprises the following steps: layer-by-layer statistics of activation values and weight distribution of a floating-point model with a verification set is carried out, a quantization scale factor is automatically updated to avoid information truncation; quantization parameters are constrained in a discrete value set that can be realized by a chip, an interlayer mathematical consistency relationship is established, and a cross-layer linkage updating mechanism is adopted to process parameter coupling; based on an additive Gaussian noise model, weight and activation dynamic ranges are jointly optimized from the perspective of improving end-to-end signal-to-noise ratio, amplitude compensation and cross-layer correction are carried out; with deployment precision or signal-to-noise ratio as the target, a closed-loop iteration is constructed between discrete quantization training and joint compensation until the precision meets the standard or the parameters converge; a weight programming file, a quantization parameter configuration file and an inference control file are generated, which are directly loaded by the chip. The application realizes high-precision automatic deployment of the analog memory-computation integrated accelerator.

The invention relates to a matrix quantization operation method and device based on an analog storage and calculation integrated circuit, and the method comprises the steps: enabling a preset quantization coefficient memory, an intermediate vector memory and a controller to be connected with a preset splicing unit, a vector number multiplication unit and a matrix multiplication unit, a preset analog-to-digital converter and a digital-to-analog converter are combined to construct a target simulation, storage and calculation integrated circuit; obtaining current working demand information of the target simulation storage and calculation integrated circuit, and determining a current working state type of the target simulation storage and calculation integrated circuit according to the current working demand information; and based on the current working state type, controlling the target simulation storage and calculation integrated circuit to execute a corresponding quantization matrix multiplication operation so as to obtain a final matrix multiplication result. Therefore, the problem that an application scene is seriously limited due to the fact that an existing simulation storage and calculation integrated circuit lacks support for grouping quantization matrix multiplication is solved.

Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

Analog memory-based activation function for an artificial neural network can be provided. An apparatus can include at least two non-volatile memory devices connected in parallel such that the current can flow through one of the two non-volatile memory devices depending on the voltage level driving the current. To control which branch an input current flows through, each of the two non-volatile memory devices can be connected to a circuit element that can function as a switch, for example, a diode such as a semiconductor diode, a transistor, or another circuit element. Such apparatus can implement an analog memory-based activation function, for example, for an analog memory-based artificial neural network.

Embodiments of the present disclosure are directed to an integrated circuit with a photonic processor and an electrical analog memory. The integrated circuit further includes an array of photonic intensity modulators coupled to the photonic processor via a first set of optical connections, and an array of photodetectors coupled to the photonic processor via a second set of optical connections. The electrical analog memory is directly coupled to the array of photodetectors and the array of photonic intensity modulators.

A method and an apparatus for processing an analog input signal and generating a corresponding analog output signal are disclosed. The input signal is supplied to an analog delay line comprising analog memory cells. A propagation signal causes the input signal to propagate through the sequence of memory cells in discrete time steps. Each memory cell is buffered and weighted by the stored analog parameters, and the sum of weighted memory cell values is accumulated as an analog signal. The result of accumulation is passed through an activation function. Multiple such blocks provide a convolutional neural network that works at extremely low power in comparison with its digital equivalent.

Method for Emulating an EEPROM Memory This description relates to a method for emulating an EEPROM memory in a phase-change memory (104) of a circuit integrating a microprocessor, the method comprising the following steps: defining a write granularity in lines of the phase-change memory as a function of the size of the data packets to be written (EEelement1, EEelement2, EEelement3); associating with each data packet a first error-correcting code (ECC1, ECC2, ECC3) calculated by a program (SW) executed by said microprocessor; and storing the error-correcting codes of the data packets in the same line as the packets. Figure for the abstract: Fig. 3

A memory macro includes a tracking wordline driver that drivers a wordline with a suppressed voltage. The suppressed voltage is made lower than the voltage used to drive wordlines in the memory array by an amount that a tracking wordline is driven with a suppressed voltage, which is a voltage that is held below the drain supply voltage. Suppressing the voltage on the tracking wordline causes tracking memory cell with average cell characteristic to emulate the slowest memory cells in a memory array. The tracking wordline with the suppressed voltage may be subjected to a mimicked wordline load. The tracking wordline with the suppressed voltage and the mimicked wordline load may also be used to enable a mimicked write drive used in write tracking. The tracking wordline with the suppressed voltage may also be used as input to a write delay circuit that times write operations.

A neuron circuit can switch between two functions: as an input neuron circuit, and as a hidden neuron circuit. An error circuit can switch between two functions: as a hidden error circuit, and as an output neuron circuit. A switching circuit is configured to be capable of changing the connections between the neuron circuit, a synapse circuit, and the error circuit. The synapse circuit includes an analog memory that stores data that corresponds to the connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a writing circuit that changes the data in the analog memory, and a weighting circuit that weights an input signal in reaction to the data of the analog memory and outputs the weighted output signal. The analog memory includes a transistor comprising an oxide semiconductor with extremely low off-state current.

The present invention relates to a printable ink (3) for use in manufacturing of an analog WORM (write once read many) memory device (10), the printable ink (3) comprising a solvent, a binder and a monomer being convertible to an electrically conducting polymer (4) through electrically induced polymerization. The present invention further relates to an analog WORM memory device (10) comprising such an ink (3).

Techniques facilitating automatic non-linearity correction for analog hardware are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an adjustment component that determines a non-linear correction term for an output of an array of analog memories based on a result of a matrix vector multiplication performed on the array of analog memories. The computer executable components can also comprise a rectification component that applies the non-linear correction term to additional outputs of the array of analog memories.

A circuit comprising: a first pulse width modulator configured to generate a first pulse based on a first input; a second pulse width modulator configured to generate a second pulse based on a second input; a first differential circuit including a first transistor, a second transistor, a first resistor, and a second resistor; and a second differential circuit including the first transistor, the second transistor, the first resistor, and the second resistor, wherein a gate of the first transistor of the first differential circuit and a gate of the second transistor of the first differential circuit, and a gate of the first transistor of the second differential circuit and a gate of the second transistor of the second differential circuit are configured to be controlled by the first pulse width modulator and the second pulse width modulator based on the first input and the second input.