8 results about "Analog memory" patented technology

Analog memory-based activation function for an artificial neural network can be provided. An apparatus can include at least two non-volatile memory devices connected in parallel such that the current

An analog memory device includes a first node and a second node. The first node includes a first floating gate, a second floating gate, and a capacitor. The first node first floating gate is connected to the first node second floating gate via the capacitor. The second node includes a first floating gate, a second floating gate, and a capacitor. The second node first floating gate is connected to the second node second floating gate via the capacitor. The second node is connected to the first node, and an analog state of the first node and an analog state of the second node continuously and synchronously decay with respect to time.

The application relates to the technical field of neural network hardware acceleration, in particular to a high-precision automatic deployment method for an analog memory-computation integrated accelerator; the method comprises the following steps: layer-by-layer statistics of activation values and weight distribution of a floating-point model with a verification set is carried out, a quantization scale factor is automatically updated to avoid information truncation; quantization parameters are constrained in a discrete value set that can be realized by a chip, an interlayer mathematical consistency relationship is established, and a cross-layer linkage updating mechanism is adopted to process parameter coupling; based on an additive Gaussian noise model, weight and activation dynamic ranges are jointly optimized from the perspective of improving end-to-end signal-to-noise ratio, amplitude compensation and cross-layer correction are carried out; with deployment precision or signal-to-noise ratio as the target, a closed-loop iteration is constructed between discrete quantization training and joint compensation until the precision meets the standard or the parameters converge; a weight programming file, a quantization parameter configuration file and an inference control file are generated, which are directly loaded by the chip. The application realizes high-precision automatic deployment of the analog memory-computation integrated accelerator.

Analog memory-based activation function for an artificial neural network can be provided. An apparatus can include at least two non-volatile memory devices connected in parallel such that the current can flow through one of the two non-volatile memory devices depending on the voltage level driving the current. To control which branch an input current flows through, each of the two non-volatile memory devices can be connected to a circuit element that can function as a switch, for example, a diode such as a semiconductor diode, a transistor, or another circuit element. Such apparatus can implement an analog memory-based activation function, for example, for an analog memory-based artificial neural network.

Embodiments of the present disclosure are directed to an integrated circuit with a photonic processor and an electrical analog memory. The integrated circuit further includes an array of photonic intensity modulators coupled to the photonic processor via a first set of optical connections, and an array of photodetectors coupled to the photonic processor via a second set of optical connections. The electrical analog memory is directly coupled to the array of photodetectors and the array of photonic intensity modulators.

This disclosure relates to a method, apparatus, computer-readable storage medium, and electronic device for determining memory power consumption, and pertains to the field of integrated circuit technology. The method for determining memory power consumption includes: receiving a memory control command; controlling an analog memory to enter different operating stages according to the memory control command; acquiring the original current variation curves of the analog memory in different operating stages; determining a target time period corresponding to a target operating stage according to the timing of the memory control command; extracting a stage current variation curve corresponding to the target operating stage from the original current variation curves according to the target time period to obtain a target current variation curve; selecting target performance parameters from a memory performance parameter table according to the target operating stage; and determining the memory power consumption based on the target performance parameters and the target current variation curve. This disclosure provides a method for determining memory power consumption.

The utility model discloses an automatic test system of Nand - flash memory, including base, control unit, vibrating device and sensor module, control unit locates in the base is used to electric connection Nand - flash memory to carry out test, vibrating device connects the base is used to drive the base vibration, sensor module electric connection control unit is used to obtain the measured state information of Nand - flash memory, this application is through setting vibrating device connection and drive base vibration can simulate Nand - flash memory is in vibration environment, simultaneously, sensor module electric connection control unit, can real - time acquisition Nand - flash memory's measured state information and feedback to control unit, such as the vibration frequency of base, control unit carries out read - write erase test to Nand - flash memory, under different vibration frequency, detects whether Nand - flash memory is normal work. Effectively solved the problem of lack of the operation stability test of Nand - flash memory under the car environment in relevant technology.

Imaging circuitry is provided that includes an array of image pixels, where each image pixel in the array includes a single-photon avalanche diode (SPAD) coupled to a plurality of counters configured to obtain an in-pixel histogram and time gate driver circuitry configured to output a plurality of non-overlapping time gate pulses to the plurality of counters. Each image pixel can further include a pulse generator having an input coupled to the SPAD. Each of the counters can have a first input coupled to an output of the pulse generator and a second input configured to receive a respective one of a plurality of time gate signals. Each of the counters can further include an analog memory circuit having one or more capacitors.