21 results about "Analog memory" patented technology

In one example, a method comprises determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal; and applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.

Analog memory-based activation function for an artificial neural network can be provided. An apparatus can include at least two non-volatile memory devices connected in parallel such that the current

An analog memory device includes a first node and a second node. The first node includes a first floating gate, a second floating gate, and a capacitor. The first node first floating gate is connected to the first node second floating gate via the capacitor. The second node includes a first floating gate, a second floating gate, and a capacitor. The second node first floating gate is connected to the second node second floating gate via the capacitor. The second node is connected to the first node, and an analog state of the first node and an analog state of the second node continuously and synchronously decay with respect to time.

Disclosed is an apparatus for computationally intensive applications, such as information technology applications requiring computational power. Disclosed is an apparatus arranged to provide an analog signal to at least one input of an analog compute-in-memory resistive matrix comprised in said apparatus, and to receive a digital signal from at least one direct-drive analog-to-digital converter in the output of said at least one analog compute-in-memory resistive matrix.

A hybrid digital-analog memory device for secure storage and computation and an operating method thereof are disclosed. A nonvolatile memory device according to an embodiment includes a plurality of memory cells arranged in a matrix form; a plurality of word lines extending in a first direction, wherein each memory cell is connected with one of the plurality of word lines; a plurality of bit lines extending in a second direction different from the first direction, wherein each memory cell is connected with one of the plurality of bit lines; a word line control circuit connected with the word lines and configured to control the word lines; a first bit line control circuit configured to control the bit lines, wherein the first bit line control circuit is connected with a first end of each bit line; and a second bit line control circuit configured to control the bit lines, wherein the second bit line control circuit is connected with a second end of each bit line, the second end being opposite to the first end.

The application relates to the technical field of neural network hardware acceleration, in particular to a high-precision automatic deployment method for an analog memory-computation integrated accelerator; the method comprises the following steps: layer-by-layer statistics of activation values and weight distribution of a floating-point model with a verification set is carried out, a quantization scale factor is automatically updated to avoid information truncation; quantization parameters are constrained in a discrete value set that can be realized by a chip, an interlayer mathematical consistency relationship is established, and a cross-layer linkage updating mechanism is adopted to process parameter coupling; based on an additive Gaussian noise model, weight and activation dynamic ranges are jointly optimized from the perspective of improving end-to-end signal-to-noise ratio, amplitude compensation and cross-layer correction are carried out; with deployment precision or signal-to-noise ratio as the target, a closed-loop iteration is constructed between discrete quantization training and joint compensation until the precision meets the standard or the parameters converge; a weight programming file, a quantization parameter configuration file and an inference control file are generated, which are directly loaded by the chip. The application realizes high-precision automatic deployment of the analog memory-computation integrated accelerator.

The invention relates to a matrix quantization operation method and device based on an analog storage and calculation integrated circuit, and the method comprises the steps: enabling a preset quantization coefficient memory, an intermediate vector memory and a controller to be connected with a preset splicing unit, a vector number multiplication unit and a matrix multiplication unit, a preset analog-to-digital converter and a digital-to-analog converter are combined to construct a target simulation, storage and calculation integrated circuit; obtaining current working demand information of the target simulation storage and calculation integrated circuit, and determining a current working state type of the target simulation storage and calculation integrated circuit according to the current working demand information; and based on the current working state type, controlling the target simulation storage and calculation integrated circuit to execute a corresponding quantization matrix multiplication operation so as to obtain a final matrix multiplication result. Therefore, the problem that an application scene is seriously limited due to the fact that an existing simulation storage and calculation integrated circuit lacks support for grouping quantization matrix multiplication is solved.

Analog memory-based activation function for an artificial neural network can be provided. An apparatus can include at least two non-volatile memory devices connected in parallel such that the current can flow through one of the two non-volatile memory devices depending on the voltage level driving the current. To control which branch an input current flows through, each of the two non-volatile memory devices can be connected to a circuit element that can function as a switch, for example, a diode such as a semiconductor diode, a transistor, or another circuit element. Such apparatus can implement an analog memory-based activation function, for example, for an analog memory-based artificial neural network.

Embodiments of the present disclosure are directed to an integrated circuit with a photonic processor and an electrical analog memory. The integrated circuit further includes an array of photonic intensity modulators coupled to the photonic processor via a first set of optical connections, and an array of photodetectors coupled to the photonic processor via a second set of optical connections. The electrical analog memory is directly coupled to the array of photodetectors and the array of photonic intensity modulators.

A weight confirmation method for analog synaptic devices of an artificial neural network includes: learning artificial neural network hardware based on artificial analog memory devices using an artificial neural network learning algorithm; after the learning of the artificial neural network hardware, reading a total weight of a pair of synaptic devices; comparing the total weight of the pair of synaptic devices with 0; applying weights to a positive synaptic device and a negative synaptic device of the pair of synaptic devices, respectively; and confirming the total weight of the pair of synaptic devices in accordance with the weight of the positive synaptic device and the weight of the negative synaptic device. A retention problem of analog synaptic devices is overcome and thus the artificial neural network may stably operate.

In one example disclosed herein, the system comprises an analog memory-based computation engine for performing operations in a first layer of a neural network, and a digital memory-based computation engine for performing operations in a second layer of the neural network distinct from the first layer. The system optionally comprises a dynamic weight engine for performing operations in a third layer of the neural network distinct from the first and second layers.

This disclosure relates to a method, apparatus, computer-readable storage medium, and electronic device for determining memory power consumption, and pertains to the field of integrated circuit technology. The method for determining memory power consumption includes: receiving a memory control command; controlling an analog memory to enter different operating stages according to the memory control command; acquiring the original current variation curves of the analog memory in different operating stages; determining a target time period corresponding to a target operating stage according to the timing of the memory control command; extracting a stage current variation curve corresponding to the target operating stage from the original current variation curves according to the target time period to obtain a target current variation curve; selecting target performance parameters from a memory performance parameter table according to the target operating stage; and determining the memory power consumption based on the target performance parameters and the target current variation curve. This disclosure provides a method for determining memory power consumption.

The invention relates to a semiconductor device and an electronic apparatus. The neuron circuit is capable of switching two functions: a function as an input neuron circuit and a function as a hidden neuron circuit. The error circuit can switch two functions: function as a hidden error circuit and function as an output neuron circuit. The switching circuit is configured so as to be capable of changing connections among the neuron circuit, the synapse circuit, and the error circuit. The synapse circuit includes an analog memory storing data corresponding to a connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a write circuit that changes data in the analog memory; and a weighting circuit that weights an input signal in accordance with the data of the analog memory and outputs the weighted output signal. The analog memory includes a transistor including an oxide semiconductor with extremely low off-state current.

In one example, a method comprises determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal; and applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.

A magnetic wall utilization type analog memory element (100) according to the present application includes a magnetic wall driving layer (1) having a magnetic wall (DW), a first region (1a), a second region (1b), and a third region (1c) between the first region and the second region; a magnetization fixed layer (5) disposed in the third region via a non-magnetic layer (6); and a lower electrode layer (4) disposed on a second surface opposite to a first surface of the third region on which the magnetization fixed layer is disposed, at a position overlapping the magnetization fixed layer in a plan view.

The utility model discloses an automatic test system of Nand - flash memory, including base, control unit, vibrating device and sensor module, control unit locates in the base is used to electric connection Nand - flash memory to carry out test, vibrating device connects the base is used to drive the base vibration, sensor module electric connection control unit is used to obtain the measured state information of Nand - flash memory, this application is through setting vibrating device connection and drive base vibration can simulate Nand - flash memory is in vibration environment, simultaneously, sensor module electric connection control unit, can real - time acquisition Nand - flash memory's measured state information and feedback to control unit, such as the vibration frequency of base, control unit carries out read - write erase test to Nand - flash memory, under different vibration frequency, detects whether Nand - flash memory is normal work. Effectively solved the problem of lack of the operation stability test of Nand - flash memory under the car environment in relevant technology.

Examples herein provide a memory device comprising an eDRAM memory cell.SOLUTION: The memory device includes a write circuit formed at least partially above the storage capacitor and a read circuit formed at least partially below the storage capacitor, a computational near memory device bonded to the memory device, a processor, and an interface from the memory device to the processor. In some examples, a circuit comprising one or more of a controller, a multiplexer, or a register for providing an output of a memory device is included to emulate an output read rate of an SRAM memory device. The bonding of the surface of the memory device can be to a computational near memory device or other circuitry.SELECTED DRAWING: Figure 4

The present invention relates to a self-adaptive learning method and device for efficiently training a deep neural network on neuromorphic hardware by utilizing a hybrid architecture in which an analog backbone network and a digital attention block are combined, in order to overcome performance degradation caused by non-ideal characteristics of an analog memory device, and to a recording medium for implementing same.

The application belongs to the technical field of modulated carrier systems, and relates to a memory-computing integrated energy-enabled radio frequency signal demodulation method and system, which comprises the following steps: inputting a to-be-measured analog radio frequency signal to obtain a sampling voltage vector; determining a signal center frequency according to the sampling voltage vector; constructing a down-conversion matrix according to the signal center frequency; multiplying the down-conversion matrix and a low-pass filter matrix to obtain an I / Q demodulation matrix; and mapping the I / Q demodulation matrix to a memristor cross array in the form of conductance, so as to demodulate the to-be-measured analog radio frequency signal. The application realizes mixing and low-pass signal demodulation in the cross array of the memristor and other devices through the analog memory computing capacity of the devices.

Imaging circuitry is provided that includes an array of image pixels, where each image pixel in the array includes a single-photon avalanche diode (SPAD) coupled to a plurality of counters configured to obtain an in-pixel histogram and time gate driver circuitry configured to output a plurality of non-overlapping time gate pulses to the plurality of counters. Each image pixel can further include a pulse generator having an input coupled to the SPAD. Each of the counters can have a first input coupled to an output of the pulse generator and a second input configured to receive a respective one of a plurality of time gate signals. Each of the counters can further include an analog memory circuit having one or more capacitors.