131 results about "Neuron circuit" patented technology

The present disclosure provides a method and an apparatus for operating an in-memory computing architecture applied to a neural network and a device, the method includes: generating a mono-pulse input signal based on discrete time coding; inputting the mono-pulse input signal into a memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array; and controlling a neuron circuit of the in-memory computing architecture to output a mono-pulse output signal based on discrete time coding according to the bit line current signal, wherein the mono-pulse output signal is configured as a mono-pulse input signal of a memory array of the next layer of neural network in the next in-memory computing cycle.

The invention discloses a brain-computer interface signal identification circuit based on a memristor neural network. The brain-computer interface signal identification circuit is composed of three neuron circuits. Each neuron circuit is composed of nine parallel branches and comprises a signal input module, a weight adjusting module, a first summing module, a memristor, a second summing module, a sampling module and a comparison module. In a single neuron circuit, after nine paths of input signals Vin1-Vin9 are respectively processed by signal input modules, weight adjusting modules, summation modules (1) and memristors of nine parallel branches, the nine paths of signals are combined together and pass through a single summation module (2), a sampling module and a comparison module, and a single identification signal of the neuron circuit is output. According to the designed circuit, a memristor neural network circuit is built by using resistance plasticity and threshold characteristics of a memristor, the meaning of a brain-computer interface signal can be preliminarily identified through a self-learning mechanism of the memristor, and the identification precision of the brain-computer interface signal can be remarkably enhanced.

The invention discloses a neuron circuit and brain-like computing system based on multi-neuromorphic behaviors, and the neuron circuit maps an appreciation-Ross model to the field of physical circuits through a capacitance dynamic response mechanism and the cross-interval nonlinear characteristics of a metal-oxide semiconductor field effect transistor. Then the expanded appreciation-Ross model is realized through the design of a metal-oxide semiconductor field effect transistor; the neuron circuit comprises a membrane voltage circuit, a slow variable circuit and a recovery variable circuit. The membrane voltage circuit is used for receiving an input signal and accumulating membrane voltage; the slow variable circuit is used for accumulating a slow variable according to the membrane voltage and enabling the neuron circuit to enter a hyperpolarization stage after the slow variable is greater than a preset threshold value; the recovery variable circuit is used for outputting a recovery variable according to the film voltage delay and resetting the film voltage to a resting potential through the recovery variable.

Disclosed in the present invention is an FPGA-technology-based neuron circuit implementation method using multi-segment linear fitting. The method comprises: first, on the basis of the parity and value range of a hyperbolic tangent function in combination with a multi-segment linear fitting algorithm, processing the function, then designing a neuron circuit module for solution, performing simulation verification of implementability by means of software, and finally burning a program into an FPGA to observe consistency with the simulation verification by means of an oscilloscope. In the present invention, high-precision periodic signals and chaotic signals are generated on an FPGA by using a high-speed and high-precision multi-segment linear fitting algorithm with low resource consumption, so that abnormal discharge behaviors of an FHN neuron circuit can be more visually observed on hardware devices. The present invention provides a new method for using an FPGA to generate improved FHN abnormal discharge signals including a hyperbolic tangent function, the principle of implementing the hyperbolic tangent function by means of the FPGA can be extended to other complex functions, such as an exponential function, a logarithmic function and a transcendental function, and the present invention can be widely applied to the disciplines and fields of nonlinear neurons, intelligent control, etc.

The invention discloses a synaptic plastic mechanism bionic circuit based on a threshold symmetric memristor, and relates to the technical field of bionic circuits, the bionic circuit comprises a pre-synaptic neuron circuit, the threshold symmetric memristor and a post-synaptic neuron circuit; the bionic circuit is divided into an excitatory synaptic moldability mechanism circuit and an inhibitory synaptic moldability mechanism circuit according to a synaptic moldability mechanism; the design method of the circuit comprises the following steps: firstly, designing neuron waveforms before and after synapse, then traversing changes of memristive synapse conductance values at different time intervals to obtain a corresponding curve of the conductance changes and the time intervals, verifying the fitting degree of a biological synapse plastic mechanism curve and the curve, and if the fitting degree is low, determining that the biological synapse plastic mechanism curve is not matched with the curve. And if not, redesigning the pulse waveforms before and after synapse. The synaptic plasticity mechanism simulated by the bionic circuit provided by the invention and a biological synaptic STDP mechanism model have a small fitting error, the provided design method is higher in universality, circuit parameters can be adjusted according to different memristors, and different forms of biological synaptic plasticity mechanisms can be simulated.

Structures including multiple magnetic-tunnel-junction layer stacks and methods of forming such structures. The structure comprises a first magnetic-tunneling-junction layer stack, a second magnetic-tunneling-junction layer stack connected in a series connection to the first magnetic-tunneling-junction layer stack, and a pulsed power supply connected to the first and second magnetic-tunneling-junction layer stacks.

The invention relates to an event trigger type neuron circuit based on a volatile memristor. The event trigger type neuron circuit comprises a signal transmission module and a coding module, the signal transmission module is used for converting the received illumination signal into an output voltage and transmitting the output voltage to the coding module; wherein the output voltage is positively correlated with the intensity of the illumination signal; and the coding module is used for obtaining an oscillation coding signal according to the variable quantity of the output voltage. According to the technical scheme, the illumination signal is converted into the voltage, the oscillation coding signal consistent with LIF neuron characteristics is obtained through the variable quantity of the output voltage, and the output voltage can be changed according to the increase and decrease of the identification illumination intensity and is also consistent with the characteristics of an event driving structure; voltage coding output is carried out on illumination changes by utilizing a simple circuit structure, and development of event-driven structure research in brain-like calculation is promoted to a certain extent.

The application discloses a kind of nonvolatile memory-based pulse neuron circuit, it is related to the technical field of pulse neural network.The nonvolatile memory-based pulse neuron circuit includes: voltage dividing resistor network, current mirror circuit and MRAM pulse neuron module with temperature accumulation effect;Wherein, the voltage dividing resistor network receives target synapse array pulse signal and carries out voltage dividing processing to the target synapse array pulse signal, generates voltage dividing signal;The current mirror circuit is connected with the voltage dividing resistor network, and the current signal of the MRAM pulse neuron module is output according to the voltage dividing signal adaptation;The MRAM pulse neuron module is connected with the current mirror circuit, and the current signal is accumulated according to the temperature, and when temperature accumulation reaches threshold temperature, emits pulse signal.

The present application relates to a neural network circuit, comprising a plurality of neuron circuits and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive input and control signals from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synapse circuit comprises at least: a first transistor, a weight unit, a second transistor, a third transistor, and a fourth transistor; the present application also relates to an electronic device comprising the aforementioned neural network circuit.

A neural network device according to an embodiment includes a plurality of synapse circuits and a plurality of neuron circuits. A first neuron circuit out of the neuron circuits includes an input circuit, a charge holding circuit, a comparison circuit, a firing circuit, a charge control circuit, and a control signal output circuit. When a determination signal changes from a second value to a first value, the firing circuit outputs a spike signal. The control signal output circuit outputs a control signal indicating a comparison voltage that is based on an excess component of a membrane potential exceeding a threshold potential. In response to acquiring the spike signal from the first neuron circuit, a first synapse circuit out of the synapse circuits that acquires the spike signal from the first neuron circuit outputs a synaptic current of a current amount corresponding to the control signal and a synaptic weight.

The present invention discloses a pulse neural network circuit and an operation method thereof. The pulse neural network circuit includes a bit line input synaptic array and a neuron circuit. The bit line input synaptic array includes a plurality of page buffers, a plurality of bit line transistors, a plurality of bit lines, a plurality of storage units, a word line, a plurality of source lines and a plurality of source line transistors. The page buffer is used to provide a plurality of data signals. Each bit line transistor is electrically connected to one of these page buffers. Each bit line receives one of these data signals. These source line transistors are connected together. The neuron circuit is used to output a feedback pulse.

The invention discloses synaptic circuits, a method, equipment and a medium for avoiding displacement current of a ferroelectric tunnel junction, and relates to the technical field of pulse neural networks, the synaptic circuits and the post-neuron circuit are of the same structure, the synaptic circuits are used for generating tunneling current when voltage difference exists at two ends of the ferroelectric tunnel junction, and the post-neuron circuit is used for generating the displacement current when voltage difference exists at two ends of the ferroelectric tunnel junction. An internal capacitor in the ferroelectric tunnel junction is controlled to discharge, the voltage in the synaptic circuit is raised, and a charging voltage is output when a pre-synaptic neuron pulse signal is received; the post neuron circuit is respectively connected with the plurality of synaptic circuits and is used for outputting post-synaptic neuron pulse signals according to the accessed charging voltage; and the synaptic circuit is also used for changing the voltage amplitude applied to the two ends of the ferroelectric tunnel junction according to the time interval between the received post-synaptic neuron pulse signal and the input signal, so that the reading error and the pulse neural network application bottleneck caused by the capacitance current characteristic and the resistance current characteristic of the ferroelectric tunnel junction are solved.

A neural network device according to an embodiment includes a plurality of neuron circuits and a plurality of synapse circuits. In a case where an internal state value of a second neuron circuit is larger than a set determination reference value, a first synapse circuit among the synapse circuits executes potentiation processing to increase the degree of influence of a synaptic weight on a synapse signal in response to acquiring the input spike from the first neuron circuit. In response to outputting an output spike being a spike signal from the second neuron circuit, the first synapse circuit executes attenuation processing to decrease the degree of influence of the synaptic weight on the synapse signal.

The application discloses a three-dimensional Hindmarsh-Rose neuron model circuit under periodic excitation, comprising three neuron circuits and a matching circuit, and is composed of nine operational amplifiers and two multiplier circuits. The three-dimensional Hindmarsh-Rose neuron model circuit under periodic excitation can provide hardware support for studying neuron dynamic behaviors under periodic excitation, and has important theoretical research significance and practical application value.

The invention relates to a physical simulation model of a ferroelectric neuron circuit and a design method thereof, and the method comprises the steps: building the physical simulation model of the ferroelectric neuron circuit according to the corresponding relation between the polarization intensity of a ferroelectric layer in a ferroelectric field effect transistor and the voltage of the ferroelectric layer, the surface charge density of the ferroelectric layer, and the source voltage of the ferroelectric field effect transistor, and predicting the working state of the ferroelectric neuron circuit according to the physical simulation model. Meanwhile, a corresponding experimental design method is further developed according to the provided model. The physical simulation model combining the ferroelectric polarization flipping and the dynamic characteristics of the ferroelectric neuron circuit has very high physical reliability; the design method provided by the invention can guide the specific design of the experiment, significantly reduces the trial and error cost of the experiment manufacturing of the ferroelectric neuron circuit, and provides a physical basis for the further development of the ferroelectric neuron circuit in electronic design automation software.

The invention provides a high-fidelity neuron circuit based on a full-printed electrochemical transistor, which comprises an amplification unit, a reset OECT, a film capacitor element, a feedback capacitor element, a current input end, a voltage source VDD and a common grounding end GND, and is characterized in that a grid electrode of a first-stage OECT in the amplification unit is connected with one end of the film capacitor element and is connected with the current input end at a connection node; the drain electrode of the first-stage OECT is connected to one end of the corresponding resistor to form a first-stage inverter; an output node is formed at a connection node of the resistor and the drain electrode of the first-stage OECT; the output node is connected with the grid electrode of the next stage of OECT; the source electrode of each stage of OECT is connected with a common grounding end GND, and a voltage source pin VDD is connected with the other ends of the four resistors; one end of the feedback capacitor element is connected to the output node of the last-stage OECT; the grid electrode of the reset transistor is connected with the output node of the last-stage OECT, the source electrode of the reset transistor is connected to the input port of the amplification unit, the structure is remarkably simplified, and large-scale integration is facilitated.

A neural network device according to an embodiment includes a plurality of synapse circuits and a plurality of neuron circuits. A first neuron circuit includes a first terminal to which a synaptic current is supplied. The first neuron circuit includes a secondary battery element, a spike generation circuit, and a reset control circuit. The secondary battery element accumulates a charge according to the synaptic current supplied to the first terminal. The spike generation circuit generates a spike signal when the membrane potential generated from the secondary battery element is larger than a threshold potential being a predetermined potential. The reset control circuit releases the charge accumulated in the secondary battery element during a refractory period being a predetermined time after generation of the spike signal.

Disclosed is a spike neural network circuit according to an embodiment of the present disclosure, which includes a self-correcting control circuit that generates an input signal and a first control code, a bias voltage generation circuit that generates a first bias voltage based on the first control code, a synaptic circuit including a first synaptic column that performs an operation of the input signal and a first weight signal and generates a first operation signal, a neuron circuit including a first neuron that generates a first output signal based on a comparison of the first operation signal and a threshold voltage, and a spike comparison circuit that generates a first comparison signal corresponding to a difference between the first output signal and a reference number, and the self-correcting control circuit further generates a second control code for correcting the first bias voltage.

An apparatus comprises a bias current generation circuit configured to generate a bias current, a synapse circuit including a weight register storing a weight value and configured to perform a charge operation based on the input spike signal, the bias current, and the weight value, a membrane capacitor having a potential determined based on the charge operation of the synapse circuit, and a neuron circuit configured to generate an output spike signal based on a comparison between the potential of the membrane capacitor and a threshold potential. The bias current generation circuit comprises a self-correction circuit, and the self-correction circuit comprises a target input spike register storing a value related to a target number of input spikes and is configured to correct the bias current generated by the bias current generation circuit based on the value related to the target number of input spikes.

The present application relates to a neural network circuit, including a plurality of neuron circuits and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive an input and a control signal from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein, the electronic synapse circuit at least includes a switching unit, an input unit and a weight calculation unit; the present application also relates to an electronic system including the neural network circuit as described above and an electronic device.

The present application relates to the field of artificial neuromorphics, and provides an artificial neuron circuit based on a volatile threshold switching device. A membrane potential generation circuit is used for generating different membrane potentials under different input currents and different external reset voltages; a slow variable generation circuit is used for generating a slow variable; a membrane potential reset circuit comprises a volatile threshold switching device and an external reset voltage excitation source; the external reset voltage excitation source is used for providing different external reset voltages, so that the membrane potential and the slow variable are changed, and a spiking behavior of biological neurons is simulated; and the volatile threshold switching device is used for realizing a membrane potential reset function. Compared with traditional CMOS-circuit-based neurons, the neuron circuit provided by the present application requires a greatly reduced number of transistors and reduced hardware and power consumption overhead, has the characteristics of simple structure, high flexibility and rich functions, and is beneficial to large-scale integration in a hardware pulse neural network.

The invention discloses an adjustable activation neuron circuit based on a phase change memory and a multilayer reasoning acceleration device, and relates to the technical field of micro-nano electronics, the adjustable activation neuron circuit comprises a neuron input end used for receiving data to be activated, and a neuron output end used for outputting data after nonlinear activation processing; the activation parameter adjusting circuit is connected with the activation function circuit, the activation function circuit comprises a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a phase change memory and an operational amplifier, the inverting input end of the operational amplifier receives a data signal to be activated, the non-inverting input end of the operational amplifier is grounded, and the output end of the operational amplifier serves as a neuron output end; the activation parameter adjusting circuit is used for adjusting the resistance state of the phase change memory through a pulse signal and changing the nonlinear relation between the output voltage and the input current. Based on the physical characteristics of the phase change memory, the neuron circuit with the continuously adjustable activation function is developed, and the data processing capability of a neural network is improved.

The invention discloses a memristive coupling neuron circuit based on an N-type local active memristor. The memristive coupling neuron circuit is composed of a first memristive neuron module, a second memristive neuron module and a synaptic module. The N-type local active memristor is an overall passive but local active memristor, and shows an N-type negative differential conductivity characteristic in a DC V-I curve. Two memristive neuron modules are coupled through an N-type local active memristor to form a memristive coupling neuron circuit, and two neurons reproduce the Smale paradox phenomenon and the conversion from oscillation to chaos by adjusting appropriate model parameters of the coupling memristor. The memristor coupling neuron circuit fills the blank of research of using an N-type local active memristor coupling memristor neuron circuit in the prior art, and lays a certain foundation for application of the memristor coupling neuron circuit based on the N-type local active memristor in neuromorphic calculation.

Convolutional neural networks (CNN) or spiking neural networks (SNN) are usually applied for implementation. Although CNNs can be realized purely digitally, they require a lot of energy due to the high processing power (MAC structures). SNNs can usually only be implemented with analog components and are therefore difficult to implement in circuits with a technology node below 10 nm. The present disclosure is aimed to realize electronic neurons that process pulse-width modulated signals. These neurons encode the analog value in the length of the pulse and can be processed digitally. The combination of these neurons with an FPGA is particularly advantageous. The routing structure of the FPGA can further be configured for forwarding the pulse-width modulated signals. The configuration data of the FPGA can further be used alternatively for the weight data of the neurons.

The invention relates to a gain-adjustable neuron circuit and a control method thereof, the gain-adjustable neuron circuit comprises a memristive element, a capacitor and a resistor, one end of the memristive element is connected with the capacitor in parallel, then is connected with the resistor in series, and is connected with a driving power supply; the memristive element comprises an MIM structure, a heating module for providing a thermal field for the MIM structure and a substrate for providing support for the whole memristive element, the MIM structure comprises a top electrode, a functional layer and a bottom electrode which are sequentially distributed from top to bottom, the heating module comprises a heat conduction layer and a heating layer which are sequentially distributed, and the heating layer is in contact with the MIM structure through the heat conduction layer for heat transfer; the top electrode is connected with driving type voltage input, and the bottom electrode is grounded; one end of the heating layer is connected with modulation type voltage input, and the other end is grounded; and a port, connected with the resistor, of the memristor element is a voltage output end. Compared with the prior art, the pulse response to driving type input can be realized, and the dynamic adjustment of the response gain is also realized.

The invention discloses an adaptive structure LIF neuron circuit, which comprises a current integration module, a voltage amplification module, a voltage positive feedback module, a voltage reset module and an adaptive module, and is characterized in that the current integration module is composed of an input current source Iin and an integration capacitor C1, and the voltage amplification module is composed of two stages of c-OECT inverters in cascade connection; each level of c-OECT phase inverter is composed of a pair of n-OECT and p-OECT, namely M2-M5, the voltage positive feedback module is composed of a capacitor C2, the voltage positive feedback module and the capacitor C1 jointly form a capacitance voltage division network, the voltage reset module is composed of a transistor M1, and the self-adaption module is composed of a resistor R1, a resistor R2, a resistor R3, a capacitor C3, two n-OECTs and a p-OECT. The learning behavior of biological neurons is simulated, a neuromorphic device capable of simulating neurosynaptic plasticity can be developed, an electronic device conforming to neuromorphic calculation characteristics can be developed, and the method can be applied to neuron calculation, brain-like intelligent systems and large-scale neural network development.

The application discloses a double-time-constant adaptive neuron circuit with leakage path control, comprising a leakage integration circuit and an adaptive leakage path control circuit; the leakage integration circuit is used for accumulating input signals, and outputs a voltage pulse to the adaptive leakage path control circuit when the accumulated input signals reach a preset firing threshold; the adaptive leakage path control circuit is used for driving and controlling voltage variation according to the voltage pulse output by the leakage integration circuit, and adjusting the leakage current of the leakage integration circuit through the variation of the control voltage. The application utilizes the kinetic characteristics of the volatile memristor to efficiently realize the neuron function, and utilizes the adaptive structure introduced in the leakage circuit to efficiently realize the frequency adaptive function, and the control signal has the double-time-constant variation characteristics, thereby providing a core functional component for the intelligent bionic system.

The present invention relates to a power-free neuron circuit that utilizes a p‑n‑p‑n diode for the purpose of small area and low power consumption. According to one embodiment, the neuron circuit generates an electric potential by charging a current input from a synapse through a capacitor. If the generated electric potential is greater than a threshold value, a pulse voltage corresponding to the generated electric potential can be generated and output by a p‑n‑p‑n diode connected to the capacitor.

Minimize the loss of information transmitted. [Solution] The neural network device according to the embodiment comprises a plurality of synaptic circuits and a plurality of neuron circuits. The first neuron circuit among the plurality of neuron circuits is supplied with synaptic current to its first terminal from each of the first synaptic circuits among the plurality of synaptic circuits. The first neuron circuit has a charge storage circuit, a spike output circuit and a cutoff circuit. The charge storage circuit stores charge according to the synaptic current and generates a membrane potential according to the stored charge. The spike output circuit outputs a spike signal when the membrane potential is greater than a preset threshold potential. The cutoff circuit stops the supply of synaptic current from the first terminal to the charge storage circuit during a cutoff period, which is a predetermined time after the spike signal is output.

A logic gate with a neuron circuit which is used in electronic logic circuits, enables the arithmetic inputs to give output signal over the threshold value depending on a set threshold value according to the used AND, OR and MAJORITY logic gates, and enables to realize the logic processes by adjusting the triggering threshold value.