140 results about "Neuronal models" patented technology

A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Methods for managing memory in a processing system are described whereby memory can be allocated among a plurality of elements and rules configured for each element such that the parallel execution of the spiking networks is most optimal.

A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Neuronal network and methods for operating neuronal networks comprise a plurality of units, where each unit has a memory and a plurality of doublets, each doublet being connected to a pair of the plurality of units. Execution of unit update rules for the plurality of units is order-independent and execution of doublet event rules for the plurality of doublets is order-independent.

A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. The format is specifically tuned for neural systems and specialized neuromorphic hardware, thereby serving as a bridge between developers of brain models and neuromorphic hardware manufactures.

Disclosed is a method and apparatus for signal processing and signal pattern recognition. According to some embodiments of the present invention, events in the signal to be processed/recognized may be used to pace or clock the operation of one or more processing elements. The detected events may be based on signal energy level measurements. The processing/recognition elements may be neuron models. The signal to be processed/recognized may be a speech signal.

The invention provides an Izhikevich neural network synchronous discharging simulation platform based on an FPGA. The simulation platform comprises an FPGA neural network computing processor and an upper computer which are connected with each other. The FPGA neural network computing processor comprises an FPGA chip, an off-chip memorizer array and an Ethernet communication module, wherein the FPGA chip receives an upper computer control signal output by the off-chip memorizer array, and receives a presynaptic membrane potential signal output by the off-chip memorizer array. The upper computer is in communication with the FPGA chip and the off-chip memorizer array through a VB programming realization man-machine operating interface and the Ethernet communication module, and a neural network model is established on the FPGA chip through Verilog HDL language programming. The Izhikevich neural network synchronous discharging simulation platform has the advantages that the hardware modeling of the phenotype and physiological type neural network model is achieved through an animal-free experiment serving as a biological neural network on the basis of an FPGA neural network experiment platform conducting computation at a high speed, and the consistency with true biological nerve cells on the time scale can be achieved.

The invention discloses an image classification method based on a pulse neural network. The method comprises a step of encoding an externally input image analog quantity into a pulse time series, a step of adding time delay information to the pulse time series and storing the pulse time sequence with the added time delay information into an FIFO memory for buffering, a step of inputting the pulsetime sequence with the currently added time delay information into an IF pulse neuron model to generate a neuron membrane voltage signal, wherein a pipeline architecture is adopted by the IF pulse neuron model and a neuron model calculation method is optimized, and a step of generating a neural pulse sequence based on a Poisson distribution by comparing the membrane voltage signal and a thresholdand carrying out classification and judgment on the membrane voltage signal. According to the image classification method, the pulse neural network has powerful computing power and can simulate various neuron signals and arbitrary continuous functions, the operation efficiency is high, and so the pulse neural network has a hardware realization value.

A neuromorphic memory system including neuromorphic memory arrays. Each neuromorphic memory array includes rows and columns of neuromorphic memory cells. A column of postsynaptic circuits is electrically coupled to postsynaptic spike timing dependent plasticity (STDP) lines. Each postsynaptic STDP line is coupled to a row of neuromorphic memory cells. A column of summing circuits is electrically coupled to postsynaptic leaky integrate and fire (LIF) lines. Each postsynaptic LIF line is coupled to the row of neuromorphic memory cells at a respective memory array. Each summing circuit provides a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit.

The invention discloses an image segmenting method based on improvement of an intersecting visual cortical model. The method comprises the following steps of: firstly improving ICM basic model, establishing a network on the basis of improved ICM basic model, initiating the network parameter, inputting the original image to be segmented, self-adaptively adjusting each parameter in each neuron model according to the self-characteristic of the input image; subsequently updating the internal state value, dynamic threshold and output value of each neuron, outputting the sequentially iterative segmented images, calculating and memorizing the mutual information amount of the original image and the segmented images; and finally judging whether to iterate continuously or output the best segmented image according to the current iterative times. The method simplifies the model, improves the efficiency, completes the segmentation automation, solves the problems that the current model parameter needs to be adjusted manually by test according to different images and the best segmentation needs to be adopted manually, and has more obvious visual advantages simultaneously.

The invention belongs to the field of brain-like computing, particularly relates to a brain-like computing system based on multi-neural-network fusion and an execution method of an instruction set, and aims to solve the problem that an existing brain-like computing system cannot realize parallel fusion computing of a deep neural network and an impulsive neural network. The system is used for carrying out parallel operation on a deep neural network and a pulse neural network, and comprises a local tight coupling calculation cluster, a PCIE interface and an internal data bus, wherein the local tight coupling calculation clusters are electrically connected through an internal data bus, are used for calculating a deep neural network or a pulse neural network and consist of N * N neuron enginesNE, and each NE shares one neuron buffer area; the NE is used for carrying out matrix operation and vector operation on the neuron model data; and the PCIE interface is matched with a PCIE slot of acomputer mainboard and is used for data interaction between the brain-like computing system and external equipment. According to the invention, parallel operation of the deep neural network and the spiking neural network is realized.

A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t₁. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.

There are provided an apparatus and a method for compressing data, an apparatus and a method for analyzing data and a data management system, which are capable of compressing huge data and accurately reproducing the characteristics of the original data from the compressed data. The data compressing apparatus includes detection means for detecting a multiplicity of data sets, each including n parameter values that vary according to an operation of an object, where n is a natural number; and data compressing means for compressing the data sets by inputting the data sets into an n-dimensional space, arranging neurons smaller in number than the data sets in the n-dimensional space, carrying out unsupervised learning for a neural network on the neurons, and converting the data sets into a neuron model parameter characterizing a neuron model obtained by the unsupervised learning.

The invention discloses a precise synaptic adjustment method for multi-pulse neural network supervised learning. The invention combines LIF and SRM neuron models to propose a threshold dynamic self-adaptive precise synaptic adjustment rule. The main steps are as follows: using LIF neuron to simulate and calculate membrane voltage and synaptic current; using a W-H rule to calculate synaptic weightadjustment; calculating dynamic threshold of membrane voltage by fusing the memory of postsynaptic neurons and SRM neurons; implementing input-output multi-pulse mapping. The invention realizes precise adjustment of synaptic weights by combining two neuron models, and effectively releases the problem that the weights derived from the W-H rule are difficult to guarantee the optimal solution and thelearning convergence rate is difficult to control, which effectively improves the learning efficiency of SNN.

Apparatus and methods for processing inputs by one or more neurons of a network. The neuron(s) may generate spikes based on receipt of multiple inputs. Latency of spike generation may be determined based on an input magnitude. Inputs may be scaled using for example a non-linear concave transform. Scaling may increase neuron sensitivity to lower magnitude inputs, thereby improving latency encoding of small amplitude inputs. The transformation function may be configured compatible with existing non-scaling neuron processes and used as a plug-in to existing neuron models. Use of input scaling may allow for an improved network operation and reduce task simulation time.

The invention discloses a feedback type pulse neural network model training method for image data classification. The method comprises the following steps: constructing a feedback type pulse neural network model, and training the model through implicit differential in an equilibrium state, the model comprising two spiking neuron models based on an integration activation model IF and a leakage integration activation model LIF, and a feedback type spiking neural network model of a single-hidden-layer neural network structure and a feedback type spiking neural network model of a multi-hidden-layer neural network structure; using re-parameterization method to restrain the spectral norm of the feedback connection weight, and using an improved method to carry out batch normalization. According to the invention, the common problem of difficulty in training of a spiking neural network model can be avoided, the method is used for high-performance and efficient classification processing of computer image data and neuromorphic image visual data in an energy-saving manner, and higher classification accuracy can be obtained with fewer neurons, smaller parameters and shorter time steps.

The invention relates to a method for modeling and optimizing nerve net based on structure. Depending on the structure of system and constituent features, the complex non-linear system is decomposed to several relative simpler subsystems. The models of the sub system are built by using single artificial funciton chain neural element. The input/output is determined based on structural parameters, stimulus and response as well as historic signals. Jointing inherent action relation between each subsystem forms a model of neural net based on structure. Using said model optimizes the structural parameters. The invention provides modeling and optimizing dual functions. The advantages are structurization of model, determinate number of neural elements and fast speed of convergence.

Non-familial late-onset Alzheimer's disease (LOAD), a condition associated with the accumulation of the amyloid precursor protein-derived (APP) Abeta fragment in the brain, can be the consequence of combined genetic and environmental risk factors. One of these risk factors is the presence of the apolipoprotein E4 (APOE4) allele. This invention provides for a neuron model that can be used to screen and identify compounds that can prevent the APOE4-induced pre-LOAD state. This invention provides for methods for the treatment and/or prevention of a neurodegenerative disorder by using an inhibitor of APOE4, such as an antibody inhibitor, or by using an excess of APOE3 protein.

The embodiment of the invention discloses an FPGA implementation method based on a piecewise linear spiking neural network, and the method comprises the steps of constructing a neuron circuit according to a two-dimensional piecewise linear spiking neural model, so as to carry out the integration and output of input information through the neuron circuit, wherein the two-dimensional piecewise linear spiking neuron model comprises an expression of a membrane potential of a neuron and an expression of a recovery variable; and according to the neuron circuit, performing expansion according to a random coupling structure, and configuring a communication circuit of a pulse neural network generated by a pulse coding and decoding unit. According to the invention, less hardware resources are occupied, rich neuromorphic dynamics can be simulated and presented, meanwhile, higher hardware computing efficiency can be achieved, and the method is convenient to extend to hardware architecture implementation of a large-scale spiking neural network and dynamic simulation of a communication system.

An intelligent electrocardiogram data classification method based on voting ensemble learning in the invention is characterized by being realized through the following steps: a) carrying out data preprocessing; b) establishing a logistic regression model; c) establishing a decision tree model; d) establishing a support vector machine; e) establishing a naive Bayesian model; f) establishing a neuron model; g) establishing a k proximity model; and h) carrying out model integration. Finally, a model with the accuracy of not less than 80% is obtained, and the effect of the model is better than theeffect of the single model established in the steps b) to g). According to the intelligent electrocardiogram data classification method, enough data are firstly acquired from ccdd and are divided into a training set and a test set, then various models are established, and the model with accuracy of not less than 80% is finally obtained, thereby realizing intelligent identification and classification of normal, atrial fibrillation, atrial premature beat, accidental atrial premature beat, frequent atrial premature beat, atrial tachycardia and atrial fibrillation accompanied with rapid ventricular rate, and realizing early discovery and early treatment of cardiovascular diseases.

Apparatus and methods for processing inputs by one or more neurons of a network. The neuron(s) may generate spikes based on receipt of multiple inputs. Latency of spike generation may be determined based on an input magnitude. Inputs may be scaled using for example a non-linear concave transform. Scaling may increase neuron sensitivity to lower magnitude inputs, thereby improving latency encoding of small amplitude inputs. The transformation function may be configured compatible with existing non-scaling neuron processes and used as a plug-in to existing neuron models. Use of input scaling may allow for an improved network operation and reduce task simulation time.