FPGA implementation method based on piecewise linear spiking neural network

A technology of spiking neural network and neuron network, applied in the field of neural network, can solve the problem of loss of neuromorphic dynamic characteristics, and achieve the effect of enriching neural dynamic characteristics, facilitating dynamic simulation, and low hardware resources

Pending Publication Date: 2020-12-18
NORTHWEST NORMAL UNIVERSITY
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Problems solved by technology

[0007] The purpose of the embodiments of the present invention is to provide an FPGA implementation method based on a piecewise linear spiking neuron network to solve the problem that certain neuromorphic dynamics characteristics are lost during the hardware implementation of the existing spiking neuron model

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  • FPGA implementation method based on piecewise linear spiking neural network
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  • FPGA implementation method based on piecewise linear spiking neural network

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[0031] The implementation of the present invention will be illustrated by specific specific examples below, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0032] In the following description, for purposes of illustration rather than limitation, specific details, such as specific system architectures, interfaces, and techniques, are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0033] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descripti...

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Abstract

The embodiment of the invention discloses an FPGA implementation method based on a piecewise linear spiking neural network, and the method comprises the steps of constructing a neuron circuit according to a two-dimensional piecewise linear spiking neural model, so as to carry out the integration and output of input information through the neuron circuit, wherein the two-dimensional piecewise linear spiking neuron model comprises an expression of a membrane potential of a neuron and an expression of a recovery variable; and according to the neuron circuit, performing expansion according to a random coupling structure, and configuring a communication circuit of a pulse neural network generated by a pulse coding and decoding unit. According to the invention, less hardware resources are occupied, rich neuromorphic dynamics can be simulated and presented, meanwhile, higher hardware computing efficiency can be achieved, and the method is convenient to extend to hardware architecture implementation of a large-scale spiking neural network and dynamic simulation of a communication system.

Description

technical field [0001] The embodiment of the present invention relates to the technical field of neural networks, and in particular to an FPGA implementation method based on a segmented linear impulse neuron network. Background technique [0002] In order to simulate the mechanism of biological information encoding and explore the dynamic process of biological information processing, and then imitate the real process of brain information processing, researchers proposed Artificial Neural Network (ANN). Artificial neural network is a mathematical model inspired by the organization and function of biological neurons, which can automatically approximate any functional form that can best characterize the data, and is widely used to solve many prediction and decision modeling problems. As the third generation of artificial neural network, Spiking Neural Network (SNN) has attracted extensive attention of researchers because of its unique information processing mechanism and high-p...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04G06N3/063G06F15/78
CPCG06N3/049G06N3/063G06F15/7807G06N3/045
Inventor 蔺想红鲁晗皮晓妹石国勇
Owner NORTHWEST NORMAL UNIVERSITY
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