57 results about "Fifo memory" patented technology

The invention discloses a low-power FIFO (First In First Out) module, which comprises an FIFO memory and an FIFO controller, the FIFO memory comprises a writing unit, a memory unit and a multiplexer, the FIFO controller comprises a writing pointer register, a reading pointer register, a first adder and a second adder, the FIFO controller further comprises a mux selection register and a third adder, the third adder enables a mux selection pointer signal output by the mux selection register to increase by 1 only when valid data is cached in the storage unit or new valid data is to be cached while the storage unit outputs the last valid data; and when the read signal is high, the multiplexer selects the data on the corresponding address from the storage unit according to the mux selection pointer signal and outputs the data. According to the invention, the problem of invalid flipping caused by invalid data output is solved, so that the power consumption is reduced.

The invention relates to the technical field of quantum computers, in particular to an anti-quantum cryptographic signature algorithm execution optimization method and communication device.According to the method, a first FIFO storage for storing a first random coefficient and a second random coefficient is arranged on computing hardware, and the first random coefficient and the second random coefficient are stored in a cache mode; the times of writing the secret polynomial into the storage unit and reading the secret polynomial from the storage unit are reduced; the second FIFO memory for caching polynomial coefficients on a finite field is set to balance data processing time, the third FIFO memory is set to carry out bit width conversion of a secret key, meanwhile, the storage module for storing a common polynomial is set, and the data execution speed is balanced through combination of the first FIFO memory and the third FIFO memory. Through the data storage setting, the data access and storage times are reduced, the extra power consumption caused by memory access is reduced, the problem of high delay among the modules is reduced, and the overall execution time required by calculation is shortened.

The invention discloses a read transaction management method oriented to an AXI protocol network-on-chip, and relates to the technical field of chips, and the method comprises the steps: temporarily storing the unpacking attribute information of each group of unpacking content after the read transaction request is unpacked when the read transaction request issued by a main device is obtained; and writing pointers written into the transaction sorting FIFO memory are used as unpacking IDs to realize number rearrangement and then are sequentially issued, then returned unpacking responses are temporarily stored in the response data memory, and the unpacking responses can be sequentially read out from the response data memory and returned to the main equipment in an order-preserving manner by combining the unpacking IDs and utilizing the read pointers of the transaction sorting FIFO memory. According to the method, continuous issuing of the read transaction request is realized on the basis of ensuring the return sequence of the response data, so that the system performance is improved.

Provide is a FIFO memory system. The FIFO memory system includes: a FIFO memory; a read clock frequency circuit, configured to provide at least two clock signals, wherein the at least two clock signals include a first clock signal and a second clock signal, a frequency of the first clock signal being greater than a frequency of the second clock signal; and a controller, configured to determine a data volume in the FIFO memory, control the read clock frequency circuit to output the first clock signal in a case that the data volume in the FIFO memory is in a first range, or control the read clock frequency circuit to output the second clock signal in a case that the data volume in the FIFO memory is in a second range, the lower limit of the first range being not less than an upper limit of the second range.

Various embodiments include techniques for generating coding unit tree statistical data for video blocks included in a media frame. The disclosed video encoder includes a first-in-first-out (FIFO) memory for storing encoding data for multiple video blocks. A first set of units within the video encoder generates encoding data for each video block. After storing the encoding data in FIFO memory, the first set of units can proceed with encoding additional blocks of the media frame without having to wait for a second set of units within the video encoder to retrieve and process the encoding data. Subsequently, the second set of units can efficiently retrieve and process data for multiple blocks of the media frame at a time. Further, the video encoder can generate both forward looking prediction data and backward looking prediction data to encode a current block of the media frame, resulting in improved video quality.

The application discloses an FFT processor which is used to solve the problem of slow operation speed and large storage resource occupation in the prior art FFT circuit implementation scheme, and comprises a data processing pipeline formed by a plurality of first FFT processing units and a second FFT processing unit connected together; each first FFT processing unit comprises a base-2 butterfly operation unit generated by a base-2 frequency extraction FFT algorithm, a FIFO memory, a CORDIC processor and an angle generator; wherein the angle generator is used to determine the corresponding angle value of each first FFT processing unit at each clock, and the CORDIC processor is used to determine the rotation angle according to the angle value output by the angle generator; and the second FFT processing unit is a base-3 butterfly operation unit and is formed by multiplexing a preset number of first FFT processing units.

This disclosure provides an interface protocol converter and an electronic device, relating to the field of digital integrated circuits. The interface protocol converter includes: a read conversion module configured to convert the interface protocol of the read channel of an Advanced Scalable Interface (ASPI) into the interface protocol of a Static Random Access Memory (SRAM); the read conversion module includes: a read address FIFO memory; a read request expansion unit; a read identity FIFO memory; and a read data control FIFO memory; and a write conversion module configured to convert the interface protocol of the write channel of an ASPI into the interface protocol of a SRAM. By optimizing the data path structure, deep optimization of the SRAM interface characteristics is achieved, which can significantly reduce conversion latency and hardware resource consumption, while achieving higher bandwidth utilization and energy efficiency.

The application provides a chain communication method, a chain communication system and a computer readable storage medium, and belongs to the technical field of communication. The chain communication method comprises the following steps: receiving a preamble field of a target data frame and forwarding, determining a first baud rate based on a preamble edge interval; receiving valid data bits and writing into a FIFO memory; when the FIFO memory is empty and no valid data bits have been sent, sending preset empty bits; when the FIFO memory is not empty, reading the FIFO memory and sending the valid data bits based on the first baud rate; in the sending process, determining a deviation indication quantity according to the writing rate and the reading rate of the valid data bits in the FIFO memory, and compensating the first baud rate based on the deviation indication quantity to obtain a target baud rate for subsequent valid data sending. The application can realize adaptive adjustment of the sending rate in the chain cascade forwarding process, and improve the data transmission stability and reliability of the chain communication.

Computing device (100) comprising a main memory (104) configured to store a sparse matrix in a dense vector format (106, 108, 110) and to store a second vector (112) or a second matrix, a computing unit (102) configured to multiply the sparse matrix by the second vector or by the second matrix, and a streamer (114) comprising: an indexed loading block (116) comprising a secondary memory (118) and a FIFO memory (120) for requests to send values stored in the secondary memory to the computing unit; an indexed loading engine (122) configured to sequentially generate and store requests in the FIFO request memory according to an order in which the values are intended to be sent to the computing unit; the request storage order being calculated and stored in the form of firmware (124).

The present application provides an asynchronous FIFO memory, which comprises a synchronous FIFO memory and an asynchronous buffer. Data is written into the synchronous FIFO memory if there is a write request, the synchronous FIFO memory has a FIFO mode and a continuous mode, in the FIFO mode, the oldest written data is not allowed to be overwritten by the written data, in the continuous mode, the oldest written data is allowed to be overwritten by the written data. Data is read from the asynchronous buffer if there is a read request, the asynchronous buffer buffers the data read from the synchronous FIFO memory, the asynchronous buffer is not allowed to be written into when it is full, and the capacity of the asynchronous buffer is less than that of the synchronous FIFO memory. In this way, the area of the memory is saved, and the utilization of the memory is improved.

An image receiving device includes a first-in-first-out (FIFO) memory, a processor circuit and a FIFO multiplexer circuit. The FIFO memory includes a plurality of FIFO buffers. The processor circuit sets a plurality of first pipeline parameters according to device information of a plurality of image sensors and data capacities of the FIFO buffers. The FIFO multiplexer circuit configures correspondence between the image sensors and the FIFO buffers according to the first pipeline parameters, such that each of the image sensors transmits image data to a corresponding one of the FIFO buffers.

This disclosure presents a novel smart complementary metal oxide semiconductor (CMOS) sensor that can detect the “bright” pixels and export the light intensity and location of the selected pixels only. The detecting function is achieved by applying a thresholding criteria method. A novel CMOS architecture is proposed. The FPA-implemented COMS is shared by two sets of column processing circuitry for selecting, processing and exporting the data from top half and bottom half of FPA respectively. The CMOS architecture comprises a re-routing scheme, multiple I / Os deployment, parallel-shifting FIFO memory buffers, and interleaved timing scheme.

The invention discloses a design and an application method of an excitation synaptic backfield potential (fEPSPs) analog acquisition front-end system based on an FPGA (Field Programmable Gate Array). The system consists of a chopping stable cascode primary amplifier, a gain adjustable secondary amplifier, an AD9226 analog-to-digital conversion circuit, a serial port communication module and necessary peripheral circuits. Wherein the signal conditioning part adopts a two-stage amplification structure; in a signal transmission process, an FIFO (First In First Out) memory is used as a data cache region, a digital FIR (Finite Impulse Response) filter and a zero-phase filtfilt algorithm are fused, and the power consumption and the area are lower while signal two-stage amplification and high-fidelity filtering are performed. The system is based on FPGA control, and the electrophysiological recording analog front end can collect evoked field potential signals.

The application relates to the technical field of quantum computers, in particular to an anti-quantum password signature algorithm execution optimization method and a communication device. A first FIFO memory for storing a first random coefficient and a second random coefficient is arranged on a computing hardware, the number of times of writing and reading a secret polynomial into and from a storage unit is reduced through a cache mode; a second FIFO memory for storing polynomial coefficients on a cache finite field is arranged to balance data processing time, a third FIFO memory is arranged to perform bit width conversion of a key, and a storage module for storing a public polynomial is arranged, so that the data execution speed is balanced in combination. Through the above data storage arrangement, the number of data access and storage times is reduced, extra power consumption caused by memory access is reduced, high delay problems among modules are reduced, and the overall execution time required for calculation is reduced.

The application discloses a read transaction management method for an AXI protocol on-chip network, and relates to the chip technical field.The method temporarily stores the unpacking attribute information of each group of unpacking contents after the read transaction request is unpacked when the read transaction request issued by a host device is acquired, and sequentially issues the rearranged number by taking the write pointer of the write transaction sorting FIFO memory as the unpacking ID, then temporarily stores the returned unpacking response in a response data memory, and reads out the unpacking response from the response data memory in sequence and returns the unpacking response to the host device in sequence by combining the unpacking ID and using the read pointer of the transaction sorting FIFO memory.The method realizes the continuous issuance of the read transaction request on the basis of guaranteeing the response data return sequence, thereby improving the system performance.

The invention relates to the technical field of integrated circuit design, in particular to an FIFO (First In First Out)-based identifier generation system, which provides identifier information for read instructions through an identifier FIFO memory, can realize order preservation of read results of multi-read instructions in a multi-read instruction concurrence scene, can reuse the identifier information, and is convenient to use. In this way, it is not needed to set a plurality of bits in each read instruction to serve as the identification information corresponding to the read instruction, the convenience of generation of the identification information of the read instruction is improved, and then the data reading efficiency is improved.

The embodiment of the invention relates to the technical field of PCIe switches, in particular to a PCIe switch which comprises a plurality of port modules, and each port module comprises a message input unit, an arbitration unit and a message output unit. And the message input unit of the local port module caches the TLP messages to the first FIFO memory, performs order-preserving control on all the TLP messages, and sends an arbitration request to the arbitration unit of the target port module if detecting that the TLP messages meet order-preserving conditions. And if the TLP message meets the arbitration condition, the arbitration unit sends the TLP message to the message output unit of the target port module. And the message output unit caches the TLP messages to the second FIFO memory, performs order-preserving control on all the TLP messages, and outputs the TLP messages if the TLP messages meet the arbitration condition. According to the embodiment of the invention, through the above structure and order-preserving control, the secure transmission of the TLP message between any ports is realized, and the order-preserving requirement of the message is ensured to accord with a PCIe (Peripheral Component Interconnect Express) protocol.

Various embodiments include an automobile network device that includes a descriptor sorting engine (DSE). The DSE may include a direct memory access (DMA) controller, a memory organized by channel clusters that each include a plurality of first-in first-out (FIFO) memories, a timer, and a time stamp (TS) sorting logic component. The DMA controller may be configured to pull timestamp-pointer pairs from packet descriptors stored in an unsorted descriptor ring memory, store the timestamp-pointer pairs in the FIFO memories, trigger the TS sorting logic component to reorder the timestamp-pointer pairs in the FIFO memories so that they are sorted in ascending order, use the sorted timestamp-pointer pairs in the FIFO memories to read the packet descriptors stored in an unsorted descriptor ring memory, and store the packet descriptors in a sorted descriptor ring memory.

The application provides a kind of periodic signal measurement method and system, comprising: step S1: the measured signal with period T1 is transmitted to PAM4 chip, and the synchronous clock is input to PLL1, and the period of synchronous clock is nT1;Step S2: based on the synchronous clock, PLL1 and PLL2 are set, so that PLL2 outputs high-precision sampling trigger clock;Step S3: the analog unit in PAM4 chip is preprocessed to the measured signal, then is transmitted to ADC, and ADC converts the preprocessed measured signal into digital signal according to sampling trigger clock and stores in FIFO memory space;Step S4: MCU transmits the sampling data in FIFO memory space to PC, and PC calculates the test index of the signal to be measured after digital processing;Step S5: PC reconstructs the sampling data to recover the signal to be measured;Step S6: the recovered signal to be measured and the calculated test index of the signal to be measured are displayed through display screen.

The invention discloses a data transmission system for an LVDS (Low Voltage Differential Signaling) interface. Comprising a sending end and a receiving end, the sending end comprises a first splicing module, a first FIFO memory, a mapping module and a first conversion module, and the first splicing module is used for receiving video data, splicing each row of pixel data and then writing the spliced video data into the first FIFO memory; the mapping module is used for reading the spliced video data, receiving packet data and the number of data lines sent from the outside, and then sequentially mapping the spliced video data and the packet data to the corresponding data lines according to the number of the data lines and a mapping principle; and the first conversion module is used for converting each group of data with the bit width of 1 byte mapped to the data line into serial bit stream data with the bit width of 1 bit, and then sending the serial bit stream data to a receiving end. According to the invention, the problem of Lane quantity stiffness in the XN mode is avoided, and the bandwidth utilization rate of the LVDS interface is improved to the maximum extent.

Various embodiments include an automotive network device that includes a descriptor ordering engine (DSE). The DSE may include: a direct memory access (DMA) controller; a memory organized by channel clusters, each channel cluster comprising a plurality of first-in first-out (FIFO) memories; a timer; and a timestamp (TS) ordering logic component. The DMA controller may be configured to: pull a timestamp-pointer from a packet descriptor stored in an unordered descriptor ring memory; the timestamp is stored in the FIFO memory in a one-to-one correspondence manner; triggering the TS sorting logic component to resort the timestamp-pointer pairs in the FIFO memory, so that the timestamp-pointer pairs are sorted in an ascending order; reading the packet descriptors stored in an unordered descriptor ring memory using the ordered timestamp-pointer in the FIFO memory; and storing the packet descriptors in an ordered descriptor ring memory.

The embodiment of the present application provides a data management method and system. The method comprises the following steps: receiving a first trigger signal and receiving sampling data according to a preset data input channel configuration parameter; storing the received sampling data into a first FIFO memory according to the data input channel configuration parameter, and writing the sampling data in the first FIFO memory into a DDR according to a preset rule; receiving a sampling end signal, reading the sampling data from the DDR and storing the sampling data into a second FIFO memory, and reading the sampling data from the second FIFO memory. The system is used for executing the above method. The method and system provided by the present application realize the high-speed transmission of large data volume buffering and bridging, so that the test system can be used for high-speed test of multi-channel digital IO volume.

The present invention discloses a low-power FIFO module, which includes a FIFO memory and a FIFO controller. The FIFO memory includes a write unit, a storage unit, and a multiplexer. The FIFO controller includes a write pointer register, a read pointer register, a first adder and a second adder. The FIFO controller further includes a mux selection register and a third adder. The third adder increments the mux selection pointer signal output by the mux selection register by 1 only when there is valid data cached in the storage unit or when a new valid data is about to be cached while the storage unit outputs the last valid data, so that the multiplexer selects and outputs the data at the corresponding address from the storage unit according to the mux selection pointer signal when the read signal is high. The present invention solves the problem of invalid flips caused by outputting invalid data, thereby reducing power consumption.

The invention relates to a data storage device and method and electronic equipment, the device comprises a controller, a first FIFO module and a second FIFO module, the controller is used for determining a first data volume stored by the first FIFO module and a second data volume stored by the second FIFO module; according to the first data volume and the second data volume, a received data block is selected to be written into the first FIFO module or the second FIFO module, and / or data migration between the first FIFO module and the second FIFO module is managed; and the second FIFO module is used for sequentially outputting the data blocks according to the write-in sequence. According to the embodiment of the invention, the advantages of the first FIFO module 2 and the second FIFO module 3 can be considered at the same time, so that the requirements of high performance, low power consumption and high resource utilization rate of the FIFO memory in the fields of high-speed data communication, real-time signal processing, high-performance calculation and the like are met.

The invention discloses an inter-chip set communication method and system for optimizing communication performance, and relates to the field of inter-chip set communication, and a set communication management device in a downstream chip of the system carries out ID number rearrangement on received original transactions by using a write pointer of a transaction sorting FIFO (First In First Out) memory; according to the method, the read finger of the transaction sorting FIFO memory is used for carrying out response rearrangement on the response information returned by the application data slices, so that the issuing time of the temporarily-stored identification bit slices is judged, the identification bit slice of each original transaction can be ensured to fall later than the previous application data slices, and the subsequent data slices cannot be blocked. Therefore, the upstream chip can continuously issue the transaction slices to reduce the software management consumption and cost caused by collecting the response information, the software management cost of the downstream chip is not greatly increased, and the mechanism is beneficial for the downstream chip to quickly lift and apply, so that the inter-chip set communication efficiency is optimized.

A memory device includes a memory cell array including a plurality of planes, a plurality of first FIFO memories respectively corresponding to the plurality of planes and configured to store at least some pieces of data stored in the plurality of planes, and a second FIFO memory configured to load at least some pieces of data stored in at least one of the plurality of first FIFO memories according to a plane order in which the data stored in the plurality of planes is output, wherein the memory device is configured to store the data stored in each of the plurality of planes in a corresponding first FIFO memory of the plurality of first FIFO memories, respectively, based on an initial command-address provided from a memory controller.

A method to control a process variable in a process using a control unit includes sequential determination of values of a reference variable to be supplied to the control unit based on values of a first measurand, and sequential determination of values of a regulating variable using values for the reference variable and sequentially determined values for the process variable. A current value for the reference variable is determined by sequentially saving values of the first measurand in a first FIFO memory having a number K of memory locations for saving one value respectively, and by using only the n oldest values saved in the first FIFO memory to determine the current value for the reference variable, with n being a number of values that is smaller than the number K of the values saved in the memory locations of the first FIFO memory and greater or equal 1.

Several embodiments include techniques for generating statistical data of a coding unit tree for video blocks contained in a media frame. The disclosed video encoder includes a first-in-first-out (FIFO) memory for storing coding data for multiple video blocks. A first set of units within the video encoder generates coding data for each video block. After storing the coding data in the FIFO memory, the first set of units can proceed with coding additional blocks of the media frame without having to wait for a second set of units within the video encoder to retrieve and process the coding data. Subsequently, the second set of units can efficiently retrieve and process data for multiple blocks of the media frame simultaneously.Furthermore, the video encoder can generate both forward-looking and backward-looking prediction data to encode a current block of the media frame, resulting in improved video quality.

The application discloses a data writing method based on SPI communication, an electronic terminal and a storage medium. The method comprises the following steps: receiving current preset byte data transmitted by a host through an SPI interface; judging whether the write enable of a FIFO memory is valid based on a data receiving flag corresponding to the current preset byte data and a non-empty flag of the FIFO memory; and if the write enable of the FIFO memory is valid, writing the current preset byte data into the FIFO memory. In the foregoing manner, the application can effectively reduce the loss of data that cannot be correctly written during transmission, thereby improving the reliability of the communication system.

The application relates to the computer technical field, and discloses a FIFO memory with random address access and a data processing method to solve the problem that data written in a FIFO memory cannot be modified in a current circuit, the FIFO memory comprising a random access memory, a plurality of fixed-size memory blocks, each memory block being used for storing an Ethernet frame, write control logic and read control logic, the write control logic and the read control logic being used for reading and writing the current memory block in a FIFO order through a first external interface signal, and being used for reading and rewriting data in a specified address of the current memory block through the first external interface signal and a second external interface signal, the second external interface signal comprising an intra-block write enable signal, an intra-block write address signal, an intra-block read enable signal, an intra-block read address signal, a block write end signal and a block read end signal. The FIFO memory with random address access can modify data in the FIFO memory in the current circuit.