30 results about "Fifo memory" patented technology

Various embodiments include techniques for generating coding unit tree statistical data for video blocks included in a media frame. The disclosed video encoder includes a first-in-first-out (FIFO) memory for storing encoding data for multiple video blocks. A first set of units within the video encoder generates encoding data for each video block. After storing the encoding data in FIFO memory, the first set of units can proceed with encoding additional blocks of the media frame without having to wait for a second set of units within the video encoder to retrieve and process the encoding data. Subsequently, the second set of units can efficiently retrieve and process data for multiple blocks of the media frame at a time. Further, the video encoder can generate both forward looking prediction data and backward looking prediction data to encode a current block of the media frame, resulting in improved video quality.

The application discloses an FFT processor which is used to solve the problem of slow operation speed and large storage resource occupation in the prior art FFT circuit implementation scheme, and comprises a data processing pipeline formed by a plurality of first FFT processing units and a second FFT processing unit connected together; each first FFT processing unit comprises a base-2 butterfly operation unit generated by a base-2 frequency extraction FFT algorithm, a FIFO memory, a CORDIC processor and an angle generator; wherein the angle generator is used to determine the corresponding angle value of each first FFT processing unit at each clock, and the CORDIC processor is used to determine the rotation angle according to the angle value output by the angle generator; and the second FFT processing unit is a base-3 butterfly operation unit and is formed by multiplexing a preset number of first FFT processing units.

This disclosure provides an interface protocol converter and an electronic device, relating to the field of digital integrated circuits. The interface protocol converter includes: a read conversion module configured to convert the interface protocol of the read channel of an Advanced Scalable Interface (ASPI) into the interface protocol of a Static Random Access Memory (SRAM); the read conversion module includes: a read address FIFO memory; a read request expansion unit; a read identity FIFO memory; and a read data control FIFO memory; and a write conversion module configured to convert the interface protocol of the write channel of an ASPI into the interface protocol of a SRAM. By optimizing the data path structure, deep optimization of the SRAM interface characteristics is achieved, which can significantly reduce conversion latency and hardware resource consumption, while achieving higher bandwidth utilization and energy efficiency.

The application provides a chain communication method, a chain communication system and a computer readable storage medium, and belongs to the technical field of communication. The chain communication method comprises the following steps: receiving a preamble field of a target data frame and forwarding, determining a first baud rate based on a preamble edge interval; receiving valid data bits and writing into a FIFO memory; when the FIFO memory is empty and no valid data bits have been sent, sending preset empty bits; when the FIFO memory is not empty, reading the FIFO memory and sending the valid data bits based on the first baud rate; in the sending process, determining a deviation indication quantity according to the writing rate and the reading rate of the valid data bits in the FIFO memory, and compensating the first baud rate based on the deviation indication quantity to obtain a target baud rate for subsequent valid data sending. The application can realize adaptive adjustment of the sending rate in the chain cascade forwarding process, and improve the data transmission stability and reliability of the chain communication.

Computing device (100) comprising a main memory (104) configured to store a sparse matrix in a dense vector format (106, 108, 110) and to store a second vector (112) or a second matrix, a computing unit (102) configured to multiply the sparse matrix by the second vector or by the second matrix, and a streamer (114) comprising: an indexed loading block (116) comprising a secondary memory (118) and a FIFO memory (120) for requests to send values stored in the secondary memory to the computing unit; an indexed loading engine (122) configured to sequentially generate and store requests in the FIFO request memory according to an order in which the values are intended to be sent to the computing unit; the request storage order being calculated and stored in the form of firmware (124).

An image receiving device includes a first-in-first-out (FIFO) memory, a processor circuit and a FIFO multiplexer circuit. The FIFO memory includes a plurality of FIFO buffers. The processor circuit sets a plurality of first pipeline parameters according to device information of a plurality of image sensors and data capacities of the FIFO buffers. The FIFO multiplexer circuit configures correspondence between the image sensors and the FIFO buffers according to the first pipeline parameters, such that each of the image sensors transmits image data to a corresponding one of the FIFO buffers.

This disclosure presents a novel smart complementary metal oxide semiconductor (CMOS) sensor that can detect the “bright” pixels and export the light intensity and location of the selected pixels only. The detecting function is achieved by applying a thresholding criteria method. A novel CMOS architecture is proposed. The FPA-implemented COMS is shared by two sets of column processing circuitry for selecting, processing and exporting the data from top half and bottom half of FPA respectively. The CMOS architecture comprises a re-routing scheme, multiple I / Os deployment, parallel-shifting FIFO memory buffers, and interleaved timing scheme.

The application discloses a read transaction management method for an AXI protocol on-chip network, and relates to the chip technical field.The method temporarily stores the unpacking attribute information of each group of unpacking contents after the read transaction request is unpacked when the read transaction request issued by a host device is acquired, and sequentially issues the rearranged number by taking the write pointer of the write transaction sorting FIFO memory as the unpacking ID, then temporarily stores the returned unpacking response in a response data memory, and reads out the unpacking response from the response data memory in sequence and returns the unpacking response to the host device in sequence by combining the unpacking ID and using the read pointer of the transaction sorting FIFO memory.The method realizes the continuous issuance of the read transaction request on the basis of guaranteeing the response data return sequence, thereby improving the system performance.

The invention relates to the technical field of integrated circuit design, in particular to an FIFO (First In First Out)-based identifier generation system, which provides identifier information for read instructions through an identifier FIFO memory, can realize order preservation of read results of multi-read instructions in a multi-read instruction concurrence scene, can reuse the identifier information, and is convenient to use. In this way, it is not needed to set a plurality of bits in each read instruction to serve as the identification information corresponding to the read instruction, the convenience of generation of the identification information of the read instruction is improved, and then the data reading efficiency is improved.

Various embodiments include an automobile network device that includes a descriptor sorting engine (DSE). The DSE may include a direct memory access (DMA) controller, a memory organized by channel clusters that each include a plurality of first-in first-out (FIFO) memories, a timer, and a time stamp (TS) sorting logic component. The DMA controller may be configured to pull timestamp-pointer pairs from packet descriptors stored in an unsorted descriptor ring memory, store the timestamp-pointer pairs in the FIFO memories, trigger the TS sorting logic component to reorder the timestamp-pointer pairs in the FIFO memories so that they are sorted in ascending order, use the sorted timestamp-pointer pairs in the FIFO memories to read the packet descriptors stored in an unsorted descriptor ring memory, and store the packet descriptors in a sorted descriptor ring memory.

The application provides a kind of periodic signal measurement method and system, comprising: step S1: the measured signal with period T1 is transmitted to PAM4 chip, and the synchronous clock is input to PLL1, and the period of synchronous clock is nT1;Step S2: based on the synchronous clock, PLL1 and PLL2 are set, so that PLL2 outputs high-precision sampling trigger clock;Step S3: the analog unit in PAM4 chip is preprocessed to the measured signal, then is transmitted to ADC, and ADC converts the preprocessed measured signal into digital signal according to sampling trigger clock and stores in FIFO memory space;Step S4: MCU transmits the sampling data in FIFO memory space to PC, and PC calculates the test index of the signal to be measured after digital processing;Step S5: PC reconstructs the sampling data to recover the signal to be measured;Step S6: the recovered signal to be measured and the calculated test index of the signal to be measured are displayed through display screen.

The embodiment of the present application provides a data management method and system. The method comprises the following steps: receiving a first trigger signal and receiving sampling data according to a preset data input channel configuration parameter; storing the received sampling data into a first FIFO memory according to the data input channel configuration parameter, and writing the sampling data in the first FIFO memory into a DDR according to a preset rule; receiving a sampling end signal, reading the sampling data from the DDR and storing the sampling data into a second FIFO memory, and reading the sampling data from the second FIFO memory. The system is used for executing the above method. The method and system provided by the present application realize the high-speed transmission of large data volume buffering and bridging, so that the test system can be used for high-speed test of multi-channel digital IO volume.

The invention relates to a data storage device and method and electronic equipment, the device comprises a controller, a first FIFO module and a second FIFO module, the controller is used for determining a first data volume stored by the first FIFO module and a second data volume stored by the second FIFO module; according to the first data volume and the second data volume, a received data block is selected to be written into the first FIFO module or the second FIFO module, and / or data migration between the first FIFO module and the second FIFO module is managed; and the second FIFO module is used for sequentially outputting the data blocks according to the write-in sequence. According to the embodiment of the invention, the advantages of the first FIFO module 2 and the second FIFO module 3 can be considered at the same time, so that the requirements of high performance, low power consumption and high resource utilization rate of the FIFO memory in the fields of high-speed data communication, real-time signal processing, high-performance calculation and the like are met.

A memory device includes a memory cell array including a plurality of planes, a plurality of first FIFO memories respectively corresponding to the plurality of planes and configured to store at least some pieces of data stored in the plurality of planes, and a second FIFO memory configured to load at least some pieces of data stored in at least one of the plurality of first FIFO memories according to a plane order in which the data stored in the plurality of planes is output, wherein the memory device is configured to store the data stored in each of the plurality of planes in a corresponding first FIFO memory of the plurality of first FIFO memories, respectively, based on an initial command-address provided from a memory controller.

Several embodiments include techniques for generating statistical data of a coding unit tree for video blocks contained in a media frame. The disclosed video encoder includes a first-in-first-out (FIFO) memory for storing coding data for multiple video blocks. A first set of units within the video encoder generates coding data for each video block. After storing the coding data in the FIFO memory, the first set of units can proceed with coding additional blocks of the media frame without having to wait for a second set of units within the video encoder to retrieve and process the coding data. Subsequently, the second set of units can efficiently retrieve and process data for multiple blocks of the media frame simultaneously.Furthermore, the video encoder can generate both forward-looking and backward-looking prediction data to encode a current block of the media frame, resulting in improved video quality.

The application discloses a data writing method based on SPI communication, an electronic terminal and a storage medium. The method comprises the following steps: receiving current preset byte data transmitted by a host through an SPI interface; judging whether the write enable of a FIFO memory is valid based on a data receiving flag corresponding to the current preset byte data and a non-empty flag of the FIFO memory; and if the write enable of the FIFO memory is valid, writing the current preset byte data into the FIFO memory. In the foregoing manner, the application can effectively reduce the loss of data that cannot be correctly written during transmission, thereby improving the reliability of the communication system.

The application relates to the computer technical field, and discloses a FIFO memory with random address access and a data processing method to solve the problem that data written in a FIFO memory cannot be modified in a current circuit, the FIFO memory comprising a random access memory, a plurality of fixed-size memory blocks, each memory block being used for storing an Ethernet frame, write control logic and read control logic, the write control logic and the read control logic being used for reading and writing the current memory block in a FIFO order through a first external interface signal, and being used for reading and rewriting data in a specified address of the current memory block through the first external interface signal and a second external interface signal, the second external interface signal comprising an intra-block write enable signal, an intra-block write address signal, an intra-block read enable signal, an intra-block read address signal, a block write end signal and a block read end signal. The FIFO memory with random address access can modify data in the FIFO memory in the current circuit.

This invention pertains to the field of power and discloses a method and apparatus for acquiring magnetic field signals at the IGBT turn-on and turn-off moments. The method includes: converting magnetic field sensing signals into digital sample values ​​and determining whether a sampling trigger moment has been reached based on the digital sample values; dividing multiple FIFO memories within an FPGA control module into a first memory group and a second memory group, and cyclically updating and storing the digital sample values ​​through the first memory group before the sampling trigger moment is reached; controlling the first memory group to stop data updates and latching all currently stored pre-trigger data when the sampling trigger moment is reached, and controlling the second memory group to continuously write digital sample values ​​after the sampling trigger moment; reading complete sample data from the first and second memory groups and sending the complete sample data to a photoelectric conversion module; receiving optical signals through a converter valve control board and reconstructing the magnetic field signal waveform at the IGBT turn-on and turn-off moments via integration calculation on a host computer.

A memory device includes a memory cell array including a plurality of planes, a plurality of FIFO memories respectively corresponding to the plurality of planes and configured to store at least some pieces of data stored in the plurality of planes, and a second FIFO memory configured to load at least some pieces of data stored in at least one of the plurality of first FIFO memories according to a plane order in which the data stored in the plurality of planes is output, wherein the memory device is configured to store the data stored in each of the plurality of planes in a corresponding first FIFO memory of the plurality of first FIFO memories, respectively, based on an initial command-address provided from a memory controller.

The utility model discloses a rail transit power supply cable high-low traveling wave measurement system, and relates to the field of traveling wave measurement. According to the utility model, the current transformer with two characteristics of high precision and strong saturation resistance is configured, the multi-way switch is combined to realize intelligent switching of measurement channels, the FIFO memory is utilized to carry out data buffer storage, and the parallel comparator is adopted to realize real-time threshold judgment. When the impact current is detected, the DSP controller rapidly switches the measurement channels and completes data splicing, thereby effectively solving the problem that a single sensor cannot give consideration to both precision and anti-saturation capability.

The embodiment of the application relates to the technical field of PCIe switchers, in particular to a PCIe switcher, which comprises a plurality of port modules, each of which comprises a message input unit, an arbitration unit and a message output unit. The message input unit of a local port module caches TLP messages to a first FIFO memory, performs ordered control on all TLP messages, and sends an arbitration request to the arbitration unit of a target port module if it is detected that the TLP messages meet the ordered control condition. If the TLP messages meet the arbitration condition, the arbitration unit sends the TLP messages to the message output unit of the target port module. The message output unit caches the TLP messages to a second FIFO memory, performs ordered control on all TLP messages, and outputs the TLP messages if the TLP messages meet the arbitration condition. Through the above structure and ordered control, the embodiment realizes safe transmission of TLP messages between any ports and guarantees that the ordered control requirement of the messages meets the PCIe protocol.

The application provides a screening module, device, equipment, storage medium, the screening module comprises: screening module configuration unit, reference object configuration unit, first in first out FIFO memory of screening object, screening object reading unit, reference object reading unit, interrupt analysis unit, a plurality of screening units; wherein, the screening module configuration unit is connected with the screening object reading unit and the reference object reading unit respectively; the reference object configuration unit is connected with the reference object reading unit; the interrupt analysis unit is connected with the screening object reading unit; the screening object reading unit is connected with the FIFO memory of screening object; the reference object reading unit and the FIFO memory of screening object are connected with each screening unit respectively. The screening module provided by the application can quickly and accurately complete the screening work.

The application provides a data link processing method, device, equipment, medium and product. The method comprises the following steps: acquiring a plurality of measurement data of a quantum measurement and control instrument; in response to a data write instruction, determining a data flow direction of each measurement data according to a preset data storage strategy; based on each data flow direction, selecting a target first-in-first-out (FIFO) memory for storing each measurement data from a plurality of FIFO memories and writing the measurement data into the target FIFO memory; in response to a data read instruction, reading the corresponding measurement data from each target FIFO memory; performing data construction on each measurement data to obtain a plurality of target data; and delivering the plurality of target data to an external device. The data link processing method provided by the application uses a plurality of FIFO memories to cache a large amount of measurement data, realizes instant data storage and reading operation, reduces the response time and delay time, further timely performs the data construction and data delivery process, and effectively improves the data processing speed.

The embodiment of the present application provides a data transmission circuit, method and device of a cross power domain asynchronous FIFO, and relates to the technical field of integrated circuits. The FIFO memory of the circuit is used for storing write data from a write clock domain; the read control logic module is used for generating a read pointer; the low-power unit group comprises W first low-power units and X second low-power units; and the read pointer is transmitted to a data selector; the data selector is connected to a data output end of the FIFO memory and an output end of the second low-power unit and is used for selecting write data to be transmitted corresponding to the read pointer from the FIFO memory; the first low-power unit is used for performing cross power domain signal processing on W bits of write data to be transmitted output by the data selector to obtain target write data; and a synchronizer is connected to the output end of the first low-power unit and is used for synchronizing the target write data to a read clock domain. The present application improves the operation performance of a chip.

The invention relates to a memory device, a memory controller, and a memory system including the same. A memory device includes: a memory cell array including a plurality of planes; a plurality of FIFO memories respectively corresponding to the plurality of planes and configured to store at least some pieces of data among the data stored in the plurality of planes; and a second FIFO memory configured to load at least some pieces of data among the data stored in at least one first FIFO memory among the plurality of first FIFO memories according to a plane order in which the data stored in the plurality of planes is output, wherein the memory device is configured to store data stored in each of the plurality of planes in a corresponding first FIFO memory of the plurality of first FIFO memories, respectively, based on an initial command address provided from the memory controller.

This invention provides a method and system for processing received data streams, comprising: receiving a first data stream transmitted via wired transmission and a second data stream transmitted via radio transmission from a radio transmitting device; using the first data stream as a transmission reference stream and the second data stream as a reception test stream; writing the transmission reference stream and the reception test stream into a DDR; retrieving the transmission reference stream from the DDR and storing it in a first FIFO memory; if the difference between the retrieval time and the writing time is greater than a preset delay value, comparing the first data packet and the second data packet to obtain a first comparison result; when the first comparison result is successful, continuously comparing the transmission reference stream and the reception test stream to obtain a second comparison result; determining whether the number of times a successful comparison turns into an unsuccessful comparison exceeds a preset threshold for the number of times a comparison fails or whether the time of unsuccessful comparison exceeds a preset time threshold; if yes, displaying an unlocked result; if no, displaying a locked result.

The invention discloses a data processing method and device for a front-end electronics module, and the method comprises the steps: collecting waveform data from a detector according to channels, merging the data of eight adjacent channels into one group, and storing the data into a first-stage FIFO memory; the collected data are compressed, compression processing is carried out in a segmented mode according to the characteristics of the pulse signals, and the compressed data of the adjacent 64 channels are loaded into a second-stage FIFO storage; the DDR is divided into 16 pieces of independent caches, and partition cache management is carried out; dynamically transferring data among different cache regions according to the storage conditions of the 16 cache regions of the DDR; transferring data among the plurality of front-end electronics modules through a GT port according to storage conditions among different front-end electronics modules; and uploading the data to a rear-end data acquisition system through the high-speed link. According to the method, through segmented compression, layered caching, intra-module equalization and inter-module equalization, the waveform data rate is reduced, and the transmission pressure is reduced.

This application discloses a method, apparatus, chip, and medium for reading and writing data in a FIFO memory, relating to the field of storage systems. The method includes interleaving data reading and writing from two single-port memories when no read / write conflict exists; and when a read / write conflict exists, a read-first approach is adopted, and then data is interleaved from the two single-port memories again in the next clock cycle, except that the written data is delayed by one clock cycle. Therefore, this method solves the problem of read / write conflict and realizes the function of FIFO data reading and writing; using two single-port memories enables simultaneous data reading and writing, thus realizing the function of simultaneous read / write of dual-port memories; and because the area of ​​single-port memories is small, chip area optimization can be achieved; furthermore, no clock multiplication is required, so the FIFO memory of this application can operate at higher frequencies.

The application discloses a data processing method and device for a front-end electronics module, which comprises the following steps: collecting waveform data from a detector according to channels, merging data of 8 adjacent channels into a group, and storing the group into a first-level FIFO memory; compressing the collected data, compressing the data according to the characteristics of pulse signals, and storing compressed data of 64 adjacent channels into a second-level FIFO memory; dividing a DDR into 16 independent caches, and performing partition cache management; dynamically transferring data between different cache regions according to the storage conditions of the 16 cache regions of the DDR; transferring data between multiple front-end electronics modules through a GT port according to the storage conditions of the multiple front-end electronics modules; and uploading data to a back-end data acquisition system through a high-speed link. The method reduces the waveform data rate and reduces the transmission pressure through segmented compression, layered caching, intra-module balancing and inter-module balancing.

The invention relates to a hardware architecture applied to RS (Reed-Solomon) encoding and decoding, which is established based on an ASIC (Application Specific Integrated Circuit) architecture and comprises a memory array and an FIFO (First In First Out) The prefetch RS encoder is used for reading write-in data from the memory array according to the size of an RS code word / code element, performing RS encoding and writing an RS encoding result into the memory array; the pre-fetching RS decoder is used for pre-fetching data of each address in the memory array for pre-decoding during the idle period of the memory array, and pre-storing an error position and an error pattern value decoded by each code word into the FIFO memory; and the error correction module is used for performing error correction on the data of each address in the memory array by adopting the error position and the error pattern value stored in the FIFO memory and outputting the data. According to the invention, hardware acceleration processing can be realized, and the characteristic of continuous writing and continuous reading of row data can be supported.