12 results about "Fft processor" patented technology

Disclosed herein are an FFT processor, an FFT computing method, a radar signal processing system-on-chip, an integrated circuit, and an electromagnetic wave sensor. The FFT processor comprises two cascaded FFT kernels, and the FFT processor has at least two operating modes among a large-point-number FFT mode, a pipeline mode and an independent parallel mode, wherein when the FFT processor is in the large-point-number FFT mode, the two FFT kernels are configured to decompose FFT of N points into two instances of FFT; when the FFT processor is in the pipeline mode, the former FFT kernel of the two cascaded FFT kernels is configured to perform distance FFT, and the latter FFT kernel of the two cascaded FFT kernels is configured to perform Doppler FFT; and when the FFT processor is in the independent parallel mode, the two FFT kernels are configured to independently process data of different channels in parallel.

The application discloses an FFT processor which is used to solve the problem of slow operation speed and large storage resource occupation in the prior art FFT circuit implementation scheme, and comprises a data processing pipeline formed by a plurality of first FFT processing units and a second FFT processing unit connected together; each first FFT processing unit comprises a base-2 butterfly operation unit generated by a base-2 frequency extraction FFT algorithm, a FIFO memory, a CORDIC processor and an angle generator; wherein the angle generator is used to determine the corresponding angle value of each first FFT processing unit at each clock, and the CORDIC processor is used to determine the rotation angle according to the angle value output by the angle generator; and the second FFT processing unit is a base-3 butterfly operation unit and is formed by multiplexing a preset number of first FFT processing units.

This invention relates to a reconfigurable hybrid-radix FFT processor based on the CORDIC algorithm, belonging to the field of reconfigurable FFT computing technology. It addresses the technical problems of traditional FFT processors, such as insufficient flexibility, high power consumption, low accuracy, and difficulty in adapting to diverse application scenarios. The technical solution includes a configuration information generation module, a multi-level multi-radix FFT computing module, and a two-radix FFT computing module. It employs a novel CORDIC algorithm that removes compensation factors, supporting hybrid-radix butterfly operations (radix 2, 3, 4, and 5), and dynamically reconfigures to adapt to different point count requirements. The technical advantages are reflected in ultra-high flexibility, low power consumption, high accuracy, and efficient utilization of hardware resources.

Digital Beam-Formed Data Packet Communication Across Serially-Connected Transceivers by receiving modulated RF signals at a plurality of signal ports of each transceiver IC in a subarray of serially connected transceiver ICs and generating one or more frequency domain digital data packets of subcarrier IQ data associated with each signal port by demodulating each modulated RF signal from each signal port using an FFT processor within the respective transceiver ICs, and forming a plurality of combined frequency domain digital data packets from the transceiver ICs using a set of serial data links between the transceiver ICs of the subarray of serially connected transceiver ICs; and transmitting the plurality of combined frequency domain digital data packets from the subarray of transceiver ICs to a beamformer processor.

One aspect of the present invention provides a signal processing apparatus including: filter processors, the number of the filter processors depending on the number of spatial modes of a received optical signal; a sum operator that outputs a sum of outputs of a plurality of the filter processors; an IFFT processor that performs inverse Fourier transform on the sum; an output signal selector that outputs a signal including only a predetermined part of an output of the IFFT processor; an error signal output that outputs, as an error signal, a difference between an output of the output signal selector and a desired signal; and an FFT processor that performs Fourier transform on signals including the error signal, in which the filter processors update a filter weight coefficient by using a signal obtained by performing multiplication only on a predetermined part for an output of the FFT processor and a signal obtained by performing processing including Fourier transform on the received optical signal, and the filter processors output a signal obtained by performing multiplication only on a predetermined part for the filter weight coefficient and the received optical signal.

A failure sign determining device includes an acquirer to acquire pieces of sensor data based on respective values measured by multiple sensors, an FFT processor to execute fast Fourier transform on each of the pieces of sensor data and thereby generate a piece of frequency spectrum data, and a determiner to determine the existence of a failure sign on the basis of comparison between the piece of frequency spectrum data and a spectrum range defined for the sensor. The determiner, only when determining that a failure sign exists, transmits at least either of the piece of frequency spectrum data and the piece of sensor data to an analysis apparatus.

The present invention discloses a high-speed array signal processing device based on optical transmission, belonging to the field of array signal processing technology. The present invention comprises an optical switching unit, first to sixth processing units, a synchronization control unit, and a backplane unit. The first to sixth processing units are implemented based on FPGAs, and the synchronization control unit is implemented based on an embedded processor. The first to fourth processing units each include a beamforming processor, a calibration filter, and a synthesis filter. The fifth processing unit includes a direction-finding processor and an FFT processor. The sixth processing unit includes a modulation processor and a DDC processor. The present invention utilizes an integrated design of optical transmission, switching, and high-speed processing, resulting in a wide processing bandwidth and enabling efficient real-time processing in complex environments.

The invention discloses a dynamic configurable pipeline FFT (Fast Fourier Transform) processor supporting multiple points and an implementation method thereof, and relates to the technical field of digital signal processing, the dynamic configurable pipeline FFT processor comprises a main control module, an FFT operation module and an output cache module which are connected in sequence; the main control module is used for receiving and analyzing external control information and determining the total number of operation stages of the FFT and cardinal number configuration corresponding to each stage of operation; the FFT operation module is used for dynamically constructing an operation pipeline according to the configuration information of the main control module and completing high-precision and high-throughput signal conversion; and the output cache module is used for caching the out-of-order result data after the FFT operation, performing rearrangement processing on the out-of-order result data and outputting a final operation result in a natural sequence. The pipeline structure and the operation cardinal number can be dynamically configured according to the input point number, the hardware resource utilization rate, the data processing flexibility and the system throughput rate are remarkably improved, and the method is suitable for various communication and image processing application scenes.

The invention relates to an FFT (Fast Fourier Transform) processor, an FFT calculation method, a radar signal processing system on chip, an integrated circuit and an electromagnetic wave sensor. The FFT processor comprises two cascaded FFT cores, and the FFT processor has at least two working modes of a large-point FFT mode, a pipeline mode and an independent parallel mode; when the FFT processor is in the large-point FFT mode, the two FFT cores are configured to be used for decomposing FFT of N points into FFT for two times; when the FFT processor is in the pipeline mode, in the two FFT cores, the FFT core cascaded in the front is configured to perform distance FFT, and the FFT core cascaded in the rear is configured to perform Doppler FFT; and when the FFT processor is in the independent parallel mode, the two FFT cores are configured to independently process data of different channels in parallel.

This invention belongs to the field of FFT computation acceleration technology, specifically relating to an adaptive FFT operation processor module for handling large amounts of data, including an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT computation module, and a control module; the FFT computation module includes m-row radix-2 arrays arranged side-by-side. k The MDC module includes a data rearrangement unit comprising a read / write data storage module and a data preprocessing module. The read / write data storage module consists of multiple memories. The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffling units of varying depths. The twiddle factor storage module stores fixed constant twiddle factors and reuses them based on the number of calculation points. The address generation module uses a program counter to generate address sequences for data read / write. The control module controls the execution of FFT calculations and can adapt to different FFT calculation requirements. This improves the utilization rate of the butterfly operation unit and the overall computational throughput of the architecture.

The invention provides a multi-substrate length-configurable fixed-floating-point FFT (Fast Fourier Transform) processor. The multi-substrate length-configurable fixed-floating-point FFT processor comprises a first RAM (Random Access Memory), a second RAM, a third RAM, a primary rearrangement unit, an FFT controller, a clock configuration unit, a fixed-floating-point multiplier / summator and a twiddle factor ROM (Read Only Memory) table, the first RAM is used for receiving external input serial data; the primary rearrangement unit is used for rearrangement; the clock configuration unit is used for outputting a plurality of multiple frequency clocks to the FFT controller; the FFT controller is used for controlling the data to be arranged, read and written; the fixed-point and floating-point multiplier / adder is used for carrying out fixed-point or floating-point FFT operation; the twiddle factor ROM table is used for pre-storing a plurality of twiddle factors required for calculating FFT (Fast Fourier Transform); and the third RAM and the second RAM are used for temporarily storing data in the base 2, base 4 or base 8 butterfly operation. The processor is simple in structure, adapts to processing in different length ranges and various application scenes, and is high in processing efficiency.

The application discloses a CSD coding multiplier optimization structure for an FFT processor and belongs to the technical field of coding multiplier optimization, in particular to a CSD coding multiplier optimization structure for an FFT processor.The application provides a CSD coding multiplier optimization structure for an FFT processor.The application comprises a first control logic line and a second control logic line, characterized in that the first control logic line controls selection of multiplication by 1 or multiplication calculation of input data, and the second control logic line controls selection of multiplication by 1 or multiplication by '-j'; the control logic is solved by using a Karnaugh map; and the CSD coding multiplier is controlled by the first control logic line and the second control logic line, so that complex multiplication operation is completed at a correct clock.