Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Low memory spending hybrid base FFT processor and its method

A technology with low memory and memory, applied in the field of wireless communication and digital signal processing, can solve the problems of inability to handle 32-point, 128-point, 512-point, 2048-point FFT, many operation stages, and unfavorable low-power design.

Inactive Publication Date: 2007-12-05
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
View PDF0 Cites 25 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the radix-2FFT algorithm is directly used, the number of calculation stages is large. In order to ensure the throughput of data processing, it is necessary to use frequency multiplication for the functional modules, which is not conducive to low power consumption design.
For fixed-base FFT algorithms such as base-4, only 4 points such as 16 points, 64 points, and 256 points can be processed. n (n=1, 2, 3,...) point FFT, cannot handle 32 points, 128 points, 512 points, 2048 points, 8192 points FFT, and the FFT of these points is currently in OFDM, digital signal processing At the same time, in order to ensure the flexibility of the number of points processed by FFT, it is of great significance to use mixed basis FFT

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Low memory spending hybrid base FFT processor and its method
  • Low memory spending hybrid base FFT processor and its method
  • Low memory spending hybrid base FFT processor and its method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] Here, the radix-4 / 2 mixed radix 32-point FFT data flow diagram is used to illustrate the specific implementation, and the algorithm derivation and hardware mapping here are also suitable for other mixed radix high-point FFT algorithms. The corresponding hardware architecture adopts two blocks of RAM, which are I / O memory and operation memory. Output sequence 1 and input sequence 2 share the same I / O memory, and each input sequence is defined as a frame. Without loss of generality, input sequence 1 represents odd frames and input sequence 2 represents even frames. I / O memory and operation memory are rotated by frame, and FFT operation is carried out continuously. The order of frequency domain points of output sequence 1 and output sequence 2 are generated by the original Input Order register, and both are exactly the same. Original Input Order1, Input Order1, Input Order 2, and Reversed Input Order2 are cumulative counting registers with a bit length of n bits, where n ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Being related to area of wireless communication technique, especially the invention is related to general operand conflict free created mixed base FFT processor with low spending memory. The FFT processor is composed of control logic unit, operation RAM, network, butterfly operation unit, complex multiplication unit of twiddle factor (CMUTF), twiddle factor ROM, and I / O shared RAM. The control logic unit controls the operation RAM, the butterfly operation unit, twiddle factor ROM, and I / O shared RAM. Through network, the operation RAM is connected to the butterfly operation unit, and CMUTF. CMUTF is connected to the twiddle factor ROM.

Description

technical field [0001] The invention relates to the technical fields of wireless communication and digital signal processing, in particular to a general-purpose mixed-base FFT processor and method thereof with low memory overhead generated without conflict of operands. Background technique [0002] In OFDM (Orthogonal Frequency Division Multiplexing) carrier modulation and demodulation and digital signal processing applications, mixed-radix FFT (Fast Fourier Transformation) plays an important role. If the radix-2FFT algorithm is directly used, more operation stages are required. In order to ensure the throughput rate of data processing, it is necessary to use frequency multiplication for the functional modules, which is not conducive to low power consumption design. For fixed-base FFT algorithms such as base-4, only 4 points such as 16 points, 64 points, and 256 points can be processed. n (n=1, 2, 3,...) point FFT, cannot handle 32 points, 128 points, 512 points, 2048 point...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H04L27/26G06F17/14
Inventor 王江黑勇仇玉林
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com