74 results about "Twiddle factor" patented technology

The invention discloses a lattice-based cryptographic algorithm-oriented side channel attack-resistant NTT circuit, which comprises a control unit, which is mainly used for controlling the enabling of a bottom layer component in the structure and the data flow direction among modules; the storage unit is used for storing the coefficient, the random twiddle factor address and the twiddle factor; the address generation unit is used for calculating and generating a storage RAM (Random Access Memory) address of a twiddle factor participating in operation and a read address required by the coefficient storage unit; and the coefficient transposing unit is used for realizing coefficient reading meeting the index distance among all NTT stages. According to the side channel attack resisting NTT circuit oriented to the lattice-based cryptographic algorithm, when a low delay base-4CT / GS butterfly unit is masked, the increment of modular multiplication resources is reduced, and the resource consumption is remarkably reduced while high security is kept.

The invention provides a high-speed NTT method and system based on GPU matrix-thread collaborative optimization. The method comprises the steps that an input twiddle factor is converted into a matrix form; transmitting the updated twiddle factor matrix and the input array to a graphics processor; according to the input array and the size of the twiddle factor matrix, the number of blocks in the grid and the number of threads included in each block are set, so that each block is responsible for the operation of multiplying one row by one column, and each thread in the block completes the operation of multiplying one pair of data in the corresponding row-by-column process to obtain a group of intermediate results; and obtaining output data corresponding to the block according to an intermediate result in the block, and sending the output data to a corresponding position of an output matrix to serve as a multiplication result. According to the method, NTT calculation is reconstructed into parallel matrix-vector operation, the maximum utilization of GPU calculation resources is realized through the combination of an efficient thread allocation strategy and an optimized memory access mode, and the calculation efficiency is remarkably improved.

The invention discloses a lattice cryptographic modular multiplication method and a modular multiplier based on an improved plantard algorithm, which eliminate the post-processing overhead of the traditional modular multiplication method by preprocessing twiddle factors in the level of the modular multiplication method. In hardware implementation, shift-addition is adopted to replace a complex multiplier, a dynamic bit width truncation technology is combined, the bit width of intermediate data is compressed from 39 bits to 21 bits, and logic resource consumption is greatly reduced, so that modular multiplication operation in a lattice password digital signature scheme can be quickly and efficiently completed.

Embodiments of the present application provide a system, a device, and a method for a two-variable number theoretic transform. A matrix having the two-variable number theoretic transform may be applied to a matrix having dimensions a×b, where a=2x and b=2y for x≥y. The two-variable number theoretic transform includes two stages: decomposition by rows and row-wise fast Fourier transforms (FFTs), with twiddle factors computed based on a first root α satisfying αb=−1 mod p; and decomposition by columns and column-wise FFTs, with twiddle factors computed based on a second root β satisfying β2a=2 or −2 mod p. Since each of the stages uses a different root, the number of twiddle factors is reduced.

Generally discussed herein are devices, systems, and methods for performing a number theoretic transform (NTT) / inverse NTT (INTT). A circuit for NTT / INTT can include a first butterfly operator circuit (BOC) that generates first and second output coefficients based on first and second polynomial coefficients and a twiddle factor, a second BOC that operates in parallel with the first BOC and generates third and fourth output coefficients based on third and fourth polynomial coefficients and the twiddle factor, a third BOC that operates in series with the first and second BOCs and generates fifth and sixth output coefficients based on the first and third output coefficients and a second twiddle factor, and a fourth BOC that operates in series with the first and second BOCs and in parallel with the third BOC and generates seventh and eighth output coefficients based on the second and fourth output coefficients and a third twiddle factor.

The invention belongs to the technical field of FFT (Fast Fourier Transform) calculation acceleration, and particularly relates to a self-adaptive FFT operation processor module for processing large data volume, which comprises an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT calculation module and a control module, the FFT calculation module comprises m rows of radix-2kMDC modules which are arranged side by side; the data rearrangement unit comprises a read-write data storage module and a data preprocessing module; the read-write data storage module consists of a plurality of memories; the data preprocessing module is composed of a plurality of parallel branch switching circuits and a plurality of shuffling units with different depths; the twiddle factor storage module is used for storing fixed constant twiddle factors and realizing repeated utilization of the constant twiddle factors according to the calculated points; the address generation module is used for generating an address sequence for data reading / writing by using a program counter, the control module is used for controlling and executing FFT calculation, and different FFT calculation requirements can be met. And the utilization rate of the butterfly operation unit and the calculation throughput rate of the whole architecture are improved.

Fourier transform operations may be converted to matrix multiplications that may be like matrix multiplications in convolutions and can be executed by deep neural network (DNN) accelerators. A DNN accelerator may receive an input tensor representing an input signal of a Fourier transform operation. The input tensor may include activations arranged in one or more rows and one or more columns. The DNN accelerator may receive a weight tensor determined based on one or more twiddle factors of the Fourier transform operation. The DNN accelerator may perform two sequences of multiply-accumulate (MAC) operations. An MAC operation in the first sequence may be performed on the weight tensor and a row in the input tensor. An MAC operation in the second sequence may be performed on the weight tensor and a column in the input tensor. The outputs of the MAC operations may represent the Fourier transform of the input signal.

The embodiments of the present application belong to the technical field of computers. Disclosed are a method and apparatus for executing FFT computation, and a computing device. The method comprises: on the basis of the length of a data sequence to be subjected to FFT computation, dividing the FFT computation into a plurality of computation stages; for at least one target computation stage among the plurality of computation stages, on the basis of radixes respectively corresponding to the plurality of computation stages, and the execution order of the target computation stages among the plurality of computation stages, determining a merged matrix corresponding to the target computation stage, wherein the merged matrix is a product of a discrete Fourier transform (DFT) coefficient matrix and a twiddle factor in the target computation stage; and when executing the target computation stage, determining the product of an input sequence of the target computation stage and the merged matrix, and determining the product to be an output sequence of the target computation stage. By means of the present application, a computation amount corresponding to a computation stage can be reduced, thereby improving the execution efficiency of FFT computation.

Generally discussed herein are devices, systems, and methods for performing a number theoretic transform (NTT) / inverse NTT (INTT). A circuit for NTT / INTT can include a first butterfly operator circuit (BOC) that generates first and second output coefficients based on first and second polynomial coefficients and a twiddle factor, a second BOC that operates in parallel with the first BOC and generates third and fourth output coefficients based on third and fourth polynomial coefficients and the twiddle factor, a third BOC that operates in series with the first and second BOCs and generates fifth and sixth output coefficients based on the first and third output coefficients and a second twiddle factor, and a fourth BOC that operates in series with the first and second BOCs and in parallel with the third BOC and generates seventh and eighth output coefficients based on the second and fourth output coefficients and a third twiddle factor.

The invention discloses a hardware acceleration method for a Fourier neural operator. The hardware acceleration method comprises the following steps: setting an FFT module and a DFT / NN module which are independent from each other on an FNO hardware accelerator; performing fast Fourier transform (FFT) calculation on the batch input data by using an FFT module; a DFT / NN module is utilized to execute discrete Fourier transform (DFT) calculation based on a Bluestein algorithm, and access mode parallel random access of twiddle factors is reconstructed into parallel rule access; in an FNO hardware accelerator, an FFT module or a DFT / NN module is adaptively selected as a unit for executing calculation based on static parameter analysis of input dimensions, transformation points and frequency cut-off output points, and corresponding operator fusion is executed based on a predefined operator fusion mode. The adaptive capacity of the FNO to different transformation points and dimension structures is enhanced, and effective unification of computing performance, hardware efficiency and application flexibility is achieved.

Embodiments disclosed in this application pertain to the field of computer technologies, and in particular, to a method for performing FFT, a processor, and a computing device. The method includes: A processor responds to an execution request of fast Fourier transform FFT calculation of an application, and decomposes the FFT calculation into a plurality of calculation stages. The processor sequentially executes the plurality of calculation stages, where when a target calculation stage is executed, a vector operation circuit performs rotation factor calculation, and a matrix operation circuit performs DFT calculation. After the execution of the plurality of calculation stages is completed, the processor determines an execution result of the FFT calculation based on an execution result of a last calculation stage, and returns the execution result to the application. vector operation circuit matrix operation circuit

The application relates to a low-complexity OCDM modulation and demodulation implementation method based on FPGA, and belongs to the technical field of electronic communication. The DFnT or IDFnT is split into twice rotation factor multiplication, FFT or IFFT transformation, phase and amplitude adjustment steps to realize OCDM modulation and demodulation. The IQ data module is used to input IQ data to be subjected to DFnT or IDFnT transformation; the first rotation factor multiplication module is used to multiply the first rotation factor after phase rotation with the input data; the FFT or IFFT module is used to perform FFT or IFFT transformation on the output result of the first rotation factor multiplication; then, the data is subjected to second rotation factor multiplication; finally, the phase and amplitude are adjusted to complete OCDM modulation or demodulation. The application provides an OCDM modulation and demodulation scheme based on FPGA, and the storage capacity is reduced under the condition of invariable complexity.

The invention discloses a twiddle factor table generation method for number theory transformation, which is mainly based on decomposition of a polynomial on a finite field and comprises the steps of key data generation, polynomial decomposition and data selection, inverse number theory transformation data calculation, Montgomery domain conversion and the like. The method comprises the following steps of: decomposing five types of polynomials of an original three-term expression, square difference, square sum, cubic difference and cubic sum according to levels and a specific sequence, then selecting negative values of constant term parts of partial polynomials to form a rotation factor table of positive number theory transformation, and then calculating a rotation factor table used by inverse number theory transformation according to the rotation factor table of the positive number theory transformation, and finally, converting the twiddle factor table data to the Montgomery domain to obtain a final twiddle factor table. According to the technical scheme, the implementation efficiency of number theory transformation can be remarkably improved, and finer granularity and a wider range are provided for selection of lattice-based password parameters; and the efficiency of anti-quantum encryption, decryption and signature algorithms is improved.

The invention discloses a QR decomposition matrix inversion optimization method and system. The method comprises the following steps: receiving signal data, and carrying out FFT (Fast Fourier Transform) preprocessing and data downsampling; double-buffer optimization parallel processing is adopted, and FFT signal data are stored based on a double-buffer FIFO data storage structure; calculating a covariance matrix of the FFT signal data; adopting Givens rotation to gradually eliminate off-diagonal elements of the covariance matrix, carrying out Givens rotation calculation, and adopting an optimized CORDIC calculation method to calculate a Givens rotation factor; a calculation process of Givens rotation is accelerated by adopting a Systolic array architecture; and outputting a final QR decomposition result according to a Givens rotation calculation result. According to the method, the data flow is optimized, the calculation throughput rate is improved, hardware resource occupation is reduced, a low-power-consumption and high-performance hardware implementation scheme is provided for efficient matrix calculation, and the method has wide engineering application value.

This invention relates to a method and apparatus for resolving velocity ambiguity based on constant frequency assistance. The method includes the following steps: a radar sequentially transmits a constant frequency band signal and a linear continuously modulated pulse train, and acquires the radar echo signal; both the constant frequency band echo signal and the sawtooth band echo signal are mixed to obtain a constant frequency band intermediate frequency signal and a sawtooth band intermediate frequency signal; the constant frequency band intermediate frequency signal is processed by a fast Fourier transform to obtain a target true velocity estimate; the sawtooth band intermediate frequency signal is sequentially processed by a two-dimensional fast Fourier transform, a two-dimensional constant false alarm rate (CFAR) processing, and a centroid condensation processing to obtain a target range velocity estimate; based on a velocity matching method using a Fourier rotation factor, the target true velocity estimate is matched with the target range velocity estimate to obtain the true velocity of all targets. This method not only resolves velocity ambiguity but also improves velocity accuracy, offering advantages such as high velocity measurement accuracy, high real-time performance, and simplicity.

The invention discloses a sampling frequency offset phase compensation method and device under QPSK modulation, and relates to the technical field of phase compensation methods, and the method comprises the steps: collecting each load frame, and carrying out the QPSK modulation of the load frames; configuring a corresponding phase twiddle factor for each OFDM symbol based on the QPSK modulation of each load frame; in the calculation process of the phase twiddle factor, determining a corresponding phase compensation value based on the rotation compensation of each subcarrier until all subcarriers in each load frame have corresponding phase compensation values; according to the method, corresponding diversity combining is triggered according to each OFDM symbol, at the moment, a sampling frequency offset estimation value does not need to be directly estimated, approximate sampling frequency offset phase deflection information is obtained after multiple pieces of subcarrier information are combined and noise is reduced, correction is carried out according to the approximate sampling frequency offset phase deflection information, and a good correction effect can also be obtained under the low signal-to-noise ratio. Phase compensation is carried out on corresponding data before demodulation and decoding, and the receiving performance is improved.

The present invention discloses a calculation method and system for reducing the storage overhead of the rotation transformation in FFT. The method includes: Step 1, calculating n2 discrete Fourier transforms of length n1, where the on-chip cache of the processor can store at most the data required for calculating m discrete Fourier transforms of length n1, and m = on-chip cache of the processor / cache required for calculating the discrete Fourier transform of length n1; Step 2, calculating the rotation factor, performing the rotation transformation, and calculating n1 discrete Fourier transforms of length n2, where the on-chip cache of the processor can store at most the data required for calculating t discrete Fourier transforms of length n2. While maintaining a relatively low computational amount, the present invention effectively reduces the cache overhead required for calculating the rotation factor.

The invention relates to the technical field of three-phase power supply fundamental wave voltage calculation methods, and discloses an ATSE power supply fundamental wave voltage calculation method based on a Goertzel algorithm, which comprises the following steps: data acquisition: acquiring AD data of three-phase voltage of a power supply according to a fixed sampling rate through a sampling circuit of a controller; setting parameters: setting an initial frequency of frequency detection, a period number k = 1 and a sampling number N of each period; common variables are calculated, wherein the common variables of the Goertzel algorithm are calculated through a twiddle factor # imgabs0 # imgabs1 # and a twiddle factor # imgabs2 #; resampling operation: carrying out resampling operation on each sampling point according to a set frequency; and convolution operation: sequentially carrying out convolution operation on the resampled AD data. According to the method, the discrete Fourier transform is regarded as a group of filters through the Goertzel algorithm, so that the problem of relatively large delay caused by the fact that most of the existing three-phase power supply fundamental wave calculation methods widely applied to dual-power automatic change-over switch products in the market adopt the FFT algorithm is solved.

The invention discloses a frequency estimation method and device for FMCW-Lidar, and relates to the technical field of signal processing, and the method comprises the following steps: carrying out the N-point FFT of a carrier frequency signal, and obtaining a user-defined signal based on a twiddle factor; splitting the custom signal into a real part and an imaginary part, and obtaining a real part expression and an imaginary part expression; obtaining a real part ratio factor and an imaginary part ratio factor; based on the signal sampling frequency of the carrier frequency signal and the corresponding real part ratio factor and imaginary part ratio factor, calculating to obtain an estimated frequency of the carrier frequency signal; and obtaining an accurate estimation frequency of the carrier frequency signal based on the estimation frequency of the carrier frequency signal and the signal sampling frequency of the carrier frequency signal. According to the invention, the carrier frequency signal is processed based on the preset data processing flow and the calculation flow, and then estimation and accurate estimation are carried out, so that the real-time performance of the FMCW-Lidar frequency estimation algorithm is effectively improved.

Provided is an NTT acceleration chip, including: a twiddle factor computing module, including a plurality of pre-computing units and a plurality of real-time computing units, where the plurality of pre-computing units is configured to compute several initial lines of twiddle factors and an inter-line step factor in parallel by using a primitive root of unity; and the plurality of real-time computing units is configured to repeatedly and iteratively compute other lines of twiddle factors in parallel according to the inter-line step factor; a transposition module, including a plurality of transposition units, configured to perform transposition processing on an input sequence in parallel, to obtain a transposed sequence; and an NTT computing module, including a plurality of butterfly computing units, configured to perform a butterfly operation of orders and a point quantity in parallel according to the twiddle factors and the transposed sequence, to obtain an output sequence.

The invention relates to the technical field of three-phase power supply frequency calculation methods, and discloses an improved ATSE power supply frequency calculation method, which comprises the following steps: S1, acquiring voltage AD data of a three-phase power supply through a controller; s2, setting an initial frequency, a period number and a sampling point number of each period; s3, calculating twiddle factors in the Goertzel algorithm; s4, performing convolution operation on the AD data of each period in sequence; s5, calculating the frequency domain information of two periods, and obtaining the frequency information of the current power supply based on the phase deviation; s6, dynamically adjusting the AD data sampling rate of the next period; and S7, the frequency information assists the automatic change-over switch to judge and control the state of the power supply. By adopting the power supply frequency calculation method based on the Goertzel algorithm, the actual frequency of the power supply can be accurately captured by abandoning interference of higher harmonics and only keeping fundamental wave information for calculation, and the method has better anti-interference capability in a complex power environment with higher harmonic content.

The application relates to an expandable distributed privacy protection FFT method and system based on secret sharing and MAC tags, which comprises the following steps: input original data is divided into multiple data shares by adopting a three-party replication secret sharing technology, a corresponding MAC tag is generated for each data share, and the secret sharing is performed to each participant cluster; each computing node in each participant cluster performs one-dimensional fast Fourier transform on each row of the held data share to obtain an intermediate matrix; a rotation factor is multiplied with the intermediate matrix to obtain a rotation matrix; each computing node divides the rotation matrix into multiple section shares in the column direction, and sends each section share to a corresponding group leader according to the serial number of the section share; the computing node calculates the fast Fourier transform in the column direction to obtain an output matrix, and a principal verifies the output matrix; while resisting malicious attacks, the communication complexity is reduced from O(M) to O(M / N), the MAC verification overhead is reduced to less than 8% of the total time consumption, and the expandability of the system is greatly improved.

The invention discloses a full-pipeline single-path delay feedback structure fast Fourier transform calculation unit capable of simply addressing twiddle factors, which comprises SDF modules at all levels, twiddle factor read-out modules corresponding to the SDF modules, and a three-real-number complex multiplier of a pipeline structure. According to the twiddle factor reading module provided by the invention, orderly input of twiddle factors can be realized only by using three either-or data selectors, a synchronous counter and a synchronous ROM (Read Only Memory) and depending on two control signals; although the three-real-number and complex-number multiplier of the pipeline structure sacrifices the data throughput, the power consumption is greatly reduced, and meanwhile, it is ensured that the proposed FFT calculation unit is of a full pipeline architecture, so that no interval exists between two adjacent continuous output periods.

The invention relates to a navigation signal capturing method based on a reconfigurable PMF-FFT algorithm, and belongs to the technical field of satellite navigation. The method comprises the following steps: generating a partial correlation value from input data containing frequency offset / code offset through partial matched filtering (PMF); zero padding is carried out on the result to 2n points, and then the result is input into a reconfigurable FFT module for multi-stage radix-2 operation; by dynamically configuring FFT points (32 / 64 / 128) and multiplexing a twiddle factor ROM (Read Only Memory), resource occupation is optimized; and calculating the frequency offset based on peak detection and threshold judgment. Through ping-pong RAM cache, FIFO switching and cascade butterfly operation, high throughput rate data processing is realized, the problems of resource solidification, data overflow and insufficient resolution in a traditional scheme are solved, the frequency offset estimation error is less than or equal to 5Hz, the power consumption is reduced by 40%, and the method is suitable for real-time signal acquisition in a high dynamic environment.

The application provides an application method and system of a specific accelerator and the specific accelerator, the first processor comprises the specific accelerator, the specific accelerator is an FFT accelerator, the method comprises the following steps: obtaining instruction information, the instruction information is an instruction meeting a custom coding rule of a reduced instruction set; obtaining a required sampling point number and to-be-processed data based on the instruction information; selecting a delay feedback module in a preset delay feedback module set of the specific accelerator according to the sampling point number, and selecting a target twiddle factor storage unit in a twiddle factor storage module; enabling at least two delay feedback modules and the target twiddle factor storage unit to obtain a target accelerator circuit; inputting the to-be-processed data into the target accelerator circuit to obtain a calculation result. Since the specific accelerator can support custom instructions to perform calculation of different sampling point numbers, instruction extension is realized, the instruction extension matches the structure extension of the specific accelerator, and the structural form of the specific accelerator is improved.

The invention provides an FFT (Fast Fourier Transform) data stream acceleration method based on RISC-V. The method comprises the following steps: configuring a vector control state register according to an FFT point number; a data loading strategy is selected according to whether the point number exceeds a threshold value or not, small-scale data are loaded to a vector register set at a time, and large-scale data are loaded multiple times after being split; parallel operation is started through a vector butterfly operation instruction, operands and twiddle factors are read according to position information of a register and the instruction, and the operands and the twiddle factors are sequentially written back after operation is completed; and finally, storing the result in a memory, and processing according to a loading strategy: directly outputting the result in one-time loading, and carrying out data rearrangement and iterative operation in multiple loading until all FFT levels are completed. The invention also provides an FFT (Fast Fourier Transform) data stream acceleration device based on the RISC-V. Therefore, vectorized FFT operation is carried out based on the extended instruction set of the RISC-V, data are rearranged in the processor based on the thought of the data stream, and the operation efficiency when the ASIP carries out FFT is improved.

The present disclosure provides a method for executing a cryptographic operation including a NTT computation that transforms a polynomial with N coefficients from time-domain to frequency-domain. The NTT computation is divided into successive stages of butterfly operations that combine coefficients, starting from the N coefficients up to N transformed coefficients. During each stage, each butterfly combines a pair of coefficients among the N coefficients, using a NTT twiddle factor to progressively transform the pair of coefficients and uses a set of mask-related twiddle factors such. This set is based on the two input masks and on the output mask. The butterfly operations are grouped into blocks of at least two butterfly operations where all the butterfly operations within a same block have a same combination of masks in input and output at each stage of the NTT computation.

The embodiment of the invention relates to the field of network security design, in particular to a twiddle factor real-time generation method and device for fully homomorphic encryption. A specific embodiment of the method comprises the following steps: determining an initial twiddle factor set; determining a fully homomorphic encryption algorithm based on the initial twiddle factor set; determining first butterfly unit information based on a fully homomorphic encryption algorithm; determining first twiddle factor information based on a fully homomorphic encryption algorithm and the first butterfly unit information; updating the first butterfly unit information to generate second butterfly unit information; updating the first twiddle factor information based on a fully homomorphic encryption algorithm and the second butterfly unit information to generate second twiddle factor information; and updating the second twiddle factor information to generate target twiddle factor information. According to the embodiment, the storage amount of twiddle factors can be compressed, the storage space is saved, and the problem that the overall rate is reduced due to transmission of a large number of twiddle factors is solved.

The invention relates to a fast Fourier transform method and device for improving the utilization rate of a storage space. The fast Fourier transform method comprises the following steps of: 1, writing input data into the storage space in an address close arrangement form; 2, calculating a twiddle factor, and storing the twiddle factor into a storage space; 3, FFT input data processing is carried out, specifically, step 31, FFT input data is subjected to data inverted-order storage; step 32, performing data operation, specifically, step 321, expanding the twiddle factors obtained in the step 2 to obtain a twiddle factor complete set; and step 322, performing butterfly operation, and obtaining output Fourier transform data after continuous traversal is completed. According to the method, the storage resources required by the input data and the output data are reduced by converting the floating point data format of the input data and adapting the adder and the multiplier of the computing resources; and the aim of saving memory resources is fulfilled on the premise of ensuring the calculation efficiency.

The embodiments disclosed in the present application belong to the technical field of computers, particularly relate to a method for executing a fast NTT, an apparatus and a computer device. The method is executed by a processor, and the method comprises: a processor receiving an execution instruction for a fast NTT sent by an application, and acquiring a data sequence on which the fast NTT will be executed; on the basis of a length value of the data sequence, determining in a candidate radix set radixes respectively corresponding to a plurality of calculation stages comprised in the fast NTT, the candidate radix set comprising a plurality of candidate radixes, and the value of each candidate radix being greater than 2 and being an integer power of 2; acquiring a twiddle factor corresponding to each calculation stage; and, on the basis of the data sequence and the twiddle factor corresponding to each calculation stage, successively executing the calculation stages so as to obtain a result of executing the fast NTT. Using the present application can improve the efficiency of executing fast NTTs.