114 results about "Twiddle factor" patented technology

Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.

The invention discloses a number-theory transformation structure of concurrency constant geometry, which uses two polynomial storage blocks to store polynomials, namely a left storage block MembL and a right storage block MembR, each of the left storage block MembL and the right storage block MembR consists of four 1024 * 24 single-port SRAMs (Static Random Access Memory), and n is an integer multiple greater than or equal to 16; and parallel computing of the two butterfly arithmetic units is realized through the four multiplexers, and position transformation of input and output data of the BFU is controlled. To be compatible with multiple algorithms, there is a need for an additional number-theoretical transform constant memory to store a pre-computed twiddle factor to provide a required twiddle factor access bandwidth. According to the method, data independence between polynomial storage blocks is utilized, a modular arithmetic unit of a two-concurrence BFU is designed, and the polynomial multiplication performance is improved by more than one time under the condition that the area increase is limited.

The invention discloses a lattice-based cryptographic algorithm-oriented side channel attack-resistant NTT circuit, which comprises a control unit, which is mainly used for controlling the enabling of a bottom layer component in the structure and the data flow direction among modules; the storage unit is used for storing the coefficient, the random twiddle factor address and the twiddle factor; the address generation unit is used for calculating and generating a storage RAM (Random Access Memory) address of a twiddle factor participating in operation and a read address required by the coefficient storage unit; and the coefficient transposing unit is used for realizing coefficient reading meeting the index distance among all NTT stages. According to the side channel attack resisting NTT circuit oriented to the lattice-based cryptographic algorithm, when a low delay base-4CT / GS butterfly unit is masked, the increment of modular multiplication resources is reduced, and the resource consumption is remarkably reduced while high security is kept.

The invention provides a high-speed NTT method and system based on GPU matrix-thread collaborative optimization. The method comprises the steps that an input twiddle factor is converted into a matrix form; transmitting the updated twiddle factor matrix and the input array to a graphics processor; according to the input array and the size of the twiddle factor matrix, the number of blocks in the grid and the number of threads included in each block are set, so that each block is responsible for the operation of multiplying one row by one column, and each thread in the block completes the operation of multiplying one pair of data in the corresponding row-by-column process to obtain a group of intermediate results; and obtaining output data corresponding to the block according to an intermediate result in the block, and sending the output data to a corresponding position of an output matrix to serve as a multiplication result. According to the method, NTT calculation is reconstructed into parallel matrix-vector operation, the maximum utilization of GPU calculation resources is realized through the combination of an efficient thread allocation strategy and an optimized memory access mode, and the calculation efficiency is remarkably improved.

Devices, e.g., hardware accelerators, and systems are operable to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

Embodiments of the present specification provide a method of constructing a processing circuit for a target transformation. The target transform is a discrete transform or an inverse transform thereof that transforms an input coefficient sequence into an output coefficient sequence based on a twiddle factor. The method comprises the following steps: aiming at a to-be-processed K point input coefficient sequence, determining a plurality of alternative decomposition points corresponding to a k-bit coefficient index; and then, starting from a low-order decomposition point, sequentially aiming at each alternative decomposition point, according to a decomposition cost evaluation function, through recursive multi-level index bit decomposition, determining the minimum storage cost under each alternative decomposition point, so as to determine a target decomposition mode of the k-bit coefficient index with the minimum storage cost. The decomposition cost assessment function defines storage costs including a cost of a (n-p) order first transform, a cost of a p order second transform, a local cost for inter-stage twiddle factor multiplication. And according to the target decomposition mode, allocating a corresponding memory to the twiddle factor for forming a processing circuit.

The invention discloses a lattice cryptographic modular multiplication method and a modular multiplier based on an improved plantard algorithm, which eliminate the post-processing overhead of the traditional modular multiplication method by preprocessing twiddle factors in the level of the modular multiplication method. In hardware implementation, shift-addition is adopted to replace a complex multiplier, a dynamic bit width truncation technology is combined, the bit width of intermediate data is compressed from 39 bits to 21 bits, and logic resource consumption is greatly reduced, so that modular multiplication operation in a lattice password digital signature scheme can be quickly and efficiently completed.

Embodiments of the present specification provide methods of storing or reading twiddle factors in a target transformation. The target transform is a discrete transform or an inverse transform thereof that transforms an input coefficient sequence into an output coefficient sequence based on a twiddle factor. The method comprises the following steps: determining a target twiddle factor to be stored, wherein the power of the target twiddle factor is a result of a product modular target value of a first factor of a first digit and a second factor of a second digit; the target twiddle factor is stored in a two-stage storage mode, and the two-stage storage mode comprises the steps that the target twiddle factor is stored at a first address in a twiddle factor storage device, and the twiddle factor storage device comprises a first number of first storage units, the first number is the number of different modular multiplication results generated by the factor of the first digit and the factor of the second digit; storing an index value directed to the first address at a second address in an index memory, where the index memory includes a target number of second memory cells, the second address corresponding to a power of the target twiddle factor; the target value is greater than the first number.

Embodiments of the present application provide a system, a device, and a method for a two-variable number theoretic transform. A matrix having the two-variable number theoretic transform may be applied to a matrix having dimensions a×b, where a=2x and b=2y for x≥y. The two-variable number theoretic transform includes two stages: decomposition by rows and row-wise fast Fourier transforms (FFTs), with twiddle factors computed based on a first root α satisfying αb=−1 mod p; and decomposition by columns and column-wise FFTs, with twiddle factors computed based on a second root β satisfying β2a=2 or −2 mod p. Since each of the stages uses a different root, the number of twiddle factors is reduced.

Generally discussed herein are devices, systems, and methods for performing a number theoretic transform (NTT) / inverse NTT (INTT). A circuit for NTT / INTT can include a first butterfly operator circuit (BOC) that generates first and second output coefficients based on first and second polynomial coefficients and a twiddle factor, a second BOC that operates in parallel with the first BOC and generates third and fourth output coefficients based on third and fourth polynomial coefficients and the twiddle factor, a third BOC that operates in series with the first and second BOCs and generates fifth and sixth output coefficients based on the first and third output coefficients and a second twiddle factor, and a fourth BOC that operates in series with the first and second BOCs and in parallel with the third BOC and generates seventh and eighth output coefficients based on the second and fourth output coefficients and a third twiddle factor.

The invention belongs to the technical field of FFT (Fast Fourier Transform) calculation acceleration, and particularly relates to a self-adaptive FFT operation processor module for processing large data volume, which comprises an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT calculation module and a control module, the FFT calculation module comprises m rows of radix-2kMDC modules which are arranged side by side; the data rearrangement unit comprises a read-write data storage module and a data preprocessing module; the read-write data storage module consists of a plurality of memories; the data preprocessing module is composed of a plurality of parallel branch switching circuits and a plurality of shuffling units with different depths; the twiddle factor storage module is used for storing fixed constant twiddle factors and realizing repeated utilization of the constant twiddle factors according to the calculated points; the address generation module is used for generating an address sequence for data reading / writing by using a program counter, the control module is used for controlling and executing FFT calculation, and different FFT calculation requirements can be met. And the utilization rate of the butterfly operation unit and the calculation throughput rate of the whole architecture are improved.

Fourier transform operations may be converted to matrix multiplications that may be like matrix multiplications in convolutions and can be executed by deep neural network (DNN) accelerators. A DNN accelerator may receive an input tensor representing an input signal of a Fourier transform operation. The input tensor may include activations arranged in one or more rows and one or more columns. The DNN accelerator may receive a weight tensor determined based on one or more twiddle factors of the Fourier transform operation. The DNN accelerator may perform two sequences of multiply-accumulate (MAC) operations. An MAC operation in the first sequence may be performed on the weight tensor and a row in the input tensor. An MAC operation in the second sequence may be performed on the weight tensor and a column in the input tensor. The outputs of the MAC operations may represent the Fourier transform of the input signal.

Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.

The embodiments of the present application belong to the technical field of computers. Disclosed are a method and apparatus for executing FFT computation, and a computing device. The method comprises: on the basis of the length of a data sequence to be subjected to FFT computation, dividing the FFT computation into a plurality of computation stages; for at least one target computation stage among the plurality of computation stages, on the basis of radixes respectively corresponding to the plurality of computation stages, and the execution order of the target computation stages among the plurality of computation stages, determining a merged matrix corresponding to the target computation stage, wherein the merged matrix is a product of a discrete Fourier transform (DFT) coefficient matrix and a twiddle factor in the target computation stage; and when executing the target computation stage, determining the product of an input sequence of the target computation stage and the merged matrix, and determining the product to be an output sequence of the target computation stage. By means of the present application, a computation amount corresponding to a computation stage can be reduced, thereby improving the execution efficiency of FFT computation.

Generally discussed herein are devices, systems, and methods for performing a number theoretic transform (NTT) / inverse NTT (INTT). A circuit for NTT / INTT can include a first butterfly operator circuit (BOC) that generates first and second output coefficients based on first and second polynomial coefficients and a twiddle factor, a second BOC that operates in parallel with the first BOC and generates third and fourth output coefficients based on third and fourth polynomial coefficients and the twiddle factor, a third BOC that operates in series with the first and second BOCs and generates fifth and sixth output coefficients based on the first and third output coefficients and a second twiddle factor, and a fourth BOC that operates in series with the first and second BOCs and in parallel with the third BOC and generates seventh and eighth output coefficients based on the second and fourth output coefficients and a third twiddle factor.

The invention discloses a hardware acceleration method for a Fourier neural operator. The hardware acceleration method comprises the following steps: setting an FFT module and a DFT / NN module which are independent from each other on an FNO hardware accelerator; performing fast Fourier transform (FFT) calculation on the batch input data by using an FFT module; a DFT / NN module is utilized to execute discrete Fourier transform (DFT) calculation based on a Bluestein algorithm, and access mode parallel random access of twiddle factors is reconstructed into parallel rule access; in an FNO hardware accelerator, an FFT module or a DFT / NN module is adaptively selected as a unit for executing calculation based on static parameter analysis of input dimensions, transformation points and frequency cut-off output points, and corresponding operator fusion is executed based on a predefined operator fusion mode. The adaptive capacity of the FNO to different transformation points and dimension structures is enhanced, and effective unification of computing performance, hardware efficiency and application flexibility is achieved.

Embodiments disclosed in this application pertain to the field of computer technologies, and in particular, to a method for performing FFT, a processor, and a computing device. The method includes: A processor responds to an execution request of fast Fourier transform FFT calculation of an application, and decomposes the FFT calculation into a plurality of calculation stages. The processor sequentially executes the plurality of calculation stages, where when a target calculation stage is executed, a vector operation circuit performs rotation factor calculation, and a matrix operation circuit performs DFT calculation. After the execution of the plurality of calculation stages is completed, the processor determines an execution result of the FFT calculation based on an execution result of a last calculation stage, and returns the execution result to the application. vector operation circuit matrix operation circuit

The invention relates to a broadband oscillation signal component analysis method based on non-iterative classification interpolation. The method comprises the following steps: firstly, carrying out modeling and time domain sampling on a random broadband oscillation signal to obtain a sampling signal; then windowing Fourier transform and twiddle factor correction are carried out on the sampling signals; then, a frequency rough estimation sequence is determined based on the corrected sampling signal; then, oscillation frequency separation is carried out based on the frequency rough estimation sequence, and oscillation frequency and non-oscillation frequency are determined through a classification interpolation formula; and finally, determining a non-oscillation amplitude, an oscillation amplitude and a damping factor by adopting a least square method based on the sampling signal, the oscillation frequency and the non-oscillation frequency. That is to say, signal component analysis and parameter calculation can be quickly carried out under the condition that the number of components in the signal is unknown and component models are different through the non-iterative classification interpolation and the least square method.

The application relates to a low-complexity OCDM modulation and demodulation implementation method based on FPGA, and belongs to the technical field of electronic communication. The DFnT or IDFnT is split into twice rotation factor multiplication, FFT or IFFT transformation, phase and amplitude adjustment steps to realize OCDM modulation and demodulation. The IQ data module is used to input IQ data to be subjected to DFnT or IDFnT transformation; the first rotation factor multiplication module is used to multiply the first rotation factor after phase rotation with the input data; the FFT or IFFT module is used to perform FFT or IFFT transformation on the output result of the first rotation factor multiplication; then, the data is subjected to second rotation factor multiplication; finally, the phase and amplitude are adjusted to complete OCDM modulation or demodulation. The application provides an OCDM modulation and demodulation scheme based on FPGA, and the storage capacity is reduced under the condition of invariable complexity.

The invention discloses a twiddle factor table generation method for number theory transformation, which is mainly based on decomposition of a polynomial on a finite field and comprises the steps of key data generation, polynomial decomposition and data selection, inverse number theory transformation data calculation, Montgomery domain conversion and the like. The method comprises the following steps of: decomposing five types of polynomials of an original three-term expression, square difference, square sum, cubic difference and cubic sum according to levels and a specific sequence, then selecting negative values of constant term parts of partial polynomials to form a rotation factor table of positive number theory transformation, and then calculating a rotation factor table used by inverse number theory transformation according to the rotation factor table of the positive number theory transformation, and finally, converting the twiddle factor table data to the Montgomery domain to obtain a final twiddle factor table. According to the technical scheme, the implementation efficiency of number theory transformation can be remarkably improved, and finer granularity and a wider range are provided for selection of lattice-based password parameters; and the efficiency of anti-quantum encryption, decryption and signature algorithms is improved.

The invention discloses a QR decomposition matrix inversion optimization method and system. The method comprises the following steps: receiving signal data, and carrying out FFT (Fast Fourier Transform) preprocessing and data downsampling; double-buffer optimization parallel processing is adopted, and FFT signal data are stored based on a double-buffer FIFO data storage structure; calculating a covariance matrix of the FFT signal data; adopting Givens rotation to gradually eliminate off-diagonal elements of the covariance matrix, carrying out Givens rotation calculation, and adopting an optimized CORDIC calculation method to calculate a Givens rotation factor; a calculation process of Givens rotation is accelerated by adopting a Systolic array architecture; and outputting a final QR decomposition result according to a Givens rotation calculation result. According to the method, the data flow is optimized, the calculation throughput rate is improved, hardware resource occupation is reduced, a low-power-consumption and high-performance hardware implementation scheme is provided for efficient matrix calculation, and the method has wide engineering application value.

This invention relates to a method and apparatus for resolving velocity ambiguity based on constant frequency assistance. The method includes the following steps: a radar sequentially transmits a constant frequency band signal and a linear continuously modulated pulse train, and acquires the radar echo signal; both the constant frequency band echo signal and the sawtooth band echo signal are mixed to obtain a constant frequency band intermediate frequency signal and a sawtooth band intermediate frequency signal; the constant frequency band intermediate frequency signal is processed by a fast Fourier transform to obtain a target true velocity estimate; the sawtooth band intermediate frequency signal is sequentially processed by a two-dimensional fast Fourier transform, a two-dimensional constant false alarm rate (CFAR) processing, and a centroid condensation processing to obtain a target range velocity estimate; based on a velocity matching method using a Fourier rotation factor, the target true velocity estimate is matched with the target range velocity estimate to obtain the true velocity of all targets. This method not only resolves velocity ambiguity but also improves velocity accuracy, offering advantages such as high velocity measurement accuracy, high real-time performance, and simplicity.

The invention discloses a sampling frequency offset phase compensation method and device under QPSK modulation, and relates to the technical field of phase compensation methods, and the method comprises the steps: collecting each load frame, and carrying out the QPSK modulation of the load frames; configuring a corresponding phase twiddle factor for each OFDM symbol based on the QPSK modulation of each load frame; in the calculation process of the phase twiddle factor, determining a corresponding phase compensation value based on the rotation compensation of each subcarrier until all subcarriers in each load frame have corresponding phase compensation values; according to the method, corresponding diversity combining is triggered according to each OFDM symbol, at the moment, a sampling frequency offset estimation value does not need to be directly estimated, approximate sampling frequency offset phase deflection information is obtained after multiple pieces of subcarrier information are combined and noise is reduced, correction is carried out according to the approximate sampling frequency offset phase deflection information, and a good correction effect can also be obtained under the low signal-to-noise ratio. Phase compensation is carried out on corresponding data before demodulation and decoding, and the receiving performance is improved.

The present invention discloses a calculation method and system for reducing the storage overhead of the rotation transformation in FFT. The method includes: Step 1, calculating n2 discrete Fourier transforms of length n1, where the on-chip cache of the processor can store at most the data required for calculating m discrete Fourier transforms of length n1, and m = on-chip cache of the processor / cache required for calculating the discrete Fourier transform of length n1; Step 2, calculating the rotation factor, performing the rotation transformation, and calculating n1 discrete Fourier transforms of length n2, where the on-chip cache of the processor can store at most the data required for calculating t discrete Fourier transforms of length n2. While maintaining a relatively low computational amount, the present invention effectively reduces the cache overhead required for calculating the rotation factor.

The invention relates to the technical field of three-phase power supply fundamental wave voltage calculation methods, and discloses an ATSE power supply fundamental wave voltage calculation method based on a Goertzel algorithm, which comprises the following steps: data acquisition: acquiring AD data of three-phase voltage of a power supply according to a fixed sampling rate through a sampling circuit of a controller; setting parameters: setting an initial frequency of frequency detection, a period number k = 1 and a sampling number N of each period; common variables are calculated, wherein the common variables of the Goertzel algorithm are calculated through a twiddle factor # imgabs0 # imgabs1 # and a twiddle factor # imgabs2 #; resampling operation: carrying out resampling operation on each sampling point according to a set frequency; and convolution operation: sequentially carrying out convolution operation on the resampled AD data. According to the method, the discrete Fourier transform is regarded as a group of filters through the Goertzel algorithm, so that the problem of relatively large delay caused by the fact that most of the existing three-phase power supply fundamental wave calculation methods widely applied to dual-power automatic change-over switch products in the market adopt the FFT algorithm is solved.

Method for the approximate calculation of butterfly units of a Fourier transform of a signal in which binary or ternary quantization is performed, wherein the method comprises: Representing a number of butterfly units of a Fourier transform; approximating the number of butterfly units by quantizing rotation factors associated with the butterfly units to obtain approximate rotation factors, wherein a bit width of a quantized, approximate rotation factor is less than or equal to 8 bits, wherein, in the case of binary or ternary quantization, the procedure comprises: minimizing an error between the approximate rotation factors and the rotation factors by using a correction factor α, wherein the correction factor α is a non-1 constant known prior to α.

The present application discloses a method and device for encoding and reading rotation factors, a medium and a chip. The encoding device includes: a first acquisition module, used to obtain the operation information of the data to be processed, the operation information includes the sequence length of the data to be processed and the degree of parallelism during the forward number theory transformation; based on the operation information, determine the various rotation factors required for the data to be processed during the forward number theory transformation; exclude the rotation factors of the data to be processed in the first preset number of stages of the forward number theory transformation; an encoding module, used to construct the storage mapping relationship between the various rotation factors in the remaining stages and the various static random access memories for storing the rotation factors. In an embodiment of the present application, after the storage mapping relationship is constructed based on the encoding device, when storing the various rotation factors based on the storage mapping relationship, the redundant rotation factors in the first b-1 stages do not need to be stored, thereby reducing the storage space overhead of the rotation factors.

The invention discloses a frequency estimation method and device for FMCW-Lidar, and relates to the technical field of signal processing, and the method comprises the following steps: carrying out the N-point FFT of a carrier frequency signal, and obtaining a user-defined signal based on a twiddle factor; splitting the custom signal into a real part and an imaginary part, and obtaining a real part expression and an imaginary part expression; obtaining a real part ratio factor and an imaginary part ratio factor; based on the signal sampling frequency of the carrier frequency signal and the corresponding real part ratio factor and imaginary part ratio factor, calculating to obtain an estimated frequency of the carrier frequency signal; and obtaining an accurate estimation frequency of the carrier frequency signal based on the estimation frequency of the carrier frequency signal and the signal sampling frequency of the carrier frequency signal. According to the invention, the carrier frequency signal is processed based on the preset data processing flow and the calculation flow, and then estimation and accurate estimation are carried out, so that the real-time performance of the FMCW-Lidar frequency estimation algorithm is effectively improved.

Provided is an NTT acceleration chip, including: a twiddle factor computing module, including a plurality of pre-computing units and a plurality of real-time computing units, where the plurality of pre-computing units is configured to compute several initial lines of twiddle factors and an inter-line step factor in parallel by using a primitive root of unity; and the plurality of real-time computing units is configured to repeatedly and iteratively compute other lines of twiddle factors in parallel according to the inter-line step factor; a transposition module, including a plurality of transposition units, configured to perform transposition processing on an input sequence in parallel, to obtain a transposed sequence; and an NTT computing module, including a plurality of butterfly computing units, configured to perform a butterfly operation of orders and a point quantity in parallel according to the twiddle factors and the transposed sequence, to obtain an output sequence.

A cryptosystem processor includes a twiddle factor memory, a SRDGT BFU, and a SPN. The twiddle factor memory has ZETA ports. The at least one SRDGT BFU has six input ports and four output ports and switchable among operation in DGT / IDGT / CWM mode, in which two of the input ports electrically communicate with the ZETA ports, respectively. The SRDGT BFU is configured to read and write two data points when working under the DGT / IDGT mode and is configured to read and write four data points when working under the CWM mode. The SPN electrically communicates with the SRDGT BFU and has at least one dual-port BRAM serving as memory cache configured to store polynomial, in which the SPN is configured to support the required number of data points reading or writing per cycle in the DGT / IDGT / CWM mode.