32 results about "Twiddle factor" patented technology

Embodiments of the present application provide a system, a device, and a method for a two-variable number theoretic transform. A matrix having the two-variable number theoretic transform may be applied to a matrix having dimensions a×b, where a=2x and b=2y for x≥y. The two-variable number theoretic transform includes two stages: decomposition by rows and row-wise fast Fourier transforms (FFTs), with twiddle factors computed based on a first root α satisfying αb=−1 mod p; and decomposition by columns and column-wise FFTs, with twiddle factors computed based on a second root β satisfying β2a=2 or −2 mod p. Since each of the stages uses a different root, the number of twiddle factors is reduced.

Generally discussed herein are devices, systems, and methods for performing a number theoretic transform (NTT) / inverse NTT (INTT). A circuit for NTT / INTT can include a first butterfly operator circuit (BOC) that generates first and second output coefficients based on first and second polynomial coefficients and a twiddle factor, a second BOC that operates in parallel with the first BOC and generates third and fourth output coefficients based on third and fourth polynomial coefficients and the twiddle factor, a third BOC that operates in series with the first and second BOCs and generates fifth and sixth output coefficients based on the first and third output coefficients and a second twiddle factor, and a fourth BOC that operates in series with the first and second BOCs and in parallel with the third BOC and generates seventh and eighth output coefficients based on the second and fourth output coefficients and a third twiddle factor.

The invention discloses a hardware acceleration method for a Fourier neural operator. The hardware acceleration method comprises the following steps: setting an FFT module and a DFT / NN module which are independent from each other on an FNO hardware accelerator; performing fast Fourier transform (FFT) calculation on the batch input data by using an FFT module; a DFT / NN module is utilized to execute discrete Fourier transform (DFT) calculation based on a Bluestein algorithm, and access mode parallel random access of twiddle factors is reconstructed into parallel rule access; in an FNO hardware accelerator, an FFT module or a DFT / NN module is adaptively selected as a unit for executing calculation based on static parameter analysis of input dimensions, transformation points and frequency cut-off output points, and corresponding operator fusion is executed based on a predefined operator fusion mode. The adaptive capacity of the FNO to different transformation points and dimension structures is enhanced, and effective unification of computing performance, hardware efficiency and application flexibility is achieved.

Embodiments disclosed in this application pertain to the field of computer technologies, and in particular, to a method for performing FFT, a processor, and a computing device. The method includes: A processor responds to an execution request of fast Fourier transform FFT calculation of an application, and decomposes the FFT calculation into a plurality of calculation stages. The processor sequentially executes the plurality of calculation stages, where when a target calculation stage is executed, a vector operation circuit performs rotation factor calculation, and a matrix operation circuit performs DFT calculation. After the execution of the plurality of calculation stages is completed, the processor determines an execution result of the FFT calculation based on an execution result of a last calculation stage, and returns the execution result to the application. vector operation circuit matrix operation circuit

The application relates to a low-complexity OCDM modulation and demodulation implementation method based on FPGA, and belongs to the technical field of electronic communication. The DFnT or IDFnT is split into twice rotation factor multiplication, FFT or IFFT transformation, phase and amplitude adjustment steps to realize OCDM modulation and demodulation. The IQ data module is used to input IQ data to be subjected to DFnT or IDFnT transformation; the first rotation factor multiplication module is used to multiply the first rotation factor after phase rotation with the input data; the FFT or IFFT module is used to perform FFT or IFFT transformation on the output result of the first rotation factor multiplication; then, the data is subjected to second rotation factor multiplication; finally, the phase and amplitude are adjusted to complete OCDM modulation or demodulation. The application provides an OCDM modulation and demodulation scheme based on FPGA, and the storage capacity is reduced under the condition of invariable complexity.

This invention relates to a method and apparatus for resolving velocity ambiguity based on constant frequency assistance. The method includes the following steps: a radar sequentially transmits a constant frequency band signal and a linear continuously modulated pulse train, and acquires the radar echo signal; both the constant frequency band echo signal and the sawtooth band echo signal are mixed to obtain a constant frequency band intermediate frequency signal and a sawtooth band intermediate frequency signal; the constant frequency band intermediate frequency signal is processed by a fast Fourier transform to obtain a target true velocity estimate; the sawtooth band intermediate frequency signal is sequentially processed by a two-dimensional fast Fourier transform, a two-dimensional constant false alarm rate (CFAR) processing, and a centroid condensation processing to obtain a target range velocity estimate; based on a velocity matching method using a Fourier rotation factor, the target true velocity estimate is matched with the target range velocity estimate to obtain the true velocity of all targets. This method not only resolves velocity ambiguity but also improves velocity accuracy, offering advantages such as high velocity measurement accuracy, high real-time performance, and simplicity.

The invention discloses a frequency estimation method and device for FMCW-Lidar, and relates to the technical field of signal processing, and the method comprises the following steps: carrying out the N-point FFT of a carrier frequency signal, and obtaining a user-defined signal based on a twiddle factor; splitting the custom signal into a real part and an imaginary part, and obtaining a real part expression and an imaginary part expression; obtaining a real part ratio factor and an imaginary part ratio factor; based on the signal sampling frequency of the carrier frequency signal and the corresponding real part ratio factor and imaginary part ratio factor, calculating to obtain an estimated frequency of the carrier frequency signal; and obtaining an accurate estimation frequency of the carrier frequency signal based on the estimation frequency of the carrier frequency signal and the signal sampling frequency of the carrier frequency signal. According to the invention, the carrier frequency signal is processed based on the preset data processing flow and the calculation flow, and then estimation and accurate estimation are carried out, so that the real-time performance of the FMCW-Lidar frequency estimation algorithm is effectively improved.

Provided is an NTT acceleration chip, including: a twiddle factor computing module, including a plurality of pre-computing units and a plurality of real-time computing units, where the plurality of pre-computing units is configured to compute several initial lines of twiddle factors and an inter-line step factor in parallel by using a primitive root of unity; and the plurality of real-time computing units is configured to repeatedly and iteratively compute other lines of twiddle factors in parallel according to the inter-line step factor; a transposition module, including a plurality of transposition units, configured to perform transposition processing on an input sequence in parallel, to obtain a transposed sequence; and an NTT computing module, including a plurality of butterfly computing units, configured to perform a butterfly operation of orders and a point quantity in parallel according to the twiddle factors and the transposed sequence, to obtain an output sequence.

The application relates to an expandable distributed privacy protection FFT method and system based on secret sharing and MAC tags, which comprises the following steps: input original data is divided into multiple data shares by adopting a three-party replication secret sharing technology, a corresponding MAC tag is generated for each data share, and the secret sharing is performed to each participant cluster; each computing node in each participant cluster performs one-dimensional fast Fourier transform on each row of the held data share to obtain an intermediate matrix; a rotation factor is multiplied with the intermediate matrix to obtain a rotation matrix; each computing node divides the rotation matrix into multiple section shares in the column direction, and sends each section share to a corresponding group leader according to the serial number of the section share; the computing node calculates the fast Fourier transform in the column direction to obtain an output matrix, and a principal verifies the output matrix; while resisting malicious attacks, the communication complexity is reduced from O(M) to O(M / N), the MAC verification overhead is reduced to less than 8% of the total time consumption, and the expandability of the system is greatly improved.

The application provides an application method and system of a specific accelerator and the specific accelerator, the first processor comprises the specific accelerator, the specific accelerator is an FFT accelerator, the method comprises the following steps: obtaining instruction information, the instruction information is an instruction meeting a custom coding rule of a reduced instruction set; obtaining a required sampling point number and to-be-processed data based on the instruction information; selecting a delay feedback module in a preset delay feedback module set of the specific accelerator according to the sampling point number, and selecting a target twiddle factor storage unit in a twiddle factor storage module; enabling at least two delay feedback modules and the target twiddle factor storage unit to obtain a target accelerator circuit; inputting the to-be-processed data into the target accelerator circuit to obtain a calculation result. Since the specific accelerator can support custom instructions to perform calculation of different sampling point numbers, instruction extension is realized, the instruction extension matches the structure extension of the specific accelerator, and the structural form of the specific accelerator is improved.

The invention provides an FFT (Fast Fourier Transform) data stream acceleration method based on RISC-V. The method comprises the following steps: configuring a vector control state register according to an FFT point number; a data loading strategy is selected according to whether the point number exceeds a threshold value or not, small-scale data are loaded to a vector register set at a time, and large-scale data are loaded multiple times after being split; parallel operation is started through a vector butterfly operation instruction, operands and twiddle factors are read according to position information of a register and the instruction, and the operands and the twiddle factors are sequentially written back after operation is completed; and finally, storing the result in a memory, and processing according to a loading strategy: directly outputting the result in one-time loading, and carrying out data rearrangement and iterative operation in multiple loading until all FFT levels are completed. The invention also provides an FFT (Fast Fourier Transform) data stream acceleration device based on the RISC-V. Therefore, vectorized FFT operation is carried out based on the extended instruction set of the RISC-V, data are rearranged in the processor based on the thought of the data stream, and the operation efficiency when the ASIP carries out FFT is improved.

The present disclosure provides a method for executing a cryptographic operation including a NTT computation that transforms a polynomial with N coefficients from time-domain to frequency-domain. The NTT computation is divided into successive stages of butterfly operations that combine coefficients, starting from the N coefficients up to N transformed coefficients. During each stage, each butterfly combines a pair of coefficients among the N coefficients, using a NTT twiddle factor to progressively transform the pair of coefficients and uses a set of mask-related twiddle factors such. This set is based on the two input masks and on the output mask. The butterfly operations are grouped into blocks of at least two butterfly operations where all the butterfly operations within a same block have a same combination of masks in input and output at each stage of the NTT computation.

Embodiments of the present specification provide a method for constructing a processing circuit for a target transform. The target transform is a discrete transform or its inverse transform that transforms an input coefficient sequence into an output coefficient sequence based on a rotation factor. The method includes, for a K-point input coefficient sequence to be processed, determining a plurality of candidate decomposition points corresponding to a k-bit coefficient index. Then, starting from a low-bit decomposition point, for each candidate decomposition point, determining the minimum storage cost under each candidate decomposition point according to a decomposition cost evaluation function through recursive index bit number decomposition for several levels, so as to determine a target decomposition mode of the k-bit coefficient index with the minimum storage cost. The decomposition cost evaluation function limits the storage cost to include the cost of a (n-p)th order first transform, the cost of a pth order second transform, and the local cost for inter-level rotation factor multiplication. According to the target decomposition mode, a corresponding memory for the rotation factor is allocated to form a processing circuit.

The application discloses a hardware acceleration method for a Fourier neural operator, and sets up independent FFT modules and DFT / NN modules in an FNO hardware accelerator; the FFT modules are used to perform fast Fourier transform (FFT) calculation on batch input data; the DFT / NN modules are used to perform discrete Fourier transform (DFT) calculation based on a Bluestein algorithm, and a parallel random access mode of a rotation factor is reconstructed into a parallel regular access mode; in the FNO hardware accelerator, based on static parameter analysis on input dimensions, transform point numbers and frequency truncated output point numbers, the FFT modules or the DFT / NN modules are adaptively selected as units for performing calculation, and corresponding operator fusion is performed based on a predefined operator fusion mode. The application enhances the adaptation capability of the FNO to different transform point numbers and dimension structures, and effectively unifies the calculation performance, hardware efficiency and application flexibility.

A non-volatile memory device is configured for in-memory computation of discrete Fourier transformations and their inverses. The real and imaginary components of the twiddle factors are stored as conductance values of memory cells in non-volatile memory arrays having a cross-point structure. The real and imaginary components of inputs are encoded as word line voltages applied to the arrays. Positive and negative valued components of the twiddle factors are stored separately and positive and negative of the inputs are separately applied to the arrays. Real and imaginary parts of the outputs for the discrete Fourier transformation are determined from combinations of the output currents from the arrays.

The application relates to a rotation factor storage method, a reading method and a hardware accelerator for FFT operation. The hardware accelerator comprises a rotation factor storage unit for storing sine components or cosine components in rotation factor original data; an index calculation unit for mapping rotation factor original indexes into look-up table indexes of a rotation factor storage table and calculating sine component indexes and cosine component indexes; a folding judgment unit for judging whether the sine component indexes and the cosine component indexes exceed the index range of the rotation factor storage table; a data reading unit for respectively obtaining imaginary part readout values and real part readout values from the rotation factor storage table; and a sign correction unit for performing sign bit correction on the imaginary part readout values and the real part readout values to obtain real parts and imaginary parts of the rotation factors. The embodiment of the application reduces the storage resource occupation of the rotation factors, realizes the compatibility of a single rotation factor table to different point number FFTs, has high data reading precision and small hardware cost.

A hybrid-based discrete Fourier transform system and method based on FPGA includes: a parameter configuration module, a controller, a twitch factor generator, a hybrid-based butterfly calculation module, and a memory module. This invention achieves real-time generation of twitch factors and flexible operand retrieval through a unified parameter configuration module, a centralized controller, a universal twitch factor generator, and multi-level hybrid-based butterfly calculation units, combined with a ping-pong storage structure. It can efficiently support different hybrid-based DFT calculation processes without relying on a large-scale twitch factor lookup table, thereby effectively reducing hardware resource consumption and improving system versatility.

The invention provides an ML-DSA-oriented low-resource number-theory transformation acceleration system and method.The system comprises a control addressing module, a first storage module, a second storage module and an operation module, and a first storage unit and a second storage unit in the storage module are both used for storing coefficients of polynomials; the third storage unit and the fourth storage unit are used for storing twiddle factors and inverse twiddle factors. The addressing module is controlled to determine a plurality of target coefficient addresses based on the current operation mode according to the current operation round and the current operation count, and determine a plurality of target twiddle factor addresses. And a first operation unit and a second operation unit in the operation module respectively read the coefficient and the twiddle factor, operate the read coefficient, and store the operation result to each target coefficient address. The addressing method is simple, the arithmetic unit can access multiple coefficients at a time, and the read-write efficiency is high.

Provided in the embodiments of the present application are a data processing method and a related apparatus. In the present application, a matrix multiplication operation is performed on a rotation factor matrix and an input signal by means of cube units, so as to accelerate in combination with the cube units a fast Fourier transform (FFT) operation performed on the input signal. The method comprises: on the basis of the length of a first input signal, generating a rotation factor matrix, wherein the rotation factor matrix comprises a plurality of rotation factors, which are used for performing an FFT operation on the first input signal; and performing a matrix multiplication operation on the rotation factor matrix and the first input signal, so as to obtain a first matrix-product matrix, wherein the first matrix-product matrix comprises a result of performing the FFT operation on the first input signal.

The embodiment of the application discloses a method, device and computing equipment for performing FFT calculation, and belongs to the technical field of computers. The method comprises the following steps: dividing the FFT calculation into multiple calculation stages based on the length of a data sequence to be calculated; for at least one target calculation stage in the multiple calculation stages, determining a merging matrix corresponding to the target calculation stage based on a base corresponding to each of the multiple calculation stages, and the execution order of the target calculation stage in the multiple calculation stages, wherein the merging matrix is the product of a discrete Fourier transform (DFT) coefficient matrix in the target calculation stage and a rotation factor; and determining the product of the input sequence of the target calculation stage and the merging matrix as the output sequence of the target calculation stage when the target calculation stage is executed. According to the application, the calculation amount corresponding to the calculation stage can be reduced, and the execution efficiency of the FFT calculation can be improved.

The application relates to a multi-dimensional fast Fourier transform acceleration method based on matrix operation in the field of computing power optimization. The method comprises the following steps: S1, applying for a computing resource, copying computing data to device global memory on the host side, generating a DFT matrix and an input data matrix; S2, reading the DFT matrix data and the input data matrix from the global memory to a register and a shared memory; S3, using multi-thread parallelism to complete the calculation task of matrix element multiplication of the input data matrix and a rotation factor matrix, and obtaining intermediate calculation result data; S4, calling a matrix operation unit to perform matrix multiplication on the intermediate calculation result data obtained in the step S3 and the DFT matrix, and outputting final calculation result data; and S5, copying the final calculation result data from the device global memory to the host memory on the host side, and releasing the computing resource. The application adopts matrix operation to calculate multi-dimensional FFT, and uses a high-performance matrix operation unit of a GPU to accelerate the calculation, so that the FFT calculation efficiency on the GPU is improved.

The invention provides a dynamic frequency tracking method based on a variable twiddle factor and electric energy metering equipment, and belongs to the technical field of signal analysis, and the method comprises the steps: obtaining the voltage and current of a power grid; processing the power grid signal based on a target transfer function so as to perform dynamic frequency tracking on the power grid signal; wherein the determination process of the target transfer function comprises the following steps: extracting the fundamental frequency of the power grid signal; based on the SDFT, extracting a fundamental wave frequency corresponding to the specified subharmonic to adjust a twiddle factor of a transfer function in the SDFT to obtain an adjusted twiddle factor; and constructing a target transfer function based on the adjusted twiddle factor. According to the dynamic frequency tracking method based on the variable twiddle factor and the electric energy metering equipment, the power grid frequency can be accurately tracked, and the analysis precision of fundamental wave and harmonic wave amplitudes is improved.

Embodiments of the present specification provide a method for storing or reading a rotation factor in a target transform. The target transform is a discrete transform or its inverse transform that transforms an input coefficient sequence into an output coefficient sequence based on a rotation factor. The method includes determining a target rotation factor to be stored, whose power is a result of a multiplication of a first factor of a first number of bits and a second factor of a second number of bits modulo a target value; and storing the target rotation factor by a two-level storage manner, the two-level storage manner including storing the target rotation factor at a first address in a rotation factor storage, wherein the rotation factor storage includes a first number of first storage units, the first number being a number of different modulo multiplication results generated by the first factor of the first number of bits and the second factor of the second number of bits; and storing an index value pointing to the first address at a second address in an index storage, wherein the index storage includes a target value of second storage units, the second address corresponding to the power of the target rotation factor; and the target value is greater than the first number.

The invention is applicable to the field of digital signal processing, and discloses an FFT (Fast Fourier Transform) calculation method, system, equipment and medium based on CORDIC (Coordinated Rotation Digital Integrated Circuit) of an angle precoding circumference system, the method comprises the following steps: acquiring an input angle to be calculated, and obtaining a vector and a residual angle by inquiring a predefined distribution table; based on residual angle block coding, obtaining a non-scaling twiddle factor corresponding to the coded angle through Taylor expansion, and rotating the vector to obtain a rotated vector and a micro angle; obtaining a trigonometric function value corresponding to the input angle by combining approximate processing with multiply-add operation based on the rotated vector and the micro angle; and according to the received sampling sequence data, applying the trigonometric function value as a twiddle factor, and executing complex multiplication and data exchange in each level of butterfly operation unit of the FFT to obtain FFT spectrum data. The CORDIC algorithm with few iterations, high calculation precision and low hardware resource consumption is realized, and the FFT calculation efficiency and performance are improved.

Embodiments of the present application provide a system, a device, and a method for a two-variable number theoretic transform. A matrix having the two-variable number theoretic transform may be applied to a matrix having dimensions a × b, where a = 2x and b = 2y for X ≥ y. The two-variable number theoretic transform includes two stages: decomposition by rows and row-wise fast Fourier transforms (FFTs), with twiddle factors computed based on a first root α satisfying αb = -1 mod p; and decomposition by columns and column-wise FFTs, with twiddle factors computed based on a second root β satisfying β2a = 2 or - 2 mod p. Since each of the stages uses a different root, the number of twiddle factors is reduced.

The invention is suitable for the technical field of electric energy metering, and relates to a rapid analysis method of electric power signal harmonic waves, a medium and a terminal. A linear convolution system of a sampling value sequence and a discrete Fourier transform phase twiddle factor is constructed by utilizing the periodicity of the discrete Fourier transform phase twiddle factor; discrete Fourier transform of a sampling value sequence is expressed as a digital filtering form, and finally harmonic spectrum analysis is completed through recursive iterative calculation only including real number operation and a difference equation form. The method effectively solves the problems of spectrum leakage and fence effect caused by asynchronous sampling and non-integer period truncation during fundamental wave / harmonic wave analysis, and has the advantages of high harmonic wave analysis accuracy and efficiency, low resource consumption and high real-time performance compared with the existing method.

Embodiments of the present application provide a data processing method and related device, which performs matrix multiplication operation on a twiddle factor matrix and an input signal by a cube unit to realize fast Fourier operation on the input signal combined with the cube unit acceleration. The method comprises: generating a twiddle factor matrix according to the length of a first input signal, the twiddle factor matrix comprising a plurality of twiddle factors used for fast Fourier transform (FFT) operation on the first input signal; performing matrix multiplication operation on the twiddle factor matrix and the first input signal to obtain a first matrix multiplication matrix, the first matrix multiplication matrix comprising the result of FFT operation on the first input signal.

This invention belongs to the field of FFT computation acceleration technology, specifically relating to an adaptive FFT operation processor module for handling large amounts of data, including an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT computation module, and a control module; the FFT computation module includes m-row radix-2 arrays arranged side-by-side. k The MDC module includes a data rearrangement unit comprising a read / write data storage module and a data preprocessing module. The read / write data storage module consists of multiple memories. The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffling units of varying depths. The twiddle factor storage module stores fixed constant twiddle factors and reuses them based on the number of calculation points. The address generation module uses a program counter to generate address sequences for data read / write. The control module controls the execution of FFT calculations and can adapt to different FFT calculation requirements. This improves the utilization rate of the butterfly operation unit and the overall computational throughput of the architecture.

A method for accelerating fast Fourier transform (FFT) based on field programmable gate array is provided. A sequence requiring N-point FFT is decomposed equally into 4 subsequences. The 4 subsequences are processed through 4 parallel FFT intellectual property (IP) cores. Finally, an arithmetic operation is performed on the processed data and twiddle factor data pre-stored in a memory to obtain a result of the N-point FFT of an original sequence. An FFT decomposition module, a twiddle factor storage module, and an operation processing module are provided. Through the processing method, a time delay consumed by an N-point FFT operation can be reduced, and excellent application value can be achieved in a high-speed digital signal processing system.

To provide a KR (Khatri-Rao) product extension radar signal processing device and a program for reducing the number of times of multiplication of a reception signal and a complex conjugate of the reception signal, reducing a memory amount of a matrix element of a covariance matrix, and facilitating mounting on built-in equipment.SOLUTION: The signal processing device calculates one of an upper triangular component and a lower triangular component including a diagonal component in the covariance matrix, performs Fourier transform on the reception signal of the first antenna arrangement to calculate a first target angular spectrum of every other sample, performs Fourier transform on the reception signal of the first antenna arrangement multiplied by a predetermined twiddle factor to calculate a second target angular spectrum of every other sample, and integrates the first target angular spectrum and the second target angular spectrum of every other sample to calculate a target angular spectrum in all samples.SELECTED DRAWING: Figure 6