54 results about "Twiddle factor" patented technology

The invention provides a high-speed NTT method and system based on GPU matrix-thread collaborative optimization. The method comprises the steps that an input twiddle factor is converted into a matrix form; transmitting the updated twiddle factor matrix and the input array to a graphics processor; according to the input array and the size of the twiddle factor matrix, the number of blocks in the grid and the number of threads included in each block are set, so that each block is responsible for the operation of multiplying one row by one column, and each thread in the block completes the operation of multiplying one pair of data in the corresponding row-by-column process to obtain a group of intermediate results; and obtaining output data corresponding to the block according to an intermediate result in the block, and sending the output data to a corresponding position of an output matrix to serve as a multiplication result. According to the method, NTT calculation is reconstructed into parallel matrix-vector operation, the maximum utilization of GPU calculation resources is realized through the combination of an efficient thread allocation strategy and an optimized memory access mode, and the calculation efficiency is remarkably improved.

Embodiments of the present application provide a system, a device, and a method for a two-variable number theoretic transform. A matrix having the two-variable number theoretic transform may be applied to a matrix having dimensions a×b, where a=2x and b=2y for x≥y. The two-variable number theoretic transform includes two stages: decomposition by rows and row-wise fast Fourier transforms (FFTs), with twiddle factors computed based on a first root α satisfying αb=−1 mod p; and decomposition by columns and column-wise FFTs, with twiddle factors computed based on a second root β satisfying β2a=2 or −2 mod p. Since each of the stages uses a different root, the number of twiddle factors is reduced.

Generally discussed herein are devices, systems, and methods for performing a number theoretic transform (NTT) / inverse NTT (INTT). A circuit for NTT / INTT can include a first butterfly operator circuit (BOC) that generates first and second output coefficients based on first and second polynomial coefficients and a twiddle factor, a second BOC that operates in parallel with the first BOC and generates third and fourth output coefficients based on third and fourth polynomial coefficients and the twiddle factor, a third BOC that operates in series with the first and second BOCs and generates fifth and sixth output coefficients based on the first and third output coefficients and a second twiddle factor, and a fourth BOC that operates in series with the first and second BOCs and in parallel with the third BOC and generates seventh and eighth output coefficients based on the second and fourth output coefficients and a third twiddle factor.

Fourier transform operations may be converted to matrix multiplications that may be like matrix multiplications in convolutions and can be executed by deep neural network (DNN) accelerators. A DNN accelerator may receive an input tensor representing an input signal of a Fourier transform operation. The input tensor may include activations arranged in one or more rows and one or more columns. The DNN accelerator may receive a weight tensor determined based on one or more twiddle factors of the Fourier transform operation. The DNN accelerator may perform two sequences of multiply-accumulate (MAC) operations. An MAC operation in the first sequence may be performed on the weight tensor and a row in the input tensor. An MAC operation in the second sequence may be performed on the weight tensor and a column in the input tensor. The outputs of the MAC operations may represent the Fourier transform of the input signal.

Generally discussed herein are devices, systems, and methods for performing a number theoretic transform (NTT) / inverse NTT (INTT). A circuit for NTT / INTT can include a first butterfly operator circuit (BOC) that generates first and second output coefficients based on first and second polynomial coefficients and a twiddle factor, a second BOC that operates in parallel with the first BOC and generates third and fourth output coefficients based on third and fourth polynomial coefficients and the twiddle factor, a third BOC that operates in series with the first and second BOCs and generates fifth and sixth output coefficients based on the first and third output coefficients and a second twiddle factor, and a fourth BOC that operates in series with the first and second BOCs and in parallel with the third BOC and generates seventh and eighth output coefficients based on the second and fourth output coefficients and a third twiddle factor.

The invention discloses a hardware acceleration method for a Fourier neural operator. The hardware acceleration method comprises the following steps: setting an FFT module and a DFT / NN module which are independent from each other on an FNO hardware accelerator; performing fast Fourier transform (FFT) calculation on the batch input data by using an FFT module; a DFT / NN module is utilized to execute discrete Fourier transform (DFT) calculation based on a Bluestein algorithm, and access mode parallel random access of twiddle factors is reconstructed into parallel rule access; in an FNO hardware accelerator, an FFT module or a DFT / NN module is adaptively selected as a unit for executing calculation based on static parameter analysis of input dimensions, transformation points and frequency cut-off output points, and corresponding operator fusion is executed based on a predefined operator fusion mode. The adaptive capacity of the FNO to different transformation points and dimension structures is enhanced, and effective unification of computing performance, hardware efficiency and application flexibility is achieved.

Embodiments disclosed in this application pertain to the field of computer technologies, and in particular, to a method for performing FFT, a processor, and a computing device. The method includes: A processor responds to an execution request of fast Fourier transform FFT calculation of an application, and decomposes the FFT calculation into a plurality of calculation stages. The processor sequentially executes the plurality of calculation stages, where when a target calculation stage is executed, a vector operation circuit performs rotation factor calculation, and a matrix operation circuit performs DFT calculation. After the execution of the plurality of calculation stages is completed, the processor determines an execution result of the FFT calculation based on an execution result of a last calculation stage, and returns the execution result to the application. vector operation circuit matrix operation circuit

The application relates to a low-complexity OCDM modulation and demodulation implementation method based on FPGA, and belongs to the technical field of electronic communication. The DFnT or IDFnT is split into twice rotation factor multiplication, FFT or IFFT transformation, phase and amplitude adjustment steps to realize OCDM modulation and demodulation. The IQ data module is used to input IQ data to be subjected to DFnT or IDFnT transformation; the first rotation factor multiplication module is used to multiply the first rotation factor after phase rotation with the input data; the FFT or IFFT module is used to perform FFT or IFFT transformation on the output result of the first rotation factor multiplication; then, the data is subjected to second rotation factor multiplication; finally, the phase and amplitude are adjusted to complete OCDM modulation or demodulation. The application provides an OCDM modulation and demodulation scheme based on FPGA, and the storage capacity is reduced under the condition of invariable complexity.

The invention discloses a twiddle factor table generation method for number theory transformation, which is mainly based on decomposition of a polynomial on a finite field and comprises the steps of key data generation, polynomial decomposition and data selection, inverse number theory transformation data calculation, Montgomery domain conversion and the like. The method comprises the following steps of: decomposing five types of polynomials of an original three-term expression, square difference, square sum, cubic difference and cubic sum according to levels and a specific sequence, then selecting negative values of constant term parts of partial polynomials to form a rotation factor table of positive number theory transformation, and then calculating a rotation factor table used by inverse number theory transformation according to the rotation factor table of the positive number theory transformation, and finally, converting the twiddle factor table data to the Montgomery domain to obtain a final twiddle factor table. According to the technical scheme, the implementation efficiency of number theory transformation can be remarkably improved, and finer granularity and a wider range are provided for selection of lattice-based password parameters; and the efficiency of anti-quantum encryption, decryption and signature algorithms is improved.

The invention discloses a QR decomposition matrix inversion optimization method and system. The method comprises the following steps: receiving signal data, and carrying out FFT (Fast Fourier Transform) preprocessing and data downsampling; double-buffer optimization parallel processing is adopted, and FFT signal data are stored based on a double-buffer FIFO data storage structure; calculating a covariance matrix of the FFT signal data; adopting Givens rotation to gradually eliminate off-diagonal elements of the covariance matrix, carrying out Givens rotation calculation, and adopting an optimized CORDIC calculation method to calculate a Givens rotation factor; a calculation process of Givens rotation is accelerated by adopting a Systolic array architecture; and outputting a final QR decomposition result according to a Givens rotation calculation result. According to the method, the data flow is optimized, the calculation throughput rate is improved, hardware resource occupation is reduced, a low-power-consumption and high-performance hardware implementation scheme is provided for efficient matrix calculation, and the method has wide engineering application value.

This invention relates to a method and apparatus for resolving velocity ambiguity based on constant frequency assistance. The method includes the following steps: a radar sequentially transmits a constant frequency band signal and a linear continuously modulated pulse train, and acquires the radar echo signal; both the constant frequency band echo signal and the sawtooth band echo signal are mixed to obtain a constant frequency band intermediate frequency signal and a sawtooth band intermediate frequency signal; the constant frequency band intermediate frequency signal is processed by a fast Fourier transform to obtain a target true velocity estimate; the sawtooth band intermediate frequency signal is sequentially processed by a two-dimensional fast Fourier transform, a two-dimensional constant false alarm rate (CFAR) processing, and a centroid condensation processing to obtain a target range velocity estimate; based on a velocity matching method using a Fourier rotation factor, the target true velocity estimate is matched with the target range velocity estimate to obtain the true velocity of all targets. This method not only resolves velocity ambiguity but also improves velocity accuracy, offering advantages such as high velocity measurement accuracy, high real-time performance, and simplicity.

The invention discloses a sampling frequency offset phase compensation method and device under QPSK modulation, and relates to the technical field of phase compensation methods, and the method comprises the steps: collecting each load frame, and carrying out the QPSK modulation of the load frames; configuring a corresponding phase twiddle factor for each OFDM symbol based on the QPSK modulation of each load frame; in the calculation process of the phase twiddle factor, determining a corresponding phase compensation value based on the rotation compensation of each subcarrier until all subcarriers in each load frame have corresponding phase compensation values; according to the method, corresponding diversity combining is triggered according to each OFDM symbol, at the moment, a sampling frequency offset estimation value does not need to be directly estimated, approximate sampling frequency offset phase deflection information is obtained after multiple pieces of subcarrier information are combined and noise is reduced, correction is carried out according to the approximate sampling frequency offset phase deflection information, and a good correction effect can also be obtained under the low signal-to-noise ratio. Phase compensation is carried out on corresponding data before demodulation and decoding, and the receiving performance is improved.

The invention discloses a frequency estimation method and device for FMCW-Lidar, and relates to the technical field of signal processing, and the method comprises the following steps: carrying out the N-point FFT of a carrier frequency signal, and obtaining a user-defined signal based on a twiddle factor; splitting the custom signal into a real part and an imaginary part, and obtaining a real part expression and an imaginary part expression; obtaining a real part ratio factor and an imaginary part ratio factor; based on the signal sampling frequency of the carrier frequency signal and the corresponding real part ratio factor and imaginary part ratio factor, calculating to obtain an estimated frequency of the carrier frequency signal; and obtaining an accurate estimation frequency of the carrier frequency signal based on the estimation frequency of the carrier frequency signal and the signal sampling frequency of the carrier frequency signal. According to the invention, the carrier frequency signal is processed based on the preset data processing flow and the calculation flow, and then estimation and accurate estimation are carried out, so that the real-time performance of the FMCW-Lidar frequency estimation algorithm is effectively improved.

Provided is an NTT acceleration chip, including: a twiddle factor computing module, including a plurality of pre-computing units and a plurality of real-time computing units, where the plurality of pre-computing units is configured to compute several initial lines of twiddle factors and an inter-line step factor in parallel by using a primitive root of unity; and the plurality of real-time computing units is configured to repeatedly and iteratively compute other lines of twiddle factors in parallel according to the inter-line step factor; a transposition module, including a plurality of transposition units, configured to perform transposition processing on an input sequence in parallel, to obtain a transposed sequence; and an NTT computing module, including a plurality of butterfly computing units, configured to perform a butterfly operation of orders and a point quantity in parallel according to the twiddle factors and the transposed sequence, to obtain an output sequence.

The application relates to an expandable distributed privacy protection FFT method and system based on secret sharing and MAC tags, which comprises the following steps: input original data is divided into multiple data shares by adopting a three-party replication secret sharing technology, a corresponding MAC tag is generated for each data share, and the secret sharing is performed to each participant cluster; each computing node in each participant cluster performs one-dimensional fast Fourier transform on each row of the held data share to obtain an intermediate matrix; a rotation factor is multiplied with the intermediate matrix to obtain a rotation matrix; each computing node divides the rotation matrix into multiple section shares in the column direction, and sends each section share to a corresponding group leader according to the serial number of the section share; the computing node calculates the fast Fourier transform in the column direction to obtain an output matrix, and a principal verifies the output matrix; while resisting malicious attacks, the communication complexity is reduced from O(M) to O(M / N), the MAC verification overhead is reduced to less than 8% of the total time consumption, and the expandability of the system is greatly improved.

The invention discloses a full-pipeline single-path delay feedback structure fast Fourier transform calculation unit capable of simply addressing twiddle factors, which comprises SDF modules at all levels, twiddle factor read-out modules corresponding to the SDF modules, and a three-real-number complex multiplier of a pipeline structure. According to the twiddle factor reading module provided by the invention, orderly input of twiddle factors can be realized only by using three either-or data selectors, a synchronous counter and a synchronous ROM (Read Only Memory) and depending on two control signals; although the three-real-number and complex-number multiplier of the pipeline structure sacrifices the data throughput, the power consumption is greatly reduced, and meanwhile, it is ensured that the proposed FFT calculation unit is of a full pipeline architecture, so that no interval exists between two adjacent continuous output periods.

The application provides an application method and system of a specific accelerator and the specific accelerator, the first processor comprises the specific accelerator, the specific accelerator is an FFT accelerator, the method comprises the following steps: obtaining instruction information, the instruction information is an instruction meeting a custom coding rule of a reduced instruction set; obtaining a required sampling point number and to-be-processed data based on the instruction information; selecting a delay feedback module in a preset delay feedback module set of the specific accelerator according to the sampling point number, and selecting a target twiddle factor storage unit in a twiddle factor storage module; enabling at least two delay feedback modules and the target twiddle factor storage unit to obtain a target accelerator circuit; inputting the to-be-processed data into the target accelerator circuit to obtain a calculation result. Since the specific accelerator can support custom instructions to perform calculation of different sampling point numbers, instruction extension is realized, the instruction extension matches the structure extension of the specific accelerator, and the structural form of the specific accelerator is improved.

The invention provides an FFT (Fast Fourier Transform) data stream acceleration method based on RISC-V. The method comprises the following steps: configuring a vector control state register according to an FFT point number; a data loading strategy is selected according to whether the point number exceeds a threshold value or not, small-scale data are loaded to a vector register set at a time, and large-scale data are loaded multiple times after being split; parallel operation is started through a vector butterfly operation instruction, operands and twiddle factors are read according to position information of a register and the instruction, and the operands and the twiddle factors are sequentially written back after operation is completed; and finally, storing the result in a memory, and processing according to a loading strategy: directly outputting the result in one-time loading, and carrying out data rearrangement and iterative operation in multiple loading until all FFT levels are completed. The invention also provides an FFT (Fast Fourier Transform) data stream acceleration device based on the RISC-V. Therefore, vectorized FFT operation is carried out based on the extended instruction set of the RISC-V, data are rearranged in the processor based on the thought of the data stream, and the operation efficiency when the ASIP carries out FFT is improved.

The present disclosure provides a method for executing a cryptographic operation including a NTT computation that transforms a polynomial with N coefficients from time-domain to frequency-domain. The NTT computation is divided into successive stages of butterfly operations that combine coefficients, starting from the N coefficients up to N transformed coefficients. During each stage, each butterfly combines a pair of coefficients among the N coefficients, using a NTT twiddle factor to progressively transform the pair of coefficients and uses a set of mask-related twiddle factors such. This set is based on the two input masks and on the output mask. The butterfly operations are grouped into blocks of at least two butterfly operations where all the butterfly operations within a same block have a same combination of masks in input and output at each stage of the NTT computation.

The embodiment of the invention relates to the field of network security design, in particular to a twiddle factor real-time generation method and device for fully homomorphic encryption. A specific embodiment of the method comprises the following steps: determining an initial twiddle factor set; determining a fully homomorphic encryption algorithm based on the initial twiddle factor set; determining first butterfly unit information based on a fully homomorphic encryption algorithm; determining first twiddle factor information based on a fully homomorphic encryption algorithm and the first butterfly unit information; updating the first butterfly unit information to generate second butterfly unit information; updating the first twiddle factor information based on a fully homomorphic encryption algorithm and the second butterfly unit information to generate second twiddle factor information; and updating the second twiddle factor information to generate target twiddle factor information. According to the embodiment, the storage amount of twiddle factors can be compressed, the storage space is saved, and the problem that the overall rate is reduced due to transmission of a large number of twiddle factors is solved.

The invention relates to a fast Fourier transform method and device for improving the utilization rate of a storage space. The fast Fourier transform method comprises the following steps of: 1, writing input data into the storage space in an address close arrangement form; 2, calculating a twiddle factor, and storing the twiddle factor into a storage space; 3, FFT input data processing is carried out, specifically, step 31, FFT input data is subjected to data inverted-order storage; step 32, performing data operation, specifically, step 321, expanding the twiddle factors obtained in the step 2 to obtain a twiddle factor complete set; and step 322, performing butterfly operation, and obtaining output Fourier transform data after continuous traversal is completed. According to the method, the storage resources required by the input data and the output data are reduced by converting the floating point data format of the input data and adapting the adder and the multiplier of the computing resources; and the aim of saving memory resources is fulfilled on the premise of ensuring the calculation efficiency.

The embodiments disclosed in the present application belong to the technical field of computers, particularly relate to a method for executing a fast NTT, an apparatus and a computer device. The method is executed by a processor, and the method comprises: a processor receiving an execution instruction for a fast NTT sent by an application, and acquiring a data sequence on which the fast NTT will be executed; on the basis of a length value of the data sequence, determining in a candidate radix set radixes respectively corresponding to a plurality of calculation stages comprised in the fast NTT, the candidate radix set comprising a plurality of candidate radixes, and the value of each candidate radix being greater than 2 and being an integer power of 2; acquiring a twiddle factor corresponding to each calculation stage; and, on the basis of the data sequence and the twiddle factor corresponding to each calculation stage, successively executing the calculation stages so as to obtain a result of executing the fast NTT. Using the present application can improve the efficiency of executing fast NTTs.

Embodiments of the present specification provide a method for constructing a processing circuit for a target transform. The target transform is a discrete transform or its inverse transform that transforms an input coefficient sequence into an output coefficient sequence based on a rotation factor. The method includes, for a K-point input coefficient sequence to be processed, determining a plurality of candidate decomposition points corresponding to a k-bit coefficient index. Then, starting from a low-bit decomposition point, for each candidate decomposition point, determining the minimum storage cost under each candidate decomposition point according to a decomposition cost evaluation function through recursive index bit number decomposition for several levels, so as to determine a target decomposition mode of the k-bit coefficient index with the minimum storage cost. The decomposition cost evaluation function limits the storage cost to include the cost of a (n-p)th order first transform, the cost of a pth order second transform, and the local cost for inter-level rotation factor multiplication. According to the target decomposition mode, a corresponding memory for the rotation factor is allocated to form a processing circuit.

This application provides one or more embodiments of a signal processing method and related device based on a memristor array. The method includes: mapping an input signal to an input voltage signal, and inputting the input voltage signal to the mapped memristor array; the mapped memristor array obtaining an output current based on the input voltage signal; wherein the mapped memristor array is obtained through the following steps: determining the discrete Fourier transform expression X = W for the signal conversion. N x, where x represents the input signal, X represents the output signal, and W N The rotation factor is represented; it is converted into a complex matrix-vector multiplication expression; Re() represents the real part of the complex number, and Im() represents the imaginary part of the complex number; the operation matrix is ​​mapped to the memristor array to obtain the mapped memristor array. This application can improve the computational efficiency of the DFT or IDFT module and further improve the efficiency of signal processing.

The application discloses a hardware acceleration method for a Fourier neural operator, and sets up independent FFT modules and DFT / NN modules in an FNO hardware accelerator; the FFT modules are used to perform fast Fourier transform (FFT) calculation on batch input data; the DFT / NN modules are used to perform discrete Fourier transform (DFT) calculation based on a Bluestein algorithm, and a parallel random access mode of a rotation factor is reconstructed into a parallel regular access mode; in the FNO hardware accelerator, based on static parameter analysis on input dimensions, transform point numbers and frequency truncated output point numbers, the FFT modules or the DFT / NN modules are adaptively selected as units for performing calculation, and corresponding operator fusion is performed based on a predefined operator fusion mode. The application enhances the adaptation capability of the FNO to different transform point numbers and dimension structures, and effectively unifies the calculation performance, hardware efficiency and application flexibility.

A non-volatile memory device is configured for in-memory computation of discrete Fourier transformations and their inverses. The real and imaginary components of the twiddle factors are stored as conductance values of memory cells in non-volatile memory arrays having a cross-point structure. The real and imaginary components of inputs are encoded as word line voltages applied to the arrays. Positive and negative valued components of the twiddle factors are stored separately and positive and negative of the inputs are separately applied to the arrays. Real and imaginary parts of the outputs for the discrete Fourier transformation are determined from combinations of the output currents from the arrays.

The invention provides a multi-core DSP-FFT (Digital Signal Processor-Fast Fourier Transform) processing mode applied to radar signal processing, which comprises the following steps of: acquiring data to be processed as a data matrix with the length of M * 2N, M and N being natural numbers; selecting short data FFT operation and long data FFT operation according to the length of the data to be processed; the short data FFT operation comprises the steps of firstly configuring parameters, then carrying out M / 8 cycles, and carrying out 2N-point FFT calculation by 8 CPUs in each cycle; the long data FFT operation comprises the steps that parameter configuration is carried out firstly, then M times of circulation is carried out, in each time of circulation, eight CPUs finish splitting FFT operation of 2N points together, then complex multiplication is carried out on splitting FFT operation results and twiddle factors, and then the CPUs carry out configuration distribution, calculation writing and FFT calculation respectively; according to the method, the DSP calculation process of the large-point FFT is split by adopting the principle of FFT operation, multiple cores of the DSP are fully utilized to respectively distribute, calculate and cache resources, and the overall performance of an algorithm design assembly line is improved.

The application relates to a rotation factor storage method, a reading method and a hardware accelerator for FFT operation. The hardware accelerator comprises a rotation factor storage unit for storing sine components or cosine components in rotation factor original data; an index calculation unit for mapping rotation factor original indexes into look-up table indexes of a rotation factor storage table and calculating sine component indexes and cosine component indexes; a folding judgment unit for judging whether the sine component indexes and the cosine component indexes exceed the index range of the rotation factor storage table; a data reading unit for respectively obtaining imaginary part readout values and real part readout values from the rotation factor storage table; and a sign correction unit for performing sign bit correction on the imaginary part readout values and the real part readout values to obtain real parts and imaginary parts of the rotation factors. The embodiment of the application reduces the storage resource occupation of the rotation factors, realizes the compatibility of a single rotation factor table to different point number FFTs, has high data reading precision and small hardware cost.

The invention relates to the technical field of ultra-wideband signal processing, in particular to an ultra-wideband low-delay signal processing method based on a channelization technology, and the method comprises the steps: obtaining an input digital signal, carrying out the multiphase decomposition of the input digital signal, and obtaining K multiphase components; selecting a prototype low-pass filter, and deriving K multi-phase branch filters from the coefficient of the prototype low-pass filter according to the total number of channels and a preset interpolation factor; performing filtering operation on the K corresponding multi-phase components through K multi-phase branch filters, and performing K-point inverse discrete Fourier transform operation on the obtained K filtered component sets to obtain K transformation results; and respectively multiplying the K conversion results by corresponding twiddle factors to carry out phase correction, and outputting K sub-channel signals after phase correction. According to the invention, a multi-phase filtering structure is adopted, and filtering is carried out after extraction, so that the operand and hardware resource consumption are remarkably reduced, and the channelization processing efficiency of the ultra-wideband signal is greatly improved.

The application discloses a kind of super large point number FFT fast processing method, it is related to digital signal fast processing field, including the following steps: first, zero padding operation is carried out to original sampling signal data to the total length of sequence meets the integer multiple of M1 point;Then, the data after zero padding operation is segmented, and the input super large point number sequence is divided into L length M1 point sub-sequences, then, the sub-sequences are calculated with M1 point FFT, and high-base FFT algorithm architecture is used for iterative calculation;Finally, the phase correction of FFT result is realized by multiplying the specific rotation factor with the FFT calculation result of sub-sequence, the phase-corrected sub-FFT result is combined and spliced according to a specific weighting method, to ensure that the composition of each frequency point is correctly adjusted, and the FFT result of original data sequence is obtained.The application can reduce the algorithm complexity while improving the calculation efficiency of super large point number FFT.