12 results about "Twiddle factor" patented technology

Provided is an NTT acceleration chip, including: a twiddle factor computing module, including a plurality of pre-computing units and a plurality of real-time computing units, where the plurality of pre-computing units is configured to compute several initial lines of twiddle factors and an inter-line step factor in parallel by using a primitive root of unity; and the plurality of real-time computing units is configured to repeatedly and iteratively compute other lines of twiddle factors in parallel according to the inter-line step factor; a transposition module, including a plurality of transposition units, configured to perform transposition processing on an input sequence in parallel, to obtain a transposed sequence; and an NTT computing module, including a plurality of butterfly computing units, configured to perform a butterfly operation of orders and a point quantity in parallel according to the twiddle factors and the transposed sequence, to obtain an output sequence.

The application relates to an expandable distributed privacy protection FFT method and system based on secret sharing and MAC tags, which comprises the following steps: input original data is divided into multiple data shares by adopting a three-party replication secret sharing technology, a corresponding MAC tag is generated for each data share, and the secret sharing is performed to each participant cluster; each computing node in each participant cluster performs one-dimensional fast Fourier transform on each row of the held data share to obtain an intermediate matrix; a rotation factor is multiplied with the intermediate matrix to obtain a rotation matrix; each computing node divides the rotation matrix into multiple section shares in the column direction, and sends each section share to a corresponding group leader according to the serial number of the section share; the computing node calculates the fast Fourier transform in the column direction to obtain an output matrix, and a principal verifies the output matrix; while resisting malicious attacks, the communication complexity is reduced from O(M) to O(M / N), the MAC verification overhead is reduced to less than 8% of the total time consumption, and the expandability of the system is greatly improved.

The application provides an application method and system of a specific accelerator and the specific accelerator, the first processor comprises the specific accelerator, the specific accelerator is an FFT accelerator, the method comprises the following steps: obtaining instruction information, the instruction information is an instruction meeting a custom coding rule of a reduced instruction set; obtaining a required sampling point number and to-be-processed data based on the instruction information; selecting a delay feedback module in a preset delay feedback module set of the specific accelerator according to the sampling point number, and selecting a target twiddle factor storage unit in a twiddle factor storage module; enabling at least two delay feedback modules and the target twiddle factor storage unit to obtain a target accelerator circuit; inputting the to-be-processed data into the target accelerator circuit to obtain a calculation result. Since the specific accelerator can support custom instructions to perform calculation of different sampling point numbers, instruction extension is realized, the instruction extension matches the structure extension of the specific accelerator, and the structural form of the specific accelerator is improved.

The application discloses a hardware acceleration method for a Fourier neural operator, and sets up independent FFT modules and DFT / NN modules in an FNO hardware accelerator; the FFT modules are used to perform fast Fourier transform (FFT) calculation on batch input data; the DFT / NN modules are used to perform discrete Fourier transform (DFT) calculation based on a Bluestein algorithm, and a parallel random access mode of a rotation factor is reconstructed into a parallel regular access mode; in the FNO hardware accelerator, based on static parameter analysis on input dimensions, transform point numbers and frequency truncated output point numbers, the FFT modules or the DFT / NN modules are adaptively selected as units for performing calculation, and corresponding operator fusion is performed based on a predefined operator fusion mode. The application enhances the adaptation capability of the FNO to different transform point numbers and dimension structures, and effectively unifies the calculation performance, hardware efficiency and application flexibility.

A non-volatile memory device is configured for in-memory computation of discrete Fourier transformations and their inverses. The real and imaginary components of the twiddle factors are stored as conductance values of memory cells in non-volatile memory arrays having a cross-point structure. The real and imaginary components of inputs are encoded as word line voltages applied to the arrays. Positive and negative valued components of the twiddle factors are stored separately and positive and negative of the inputs are separately applied to the arrays. Real and imaginary parts of the outputs for the discrete Fourier transformation are determined from combinations of the output currents from the arrays.

The application relates to a rotation factor storage method, a reading method and a hardware accelerator for FFT operation. The hardware accelerator comprises a rotation factor storage unit for storing sine components or cosine components in rotation factor original data; an index calculation unit for mapping rotation factor original indexes into look-up table indexes of a rotation factor storage table and calculating sine component indexes and cosine component indexes; a folding judgment unit for judging whether the sine component indexes and the cosine component indexes exceed the index range of the rotation factor storage table; a data reading unit for respectively obtaining imaginary part readout values and real part readout values from the rotation factor storage table; and a sign correction unit for performing sign bit correction on the imaginary part readout values and the real part readout values to obtain real parts and imaginary parts of the rotation factors. The embodiment of the application reduces the storage resource occupation of the rotation factors, realizes the compatibility of a single rotation factor table to different point number FFTs, has high data reading precision and small hardware cost.

A hybrid-based discrete Fourier transform system and method based on FPGA includes: a parameter configuration module, a controller, a twitch factor generator, a hybrid-based butterfly calculation module, and a memory module. This invention achieves real-time generation of twitch factors and flexible operand retrieval through a unified parameter configuration module, a centralized controller, a universal twitch factor generator, and multi-level hybrid-based butterfly calculation units, combined with a ping-pong storage structure. It can efficiently support different hybrid-based DFT calculation processes without relying on a large-scale twitch factor lookup table, thereby effectively reducing hardware resource consumption and improving system versatility.

Provided in the embodiments of the present application are a data processing method and a related apparatus. In the present application, a matrix multiplication operation is performed on a rotation factor matrix and an input signal by means of cube units, so as to accelerate in combination with the cube units a fast Fourier transform (FFT) operation performed on the input signal. The method comprises: on the basis of the length of a first input signal, generating a rotation factor matrix, wherein the rotation factor matrix comprises a plurality of rotation factors, which are used for performing an FFT operation on the first input signal; and performing a matrix multiplication operation on the rotation factor matrix and the first input signal, so as to obtain a first matrix-product matrix, wherein the first matrix-product matrix comprises a result of performing the FFT operation on the first input signal.

The application relates to a multi-dimensional fast Fourier transform acceleration method based on matrix operation in the field of computing power optimization. The method comprises the following steps: S1, applying for a computing resource, copying computing data to device global memory on the host side, generating a DFT matrix and an input data matrix; S2, reading the DFT matrix data and the input data matrix from the global memory to a register and a shared memory; S3, using multi-thread parallelism to complete the calculation task of matrix element multiplication of the input data matrix and a rotation factor matrix, and obtaining intermediate calculation result data; S4, calling a matrix operation unit to perform matrix multiplication on the intermediate calculation result data obtained in the step S3 and the DFT matrix, and outputting final calculation result data; and S5, copying the final calculation result data from the device global memory to the host memory on the host side, and releasing the computing resource. The application adopts matrix operation to calculate multi-dimensional FFT, and uses a high-performance matrix operation unit of a GPU to accelerate the calculation, so that the FFT calculation efficiency on the GPU is improved.

Embodiments of the present application provide a data processing method and related device, which performs matrix multiplication operation on a twiddle factor matrix and an input signal by a cube unit to realize fast Fourier operation on the input signal combined with the cube unit acceleration. The method comprises: generating a twiddle factor matrix according to the length of a first input signal, the twiddle factor matrix comprising a plurality of twiddle factors used for fast Fourier transform (FFT) operation on the first input signal; performing matrix multiplication operation on the twiddle factor matrix and the first input signal to obtain a first matrix multiplication matrix, the first matrix multiplication matrix comprising the result of FFT operation on the first input signal.

This invention belongs to the field of FFT computation acceleration technology, specifically relating to an adaptive FFT operation processor module for handling large amounts of data, including an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT computation module, and a control module; the FFT computation module includes m-row radix-2 arrays arranged side-by-side. k The MDC module includes a data rearrangement unit comprising a read / write data storage module and a data preprocessing module. The read / write data storage module consists of multiple memories. The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffling units of varying depths. The twiddle factor storage module stores fixed constant twiddle factors and reuses them based on the number of calculation points. The address generation module uses a program counter to generate address sequences for data read / write. The control module controls the execution of FFT calculations and can adapt to different FFT calculation requirements. This improves the utilization rate of the butterfly operation unit and the overall computational throughput of the architecture.

A method for accelerating fast Fourier transform (FFT) based on field programmable gate array is provided. A sequence requiring N-point FFT is decomposed equally into 4 subsequences. The 4 subsequences are processed through 4 parallel FFT intellectual property (IP) cores. Finally, an arithmetic operation is performed on the processed data and twiddle factor data pre-stored in a memory to obtain a result of the N-point FFT of an original sequence. An FFT decomposition module, a twiddle factor storage module, and an operation processing module are provided. Through the processing method, a time delay consumed by an N-point FFT operation can be reduced, and excellent application value can be achieved in a high-speed digital signal processing system.