Point-variable assembly line FFT processor

Abstract

The invention provides a pipeline FFT processor variable in the number of points, which comprises a first 1024-point variable FFT processing module, a twiddle-factor processing module, a second 1024-point variable FFT processing module and a selection-control module, wherein the four modules and an intermediate data storage module outside the processor jointly complete FFT two-dimensional processing large in the number of points; each 1024-point variable FFT processing module comprises a first 32-point variable FFT processing sub-module, a second 32-point variable FFT processing sub-module, a twiddle-factor processing sub-module, an intermediate data storage sub-module and a selection-control sub-module; variable-point FFT operation is implemented through the 32-point variable FFT processing sub-modules; the twiddle-factor processing module generates and multiplies intermediate twiddle factors by the result of FFT operation; and the selection-control module realizes control over a whole chip. The processor is suitable to be realized in single-chip FPGA or ASIC, and can simultaneously obtain high speed, low power consumption, high precision and other characteristics.

Description

technical field [0001] The invention belongs to the technical field of signal processing, and relates to a signal processor, in particular to an ultra-long variable-point number pipeline FFT processor, which can be applied to various input sequences such as communications or electronic warfare, where the length of the input sequence is variable in real time and the chip area is constrained. higher system. Background technique [0002] In electronic reconnaissance, radar signals cover a wide frequency range. In order to be able to identify different radar signals, electronic warfare receivers must have high frequency resolution over a wide bandwidth. The discrete Fourier transform (DFT) theory states that when using DFT for spectral analysis, the frequency resolution is equal to f s / N, where f s is the sampling frequency, and N is the total number of data points. Therefore, in order to enable the electronic warfare receiver to achieve a higher frequency resolution, the FF...

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Problems solved by technology

However, it also has its shortcomings: the computing power of a single DSP chip is limited, and it is not suitable for realizing the FFT of super long points; multiple DSP chips can be used for parallel computing, but this solution increases the complexity of the design and consumes a lot of power; The reverse order processing also takes a lot of time of the processor; due to the limited bandwidth of the DSP chip, the input and output of data may become the bottleneck of its high-speed operation

In the literature "A pipeline processor for mixed-size FFTs" (Sayegh, S.I.; Signal Processing, IEEE Trans on, 1992, Vol.40(8): 1892-1900.) A pipelined structure is proposed, which can calculate different points at the same time The disadvantage of FFT is that when the number of points is large, the circuit scale is too large

In the literature "Variable 2 n Design and Implementation of Point Pipeline FFT Processor" (Gao Zhenbin, Chen He. Journal of Beijing Institute of Technology, Issue 03, 2005) mentioned a method that can continuously calculate 2 n A pipeline structure processor for FFT of complex number sequences, but it uses traditional cascading method to realize pipeline FFT processing, which takes up a lot of storage resources and is difficult to implement in a single chip

In the document "A pipelined memory-efficient architecture for ultra-long variable-size FFT processors" (Chen He; Wu Qiang; 2008 International Conference on Computer Science and Information Technology, 2008, p357-61) mentioned a continuous calculation 4 n The pipeline structure processor of point complex number sequence FFT, but it cannot perform arbitrary 2 n Pipeline Processing of Point Complex Sequence FFT

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