Quick Fourier transformation implementation device and method

A Fourier transform and fast technology, applied in the field of fast Fourier transform implementation devices, can solve the problems of long operation cycle, low maximum operating frequency, and large storage space, so as to increase the maximum operating frequency, simplify the circuit, reduce The effect of storage space

Inactive Publication Date: 2014-08-06
COMMUNICATION UNIVERSITY OF CHINA
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Problems solved by technology

[0005] In view of this, the present invention provides a device and method for implementing fast Fourier transform, which are used to solve the problems

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  • Quick Fourier transformation implementation device and method
  • Quick Fourier transformation implementation device and method

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Embodiment Construction

[0053] The technical solutions of the present invention will be described clearly, accurately and completely in conjunction with the drawings in the embodiments of the present invention. The described embodiments are only a part of the embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0054] DFT and IDFT are a relationship between the time domain and the frequency domain of digital signals. At the same time, in the OFDM system, they are also an implementation algorithm for demodulation and modulation. In signal processing, with the convenience of processing, the data is often enlarged or reduced by a real multiplicative factor as a whole. The principle of DFT is as formula (1):

[0055] X ( k ) = X n = 0 N - 1 x ( n ) W ...

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Abstract

The invention relates to a quick Fourier transformation implementation device and method. The method comprises the steps that input data are stored to two data storage units divided into high addresses and low addresses, two complex numbers are read out from a read address generator, low address data are input into a register by delaying one period; according to a controller signal, the low address data and high address data are input into two input branches of a butterfly computation engine through a selector; at the same time, a twiddle factor is read out from a twiddle factor storage unit according to the address given by a twiddle factor address generator and input to the butterfly computation engine; in the output process, it is guaranteed that the address is written back to the data storage unit according to the delay address of a displacement register and the selector. In the address generator, a simple base value and a deviation value are used for obtaining a read address, and meanwhile the data of the two storage units are read for operation in turn. Compared with the prior art, the operation cycle is shortened, the highest operation frequency is increased, meanwhile, the twiddle factor storage unit is only 1/4 space of the needed twiddle factor, and thus design resources are saved.

Description

Technical field [0001] The invention relates to a fast Fourier transform realization device and method. The present invention particularly relates to the realization processing of orthogonal frequency division multiplexing modulation. Background technique [0002] Discrete Fourier Transform (DFT) and its inverse transform are an important part of digital signal processing, and an important method for digital signal conversion between time domain and frequency domain. Fast Fourier Transform (Fast Fourier Transform, FFT) is a fast calculation method for calculating DFT, especially N=2 K Point (where K is an integer) FFT is particularly widely used. [0003] Orthogonal Frequency Division Multiplexing (OFDM) technology has become a very competitive high-speed transmission in current and future wireless communication due to its high spectrum utilization, strong resistance to multipath interference and narrowband interference, and ease of mobile reception. technology. Now communicatio...

Claims

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Application Information

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IPC IPC(8): G06F17/14
Inventor 刘昌银张鹏万欣
Owner COMMUNICATION UNIVERSITY OF CHINA
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