The invention relates to the technical field of circuit design, in particular to a clock dynamic switching circuit. The circuit comprises a first AND gate, a second AND gate, a first clock enable signal line, a second clock enable signal line, a first feedback signal line, a second feedback signal line, a first clock signal line, a second clock signal line, a level synchronization circuit, a clockgating circuit and an OR gate circuit. The level synchronization circuit is used for synchronizing the first clock enable signal line and a first clock signal and synchronizing the second clock enable signal line and a second clock signal, and the clock gating circuit is used for controlling on-off of the clock signals. According to the circuit, the positive edge of the clock is used for triggering all devices in the circuit, a half-cycle path does not exist any more, the highest operation frequency of the circuit is improved, clock glitch is avoided through a feedback mechanism, and signalsoutput by the circuit are free of burrs.