Clock distribution network rapid design method

Abstract

The invention relates to a clock distribution network rapid design method. A clock network is divided into a first-stage clock network and a second-stage clock network, the first-stage clock network is driven by a first-stage clock network driving unit, the second-stage clock network is driven by a second-stage clock network driving unit, and the method comprises the following steps: adopting a time sequence priority layout, and obtaining the position of a trigger; dividing the trigger into a plurality of local areas by adopting a clustering algorithm according to the layout parameters, and establishing a second-stage clock network; dividing the second-stage clock network driving unit into a plurality of areas with uniform loads by adopting a clustering algorithm according to the layout parameters, and establishing a first-stage clock network; and winding the first-stage clock network and the second-stage clock network. The clock network delay can be reduced, and the clock network loadis reduced.

Description

technical field [0001] The invention relates to the technical field of sequential circuit design, in particular to a fast design method for a clock distribution network. Background technique [0002] In high-performance microprocessors, the clock network is a key component that affects processor performance and power consumption. A low-latency, low-skew clock network can effectively reduce timing overhead, and less on-chip skew and delay on the clock path can further improve processor performance. At the same time, the power consumption of the clock network accounts for more than 40% of the dynamic power consumption of the entire processor. Therefore, reducing the power consumption of the clock network helps to reduce the power consumption of the processor. Reducing the clock network is generally realized by reducing the load of the clock network. It can be seen that a low-latency, low-skew, and low-power clock network is crucial to realizing a high-energy-efficiency proc...

AI Technical Summary

Problems solved by technology

The former will affect the timing because the position of the flip-flop in the best timing situation needs to be changed, and the latter will increase the power consumption of the clock network due to the DC path problem caused by the multi-point drive. At the same time, a large number of clock grid lines occupy a large number of high-quality winding resources. thereby affecting design performance

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