29 results about "Clock network" patented technology

The invention provides a multi-mode fusion laser directional energy deposition real-time monitoring method and system, and belongs to the technical field of additive manufacturing. Comprising the steps that real-time data collection is conducted on a molten pool area in the laser directional energy deposition process through synchronous triggering of a multi-source sensor; a distributed clock network is constructed, environment influence parameters are collected in real time in combination with a working condition sensing unit, dynamic modeling and correction are conducted on asymmetric link delay in the clock synchronization process, and space-time alignment of multi-source sensor data is achieved; after the multi-source sensor data subjected to space-time alignment is preprocessed, data-level fusion, feature-level fusion and decision-level fusion are performed in sequence. The state of the molten pool can be accurately monitored in real time, and the quality and stability of the laser directional energy deposition process are improved.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

Various embodiments provide for assigning portions of a net based on one or more non-default design rules, which may be part of electronic design automation (EDA). For example, a net of a circuit design can be a clock network, and the assigning can comprise a layer assignment process, a track assignment process, or both. Additionally, various embodiments described herein can permit a plurality of non-default design rules to be applied to a single net of a circuit design.

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

A state estimation device and program capable of achieving high-precision time synchronization of a group of clocks. To provide. [Solution] The state estimation device is a device for estimating the state of a clock described by a state space model, and comprises: a model acquisition unit that acquires a state space model of a clock network composed of multiple clocks; a time difference information acquisition unit that acquires time difference information indicating the instruction time difference between the multiple clocks for each of the clocks; and a state estimation unit comprising a first estimation unit that estimates the observable portion of the state space model and a second estimation unit that estimates the unobservable portion.

The invention provides an in-speed test design method beneficial to time sequence optimization. The in-speed test design method comprises the following steps: S1, a chip design stage, a comprehensive stage and a test vector generation stage: a buffer is arranged in a netlist; s2, a back-end design stage: no buffer exists in a netlist output by a back end; s3, manually modifying the netlist, and adding a buffer; s4, a form verification stage: comparing that the functions of the netlist are the same before and after the addition of the buffer; s5, a test vector generation stage: inputting a netlist containing a buffer; and S6, a simulation verification stage, wherein no buffer exists in the verified netlist. By using the method, the chip can reach faster frequency; the balance of the clock network can be ensured, the structure of the clock network can be simplified, the possibility of errors is reduced, and the process is simpler; the clock path is inserted into an inverter to optimize the time sequence, and the power consumption is lower than that of an inserted buffer; the size of the chip can be reduced by deleting unnecessary buffers, and the production cost is saved; and the correctness is ensured.

To provide a method, device, and apparatus for monitoring a clock network in an integrated circuit.SOLUTION: The method for monitoring a clock network in an integrated circuit includes the steps of monitoring the clock frequency state of a first clock node in the clock network in the integrated circuit, detecting the clock operation state of a second clock node in the clock network, and determining an operation state of the clock network based on the clock frequency state of the first clock node and the clock operation state of the second clock node.SELECTED DRAWING: Figure 2

The present disclosure provides a clock network optimization method, a computer device and a storage medium. The method comprises: obtaining a chip design layout, determining a signal node set and a receiving endpoint set according to the chip design layout; establishing a connection between the signal node set and the receiving endpoint set, generating an initial connection result; in response to the initial connection result not meeting a set target, adjusting the connection of the initial connection result, determining whether to accept the adjustment through a set strategy, generating an intermediate connection result; and in response to the intermediate connection result meeting the set target, determining the intermediate connection result as an optimization result.

A programmable clock network module and array, relating to integrated circuit technology, are disclosed. The module comprises a first clock network unit, a second clock network unit, and a drive test unit. The programmable clock network module has two connection terminals in each of the up, down, left, and right directions. This invention features testability, low skewness, low duty cycle loss, low power consumption, and improved clock jitter.

A state estimation device estimates the state of a clock described in a state space model, the state estimation device comprising: a model acquisition unit that acquires a state space model of a clock network configured from a plurality of clocks; a time difference information acquisition unit that acquires, for each of the clocks, time difference information indicating an indicated time difference between the plurality of clocks; and a state estimation unit that is provided with a first estimation unit for estimating an observable section of the state space model and a second estimation unit for estimating an unobservable section of the state space model.

A clock tree generated through clock tree synthesis (CTS) for an integrated circuit (IC) design is stored in memory. The IC design includes a post-CTS clock tree having a plurality of clock nets. An application programming interface (API) implements a set of commands to allow a user, through a user request, to provide inputs to restructure the post-CTS clock tree to include a user-specified clock instance. The request is received from a user through the API and includes inputs defining the user-specified clock instance, a physical location of the clock instance, and a logical equivalence of a clock signal to be provided by one of the plurality of clock nets. One of the clock nets in the post-CTS clock tree is selected based on the inputs of the request and the post-CTS clock tree is restructured to include the user-specified clock instance.

The invention discloses a GNN-guided hierarchical H-tree low-skew clock tree synthesis method, which comprises the following steps of: firstly, executing fan-out-radius-capacitance three-constraint clustering on a chip register to generate an optimized buffer leaf cluster; spatial distribution and electrical characteristics are extracted, and an optimal sub-tree division scheme is predicted by using a graph neural network GNN; a K-adaptive non-uniform branch H tree is constructed based on the prediction result, a binary chain structure is adopted for a light load area, and a quadtree structure is adopted for a heavy load area; and finally, integrating the global clock network through the sparse grid. According to the method, the capacitance balance constraint and the graph neural network technology are creatively fused, and compared with a traditional H-tree method, the clock skew is reduced by 11.5%, the clock delay is reduced by 13.9%, the number of buffers is reduced by 31.0%, and the comprehensive operation time is remarkably shortened.

A method for detecting and compensating for power supply voltage droop in a computer system is disclosed. The computer system includes a clock generator circuit that generates a global clock signal, which is distributed by a forward clock network to generate multiple distributed clock signals. A backward clock network may select one or more of the multiple distributed clock signals for back propagation to the clock generator circuit. A control circuit may perform a phase comparison between the global clock signal and the one or more of the multiple distributed clock signals. The clock generator circuit may modify the global clock signal using a result of the phase comparison.

Methods and apparatus for obtaining timing adjustment values for clock points in a clock network are disclosed. In some embodiments, engineering change order (ECO) may be performed in a time- and resource-efficient manner by selecting candidate clock points from a plurality of clock points in the clock network, and performing enumerative and iterative tests on the selected candidate clock points to determine a combination of timing delay adjustment values that most reduces negative slack. The determined timing delay adjustment values may be implemented by an ECO system to effect changes to the clock network and reduce timing violations therein.

The invention provides a clock tree synthesis method related to a frequency dividing circuit. The clock tree synthesis method comprises the following steps: step 1, selectively adding / deleting buffers on a clock line; 2, dividing an independent clock region behind an output pin of a frequency dividing circuit trigger; 3, in the newly divided clock area, a clock is created again, and an independent clock network is created; step 4, adjusting clock delay by adopting an insertiondelay command, and guiding a tool to complete clock tree balance; and step 5, completing automatic wiring of the clock circuit. On the basis of the steps, the problems that time sequence violation of a frequency dividing circuit (DIV) cannot be repaired under an original clock tree synthesis method, and power consumption is increased are solved.

A method for clock distribution network control includes determining, at a first clock node of a plurality of clock nodes within a clock distribution network, a downstream clock request status. A clock request signal is transmitted by the first clock node to an upstream parent node based on the downstream clock request status. A clock buffer of the first clock node is toggled based at least in part on the clock request signal to the parent node. If the first clock node receives an asserted clock request signal from one or more downstream child nodes and clock acknowledgment signal from the parent node, a clock enable signal is asserted to the clock buffer to output a clock signal to the one or more downstream child nodes.

This application relates to the field of integrated circuit clock tree optimization technology, and discloses a low-power clock tree optimization method and system for integrated circuit chips. The method includes: acquiring clock signal propagation delay data, extracting branch delay and edge jitter characteristics, and generating synchronization offset distribution characteristics; calculating the deviation peak value based on this, determining the clock buffer density adjustment range and insertion boundary, and generating a dynamic adjustment interval; based on this interval, combined with the clock tree depth and threshold voltage offset, determining the dynamic voltage adjustment target value through a voltage adjustment unit; updating the supply voltage, analyzing the impact of crosstalk between voltage domains on edge jitter and leakage current, and determining the power consumption distribution change trend; extracting the peak-to-peak value of edge jitter from the trend to complete synchronization verification, and determining the propagation delay fluctuation control configuration based on energy consumption data; updating the operating parameters accordingly, iteratively processing the delay distribution, and generating a load balancing optimization scheme. This application improves the timing convergence and power consumption controllability of the clock network.

This invention relates to a clock discipline system and synchronization discipline method for underwater acoustic communication devices, belonging to the fields of underwater acoustic communication and underwater positioning and navigation technology. It solves the problem that existing network clock systems in underwater acoustic communication networks based on underwater acoustic communication devices can only discipline the clock of one timing node at a time, making it impossible to synchronously discipline the clocks of multiple timing nodes; furthermore, it fails to balance the accuracy, power consumption, and size of the timing nodes. This invention includes a discipline unit and N timing nodes. The discipline unit sequentially sends discipline commands to the N timing nodes via chip select. After receiving the discipline command, each timing node begins receiving a calibrated second pulse signal from the discipline unit, achieving synchronous discipline of the N timing nodes. Each disciplined timing node generates a second timestamp and a microsecond timestamp. The discipline unit also displays the discipline completion status of each timing node. It is primarily applied in underwater acoustic communication device synchronous clock networks.

The invention provides a clock tree and an arrangement method thereof, a microprocessor architecture and electronic equipment, and is applied to the technical field of computers, the clock tree comprises a first-level trunk and at least one second-level trunk, the first-level trunk is arranged based on an H-tree architecture and comprises at least one first-level Tap point, and the second-level trunk comprises at least one second-level Tap point; the secondary trunk comprises a first intensifying buffer and at least one secondary branch driven by the first intensifying buffer, the first intensifying buffer serves as a starting point of the secondary trunk and is connected with a first-stage Tap point of the primary trunk, and the secondary branch is used for providing a clock signal for a local clock network of the microprocessor architecture and is connected with a second-stage Tap point of the secondary trunk. According to the clock tree provided by the invention, only one level of trunk is established based on the H-tree architecture, so that the proportion of the H-tree structure in the clock tree can be effectively reduced, the use quantity of the enhanced buffers is reduced, the overall power consumption and the performance loss of the clock tree are reduced, and the current design requirements of low power consumption and high reliability on the microprocessor architecture are met.

The application discloses a clock tree structure and an implementation method thereof, and relates to the technical field of clock trees.The clock tree structure comprises a trunk clock network and a branch clock network.The trunk clock network is introduced from outside and is composed of a first-stage buffer unit and a second-stage buffer unit.The trunk can be horizontal or vertical.The branch clock network is introduced from the trunk clock network and is composed of a second-stage buffer unit to a third-stage buffer unit.The branch clock drives the load in a window with an L*L size, that is, the third-stage buffer unit drives a fourth-stage buffer unit in a tree structure, and so on, to drive an nth-stage buffer unit and a gated clock unit.The beneficial effects are as follows: the clock tree structure is built by establishing the trunk clock network and the branch clock network, the number of buffer units on the clock network is reduced, and the chip power consumption is reduced;the main clock tree and the sub clock network play the role of a common path, the number of stages of the clock tree is reduced, the influence of OCV on the clock is reduced, and the final timing convergence is easy.

This invention discloses a low-power Bluetooth SoC adaptive clock gating structure and chip. The structure includes a clock source, a backbone clock network, a baseband logic state machine with an internal RF wake-up counter, and an adaptive integrated clock gating macrocell connected to an RF warning feedforward. The macrocell is divided into an environmental sensing region containing a ring oscillator network and a gating logic region containing asymmetric configuration logic gates. The first transistor in the inverter sub-unit and the pull-up transistors within the logic gates are located within a continuously shared N-type well surrounded by a grounded P-type substrate contact ring. The macrocell includes a dynamic compensation unit that dynamically determines the compensation window based on the delay count value and activates the parallel drive buffer. This application can achieve zero-delay, high-precision voltage drop feedback, eliminate glitches and metastability generated during RF wake-up, and reduce unnecessary switching power consumption.

The invention provides a low-power-consumption multi-core SOC, and relates to the technical field of chip design, the low-power-consumption multi-core SOC comprises a first CPU, a second CPU, a clock network, a peripheral unit attached to the first CPU and a peripheral unit attached to the second CPU, and the clock network is used for providing clock signals for the first CPU, the second CPU, the peripheral unit attached to the first CPU and the peripheral unit attached to the second CPU; the configuration register LPMCR is used for configuring the clock gating modes of the multi-core SOC, and the clock gating modes comprise three clock gating modes. The low-power-consumption multi-core SOC chip has multiple low-power-consumption modes, and has a configurable protection field mode for a power-down mode; wakeup supporting multiple modes comprises internal interrupt wakeup and external GPIO wakeup.

The application relates to the chip technical field and provides a clock control path timing optimization method, equipment, medium and program product.The method comprises the following steps: according to the physical size and target frequency of a target circuit module, a plurality of registers are inserted on the clock control path of the target circuit module to construct a pipeline chain; the last-stage register of the pipeline chain is fixed at a target position; a clock network is constructed under the premise of maintaining the position of the last-stage register fixed, and in the process of constructing the clock network, timing constraints between clock gate units controlled by the last-stage register are shielded; after the clock network is constructed, physical connection between the clock gate units and the last-stage register is established, and timing optimization is performed on the clock control path between the last-stage register and the clock gate units.The application avoids power consumption surge, wiring congestion and violation risks caused by excessively long paths, and significantly improves the timing convergence rate and resource utilization rate of a high-performance chip in a sign-in stage.

The present application relates to the technical field of integrated circuits, and particularly relates to a clock tree synthesis method and system. The present application generates multiple optimization groups by dynamically grouping clock trees, and then iteratively optimizes each optimization group to balance clock skew. Specifically, in the iteration process, a skew compensation device is inserted into the optimization group with the minimum delay, and in each iteration, the skew of the optimization group after the skew compensation device is inserted is balanced, and then it is determined whether the skew is balanced. If so, the iteration is ended. If not, the next iteration is continued until all optimization groups reach the clock skew balance, and the iteration optimization is ended. By using the above scheme, the clock network convergence efficiency and layout adaptability are significantly improved while ensuring the optimization accuracy through the cooperative optimization of the grouping strategy and the clock skew balance mechanism.

The application provides a multi-modal fusion laser directed energy deposition real-time monitoring method and system, and belongs to the technical field of additive manufacturing; the method comprises the following steps: synchronously triggering through a multi-source sensor to collect real-time data of a molten pool area in a laser directed energy deposition process; a distributed clock network is constructed, environment influence parameters are collected in real time in combination with a working condition sensing unit, dynamic modeling and correction are performed on asymmetric link delays in a clock synchronization process, and spatio-temporal alignment of multi-source sensor data is realized; after the multi-source sensor data subjected to spatio-temporal alignment is preprocessed, data level fusion, feature level fusion and decision level fusion operations are sequentially performed. The application can monitor the molten pool state in real time and accurately, and improves the quality and stability of the laser directed energy deposition process.

The invention relates to a clock tree synthesis method and system for reducing vertical coupling capacitance of a clock tree, and belongs to the technical field of clock tree synthesis. The core of the method is that in the clock tree synthesis process of a physical design stage, parasitic coupling capacitance of a clock line and an adjacent signal line between vertical metal layers is systematically reduced through preset vertical direction design of a clock tree and a clock tree synthesis optimization cost function based on coupling sensing; therefore, the anti-noise capability of the clock network is improved, and the delay uncertainty and the dynamic power consumption are reduced.

The invention relates to the technical field of radio frequency communication, and discloses a multi-channel amplitude phase correction system and method based on a radio frequency chip. The multichannel amplitude phase correction method is applied to phase correction equipment, and specifically comprises the following steps: S101, receiving a radio frequency chip initialization instruction of a terminal, and generating an executable initialization sequence based on radio frequency chip configuration parameters, and completing comprehensive initialization of a working mode, a clock network and interface parameters of the radio frequency chip through a parallelization register configuration mechanism. According to the method, zero-cross detection and a multiple measurement average algorithm are combined, the phase measurement precision reaches 0.1 degree, measurement errors caused by noise interference are effectively overcome, twiddle factors are generated through DDS verification in the complex plane phase shifting technology, the contradiction between the capacity and the precision of a traditional lookup table method is avoided, the phase correction response time is shortened to a single clock period, and the phase correction efficiency is improved. A 2048-point sliding window and an adaptive gain mapping table are adopted in digital AGC, and microsecond-level dynamic amplitude tracking is achieved.

The invention discloses a gate control unit generation method and device and a medium, and relates to the technical field of electronic design automation. A first connection relation of boundary ports of the first gate control unit under the general library logic unit structure, and a second connection relation of ports between a latch and an AND gate unit in the first gate control unit under the general library logic unit structure. A first mapping relation between pin signals of respective corresponding gating units under the standard library unit structure and the general library logic unit structure is established in advance. And creating a second gating unit of the standard library unit structure according to the first connection relationship, the second connection relationship and the first mapping relationship to complete the generation process of the gating unit. And replacement from a general library logic unit structure to a specific standard library unit structure is realized. Integration is achieved through the corresponding spliced gating units before optimization, the clock network power consumption is reduced, meanwhile, the burr phenomenon caused by timing sequence mismatch caused by spliced clock gating is avoided, and the design correctness is improved.