64 results about "Clock network" patented technology

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

A clock tree generated through clock tree synthesis (CTS) for an integrated circuit (IC) design is stored in memory. The IC design includes a post post-CTS clock tree that includes a plurality of clock nets. A request to add a user-specified clock instance to the post-CTS clock tree is received and all logically equivalent clock nets in the post-CTS clock tree detected to generate a set of candidate clock nets. A reduced set of candidate clock nets is generated from the set of candidate clock nets based on a distance between each candidate clock net and the clock instance. One candidate clock net in the reduced set is selected based on a length of conductive traces required to interconnect the corresponding candidate clock net and the clock instance. The post-CTS clock tree is restructured to connect the clock instance to the selected one of the candidate clock nets.

The invention provides a multi-mode fusion laser directional energy deposition real-time monitoring method and system, and belongs to the technical field of additive manufacturing. Comprising the steps that real-time data collection is conducted on a molten pool area in the laser directional energy deposition process through synchronous triggering of a multi-source sensor; a distributed clock network is constructed, environment influence parameters are collected in real time in combination with a working condition sensing unit, dynamic modeling and correction are conducted on asymmetric link delay in the clock synchronization process, and space-time alignment of multi-source sensor data is achieved; after the multi-source sensor data subjected to space-time alignment is preprocessed, data-level fusion, feature-level fusion and decision-level fusion are performed in sequence. The state of the molten pool can be accurately monitored in real time, and the quality and stability of the laser directional energy deposition process are improved.

The invention provides a hierarchical clock tree synthesis method and system based on a hybrid topological structure, and aims to collaboratively optimize clock skew and clock delay in a chip clock network. The method comprises the following steps: firstly, introducing a balanced greedy search clustering algorithm, clustering registers at the initial stage of clock network construction, and reducing local clock skew and delay; and generating a bottom layer clock tree in each cluster by adopting a bounded deviation construction method so as to ensure the clock synchronization quality in the cluster. In a top-layer clock tree construction stage, the invention provides a self-adaptive H-tree topology construction algorithm, and the H-tree structure is dynamically adjusted according to the position relationship among all layers of clusters, so that a global clock distribution path is optimized under multiple layers. Besides, in order to further improve the CTS quality, the invention further designs a clock network optimization strategy based on buffer post-processing, and local buffer insertion and position adjustment are carried out for the problems of fan-out unevenness and load overrun so as to eliminate potential illegal paths.

The invention relates to a radio frequency transceiving multichannel amplitude-phase calibration system, which comprises a radio frequency receiver, a radio frequency transmitter, a data converter, an FPGA (Field Programmable Gate Array) processor and a clock network, wherein the radio frequency receiver adopts a zero intermediate frequency architecture and is used for receiving a multichannel radio frequency signal and down-converting the multichannel radio frequency signal into an analog baseband signal; the radio frequency transmitter adopts a zero intermediate frequency architecture and is used for up-converting the analog baseband signal into a radio frequency signal and transmitting the radio frequency signal; the data converter is connected with the radio frequency receiver and the radio frequency transmitter and is used for realizing conversion between an analog signal and a digital signal; the FPGA processor is connected with the data converter through a JESD204B interface and is used for aligning the data of each receiving and transmitting channel; and the clock network consists of a clock chip with JESD204B characteristics and a clock Buffer, and is used for providing a synchronous clock and an SYSREF signal for the whole system and supporting an SYNC synchronous trigger signal. By adopting the method, the problem of multi-channel amplitude-phase consistency can be solved.

The invention relates to the technical field of high-precision motion control, and discloses a multi-axis nanoscale real-time synchronous control system and method based on heterogeneous computing cooperation. The system adopts a space-time separation architecture of an AM5728 processor and an FPGA (Field Programmable Gate Array); the FPGA is used as a time sensitive layer; nanosecond synchronous acquisition of data of a multi-axis sensor and strict synchronous output of a control signal are realized through a global clock network; a double-DSP core of the AM5728 serves as a calculation dense layer, and parallel calculation of a multi-axis control algorithm is executed. Low-latency interaction of instructions and data is achieved through an optimized PCIe / GPMC interface. Under a clock taming mechanism, the synchronization error of the multi-axis control signal is obviously reduced, and the positioning precision is obviously improved. According to the scheme, the problem of real-time cooperative control of a multi-axis system in the fields of semiconductor manufacturing and the like is solved, and the cost is greatly reduced compared with a traditional architecture.

The invention provides a programmable frequency control array radar waveform generation system and method based on an FPGA, and belongs to the technical field of radar systems and digital signal processing. In order to solve the technical problems of complex hardware system, inflexible parameter adjustment and poor multi-channel synchronism of the traditional frequency control array radar, the invention provides an integrated high-performance solution. The system adopts an FPGA (Field Programmable Gate Array) architecture of an integrated processing system (PS) and programmable logic (PL). The method comprises the following steps: a PS end receives waveform control parameters of an upper computer through a communication interface and transmits the waveform control parameters to a PL end; and a plurality of parallel direct digital frequency synthesizer (DDS) modules in the PL end synchronously generate multi-channel digital baseband signals with programmable frequency offset at high precision according to the parameters under the unified driving of the FPGA global clock network. And the digital signal is subjected to digital-to-analog conversion and radio frequency front-end processing to finally form a transmitting wave beam. According to the invention, flexible programmability of parameters is realized by utilizing a PS-PL collaborative architecture, the synchronization precision of multi-channel signals is remarkably improved through a global clock network and a parallel DDS module generated in the FPGA, and meanwhile, the system has the advantages of high integration level and low complexity.

The invention relates to the technical field of chips, and provides a time sequence optimization method and device for a clock control path, a medium and a program product, and the method comprises the steps: inserting a multi-stage register on the clock control path of a target circuit module according to the physical size and target frequency of the target circuit module, and constructing to obtain an assembly line chain; fixing a last-stage register of the assembly line chain at a target position; constructing a clock network on the premise of keeping the position of the last-stage register fixed, and in the process of constructing the clock network, shielding a time sequence constraint from the last-stage register to a clock gating unit controlled by the last-stage register; and after the clock network is constructed, physical connection between the clock gating unit and the last-stage register is established, and time sequence optimization is performed on a clock control path between the last-stage register and the clock gating unit. According to the method, power consumption surge, wiring congestion and violation risks caused by an overlong path are avoided, and the time sequence convergence rate and the resource utilization rate of the high-performance chip in the sign-off stage are remarkably improved.

A method for constructing a fishbone H-clock tree suitable for a high-speed interface module includes the following steps: S1, setting an instance of a clock tree by means of an EDA tool, and eliminating existing definitions; S2, setting a root node, a non-default routing rule and multiple TAP nodes; S3, creating an H-clock tree, and performing H-clock tree synthesis, wherein the H-clock tree synthesis includes: introducing multiple intermediate nodes between the root node and the TAP nodes, editing a clock network between the root node and the TAP nodes by means of an innovus script, and deleting each redundant intermediate node to obtain a structure of a fishbone H-clock tree; mounting multiple sinks on each TAP node, and defining the TAP nodes in a same source group by means of the EDA tool; and performing routing according to the non-default routing rule to complete construction.

A unified timing closure system for the simultaneous synthesis of multi-mode clock trees in a system-on-chip architecture, comprising: a timing convergence processor configured to perform simultaneous analysis and optimization of clock distribution paths across a variety of operating modes and process voltage-temperature operating conditions, wherein the timing convergence processor maintains a unified timing graph that correlates all clock sinks with multiple mode vectors representing setup and hold relationships under different conditions; a multitude of distributed computer scaling units distributed across physically distinct sub-areas of the system-on-chip architecture, each distributed computer scaling unit being configured to determine local delay scaling factors corresponding to process variations, voltage fluctuations, and temperature gradients in its respective sub-area, and dynamically adjust the delay buffer characteristics, link impedance, and driver strength in response to the local scaling factors; a clock offset synchronization unit coupled with the timing convergence processor and the numerous distributed clock scaling units, wherein the clock offset synchronization unit is configured to monitor and minimize insertion delay differences between multiple clock sinks by dynamically adjusting capacitive loads and buffer driver strengths throughout the clock network to maintain uniform propagation characteristics across all modes; a multi-mode synchronization processor that is operationally linked to the timing convergence processor and is configured to harmonize clock arrival times across the operating modes of function, test, and power saving by mapping all mode-specific constraints into a unified timing domain, and to correct inter-mode skew divergence by iteratively adjusting clock path latencies; a distributed timing communication interface that establishes a hierarchical interconnection network between the timing convergence processor and the multiple distributed corner scaling units, wherein the distributed timing communication interface is configured to exchange real-time timing information, delay deviation metrics, and control instructions via a synchronized token-based communication protocol; and A physical time-matching circuit consisting of tunable delay lines, programmable capacitive elements and temperature-compensated bias transistors, physically embedded in the clock distribution network, wherein the physical time-matching circuit receives adaptive control signals from the time convergence processor and adjusts local propagation characteristics to achieve time completion simultaneously across all operating modes and process boundaries.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

Various embodiments provide for assigning portions of a net based on one or more non-default design rules, which may be part of electronic design automation (EDA). For example, a net of a circuit design can be a clock network, and the assigning can comprise a layer assignment process, a track assignment process, or both. Additionally, various embodiments described herein can permit a plurality of non-default design rules to be applied to a single net of a circuit design.

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

A state estimation device and program capable of achieving high-precision time synchronization of a group of clocks. To provide. [Solution] The state estimation device is a device for estimating the state of a clock described by a state space model, and comprises: a model acquisition unit that acquires a state space model of a clock network composed of multiple clocks; a time difference information acquisition unit that acquires time difference information indicating the instruction time difference between the multiple clocks for each of the clocks; and a state estimation unit comprising a first estimation unit that estimates the observable portion of the state space model and a second estimation unit that estimates the unobservable portion.

The invention relates to the technical field of integrated circuits, in particular to a clock tree synthesis method and system. According to the scheme, the clock tree is dynamically grouped to generate a plurality of to-be-optimized groups, and then each to-be-optimized group is iteratively optimized, so that all to-be-optimized groups achieve clock skew balance. Specifically, in the iteration process, a deviation compensation device is inserted into a to-be-optimized group with the minimum delay, in each round of iteration, clock skew balance is carried out on the to-be-optimized group after the deviation compensation device is inserted in the current round, then whether skew balance is achieved or not is judged, if yes, the process is finished, and if not, the process is finished. And if not, continuing to carry out the next round of iterative optimization until all the to-be-optimized groups reach clock skew balance, thereby ending the iterative optimization. By adopting the scheme, through collaborative optimization of the grouping strategy and the clock skew balance mechanism, the convergence efficiency and layout adaptability of the clock network are remarkably improved while the optimization precision is guaranteed.

The invention provides an in-speed test design method beneficial to time sequence optimization. The in-speed test design method comprises the following steps: S1, a chip design stage, a comprehensive stage and a test vector generation stage: a buffer is arranged in a netlist; s2, a back-end design stage: no buffer exists in a netlist output by a back end; s3, manually modifying the netlist, and adding a buffer; s4, a form verification stage: comparing that the functions of the netlist are the same before and after the addition of the buffer; s5, a test vector generation stage: inputting a netlist containing a buffer; and S6, a simulation verification stage, wherein no buffer exists in the verified netlist. By using the method, the chip can reach faster frequency; the balance of the clock network can be ensured, the structure of the clock network can be simplified, the possibility of errors is reduced, and the process is simpler; the clock path is inserted into an inverter to optimize the time sequence, and the power consumption is lower than that of an inserted buffer; the size of the chip can be reduced by deleting unnecessary buffers, and the production cost is saved; and the correctness is ensured.

The application relates to a chip clock network delay test method and a test circuit, and relates to integrated circuit technology. The test method comprises the following steps: 1) a clock management circuit module in a chip provides a control clock signal and N test clock signals, the phases of the test clock signals are the same, and N is an integer greater than 2; 2) N test branches are constructed, each test branch comprises a clock network path and a flip-flop connected to the clock network path, and the test branches and the test clock signals are one-to-one corresponding; 3) the control clock signal is connected to the flip-flop area in the chip through the same path, and then is branched to each flip-flop, so that the control clock signal is used as the control clock of each flip-flop; 4) the phase of the control clock signal is adjusted in a waveform sliding mode through the clock management circuit module, and the output of each flip-flop is recorded; and 5) the phase difference of the output signals of the flip-flops is used to judge the delay difference between the test branches. The application has low test cost and high precision.

To provide a method, device, and apparatus for monitoring a clock network in an integrated circuit.SOLUTION: The method for monitoring a clock network in an integrated circuit includes the steps of monitoring the clock frequency state of a first clock node in the clock network in the integrated circuit, detecting the clock operation state of a second clock node in the clock network, and determining an operation state of the clock network based on the clock frequency state of the first clock node and the clock operation state of the second clock node.SELECTED DRAWING: Figure 2

The invention discloses a clock network configuration method, device, system and equipment, a medium and a product, and relates to the technical field of high-speed interconnection communication, and the clock network configuration device comprises a clock failure monitoring module, a decision control module, a first multiplexer switching module and a second multiplexer switching module. The clock failure monitoring module monitors multiple paths of clock source signals in real time, the decision control module controls the multiplexer module to achieve port switching according to decision control information, redundant clock source switching and hybrid configuration are achieved, the reliability and flexibility of the system are improved, and link interruption caused by failure of a single clock source is avoided.

The present disclosure provides a clock network optimization method, a computer device and a storage medium. The method comprises: obtaining a chip design layout, determining a signal node set and a receiving endpoint set according to the chip design layout; establishing a connection between the signal node set and the receiving endpoint set, generating an initial connection result; in response to the initial connection result not meeting a set target, adjusting the connection of the initial connection result, determining whether to accept the adjustment through a set strategy, generating an intermediate connection result; and in response to the intermediate connection result meeting the set target, determining the intermediate connection result as an optimization result.

The invention discloses a clock data recovery circuit applied to a multi-channel array high-speed SerDes receiver. A half-rate decision feedback equalizer carries out signal recovery processing on an original analog signal input in a current period according to a first target sampling clock output from a clock network in a previous period and outputs a digital serial signal; the target sampler carries out sampling processing on the digital serial signal according to a second target sampling clock output from the clock network in the previous period and outputs serial judgment data; the demultiplexer carries out parallel processing on the digital serial signals and the serial judgment data according to a third target sampling clock output from the clock network in the previous period and outputs multiple paths of parallel signals; the clock recovery module generates a target four-phase clock according to the local clock signal and the multi-path parallel signal; and the clock network generates a first target sampling clock, a second target sampling clock and a third target sampling clock of the next period according to the target four-phase clock. The clock data recovery circuit has the advantages of low power consumption and high speed.

The application belongs to the technical field of integrated circuits, and provides a clock tree generation method, a medium and an electronic device. The method comprises the following steps: obtaining a netlist file of a circuit; identifying a clock network according to a network identifier in the netlist file. Then, the type of a device is identified according to the identification information of the device in the netlist file, and the pin information of the device is determined. The clock link is determined according to the connection relationship of the device in the netlist file. Furthermore, the flow direction of the clock signal can be determined according to the clock link and the pin information of the device. Therefore, the electronic device can automatically draw a clock tree, and the circuit development efficiency is improved.

The invention discloses a generation method, device and system suitable for a hybrid-driven multi-bit trigger. The generation method comprises the following steps: acquiring all single triggers in a digital chip of which the initial layout design is completed; mapping each single trigger into a ternary trigger vector comprising a transistor size, a threshold voltage and a number, and generating a trigger matrix; splitting the trigger matrix into a plurality of independent sub-matrixes according to the clustering result of the single trigger, wherein each sub-matrix corresponds to one multi-bit trigger; repeating the following steps until the Pareto front is stable and meets a preset layout legalization verification condition to obtain a multi-bit trigger: by taking the normalized total negative margin and power consumption minimization as optimization objectives, optimizing each sub-matrix by adopting a proxy auxiliary differential evolution algorithm and a non-dominated sorting evolution algorithm to obtain a Pareto optimal solution set; and if the multi-bit trigger corresponding to the Pareto optimal solution set does not meet the layout legalization verification condition, re-dividing the trigger matrix. The clock network power consumption can be reduced, and the time sequence convergence rate is improved.

The application discloses a clock circuit of a programmable logic device and a clock circuit configuration method. The clock circuit of the programmable logic device comprises a clock network comprising a plurality of clock paths, the plurality of clock paths having the same input clock signal and being respectively used for transmitting the clock signal to corresponding programmable logic; the number of inverters on each clock path is zero, one or more; a plurality of clock polarity selectors are respectively arranged on the plurality of clock paths, each clock polarity selector is used for performing inversion output or original polarity output on the received clock signal according to a preset polarity selection control signal; wherein each polarity selection control signal is determined based on the number of inverters on the corresponding clock path, so that the clock signals received by each programmable logic have the same polarity. Thus, the application can reduce the influence of clock signal duty cycle deterioration and ensure the consistency of clock polarity without limiting the parity of inverters.

A programmable clock network module and array, relating to integrated circuit technology, are disclosed. The module comprises a first clock network unit, a second clock network unit, and a drive test unit. The programmable clock network module has two connection terminals in each of the up, down, left, and right directions. This invention features testability, low skewness, low duty cycle loss, low power consumption, and improved clock jitter.

The application belongs to the technical field of digital and mixed signal integrated circuit design, and relates to a reinforced circuit structure and a reinforcing method for suppressing single particle effect. The reinforced circuit structure comprises: multiple parallel clock signal channels and a voter, the voter is used for majority voting on clock signals output by the multiple clock signal channels to output a system clock signal; each clock signal channel comprises a voltage-controlled oscillator, a power detection module and a controllable delay unit; the voltage-controlled oscillator is used for generating an original clock signal with the same frequency as other clock signal channels; the power detection module is used for generating a pulse signal when there is a phase deviation between the original clock signal and the system clock signal, and converting the pulse signal into a direct current control voltage; and the controllable delay unit is used for dynamically adjusting the delay amount of the original clock signal according to the direct current control voltage. The application can effectively suppress the propagation of single particle transient in the clock network, and avoid voting errors and glitch propagation caused by phase deviation.

The application relates to the technical field of clock network, in particular to a voltage-insensitive FPGA clock network and a control method, the FPGA clock network comprises a plurality of clock buffers with adjustable time delay; the clock buffer receives local feedback information of a current clock buffer or global feedback information of a backward clock buffer corresponding to a backward node, and dynamically adjusts the transmission time delay according to the local feedback information or the global feedback information; the clock buffer comprises a local feedback module and a global feedback module; the local feedback module adaptively adjusts circuit parameters of the current clock buffer based on the local feedback information, so as to balance local power supply voltage fluctuation; and the global feedback module adaptively adjusts the circuit parameters of the current clock buffer based on the global feedback information, so as to balance global power supply voltage fluctuation. The application can dynamically adjust the transmission time delay of the clock network, and effectively reduces the influence of power supply voltage fluctuation on the clock network.

A state estimation device estimates the state of a clock described in a state space model, the state estimation device comprising: a model acquisition unit that acquires a state space model of a clock network configured from a plurality of clocks; a time difference information acquisition unit that acquires, for each of the clocks, time difference information indicating an indicated time difference between the plurality of clocks; and a state estimation unit that is provided with a first estimation unit for estimating an observable section of the state space model and a second estimation unit for estimating an unobservable section of the state space model.

A clock tree generated through clock tree synthesis (CTS) for an integrated circuit (IC) design is stored in memory. The IC design includes a post-CTS clock tree having a plurality of clock nets. An application programming interface (API) implements a set of commands to allow a user, through a user request, to provide inputs to restructure the post-CTS clock tree to include a user-specified clock instance. The request is received from a user through the API and includes inputs defining the user-specified clock instance, a physical location of the clock instance, and a logical equivalence of a clock signal to be provided by one of the plurality of clock nets. One of the clock nets in the post-CTS clock tree is selected based on the inputs of the request and the post-CTS clock tree is restructured to include the user-specified clock instance.