This application discloses a large-scale cascaded
digital array antenna and a receiving synchronization method. The
digital array antenna includes a master module, several slave modules, an
antenna array, and a correction power divider network. The master module is connected to each slave module, and each slave module is connected to an element of the
antenna array. The correction power divider network is connected to the multi-channel
receiver chip of the master module and each slave module. Each slave module includes a slave SOC FPGA, an FPGA, a
clock driver, and a multi-channel
receiver chip. The FPGA integrates a DDS module, and the multi-channel
receiver chip integrates an RF PLL. The slave SOC FPGA is connected to the FPGA, the
clock driver, and the multi-channel receiver chip. The multi-channel receiver chip in the master module only outputs signals to the correction power divider network and does not receive any signals output by the correction power divider network. This application can achieve full amplitude and
phase coherence at the element level of a large-scale
digital array antenna, high-precision distributed channel synchronization correction, and high-fidelity digital
beamforming, effectively ensuring the quality of digital
beamforming.