16 results about "Fractional delay filter" patented technology

The invention belongs to the technical field of underwater acoustic engineering and digital signal processing, and particularly relates to a fractional delay FIR (Finite Impulse Response) phase calibration method and system of a multichannel sonar system. Comprising the steps of signal acquisition and reference channel selection; high-precision relative delay estimation; calculating a cross-correlation function of other channel signals and the reference channel signal, performing coarse estimation by searching a peak point of the amplitude of the cross-correlation function, and performing fine estimation on the peak position by using a parabola interpolation method to obtain the delay time of each channel relative to the reference channel; designing an FIR fractional delay filter; digital filtering and phase calibration; verifying a calibration effect; and calculating the phase of each channel signal at the target frequency point after calibration, and counting the standard deviation of each channel signal so as to evaluate the improvement degree of phase consistency. The method aims at overcoming the defect that traditional integral multiple sampling delay correction precision is insufficient, high-precision phase compensation of a sub-sampling point level is achieved, and therefore the performance of algorithms such as beam forming of a multi-channel sonar system is remarkably improved.

The invention relates to a multi-beam IQ data synchronization method based on source end pre-bias and receiving end shallow cache. The method comprises the following steps that: a receiving end measures round-trip delay of an optical link and calculates a pre-bias containing integer and decimal components; the sending end adjusts a buffer read pointer and controls a digital fractional delay filter to perform source end compensation; and a receiving end absorbs residual jitter by using a shallow-depth elastic buffer unit, and uniformly triggers reading after a full link is ready. The method has the advantages that the resource consumption of the receiving end is greatly reduced, the certainty low time delay is ensured, the dynamic thermal drift compensation is supported, and the high-precision sample point level alignment is realized.

A digital correction method for dynamic range expansion of multiple ADCs includes: obtaining gain and offset correction values of other channels relative to a standard channel CH1 based on iterative computations through positive and negative amplitude auxiliary values and positive and negative base values, then performing gain-offset error correction on the other channels, and then calculating phase differences of the other channels relative to the standard channel CH1 and constructing fractional delay filters with a Farrow structure corresponding to the channels, correcting sampling data X2, . . . , XM after performing the gain-offset error correction. Digital correction of sampling data collected from multiple channels in a multi-ADC system is realized while ensuring that respective dynamic ranges of the sampling data with different gains output by the multiple channels are not lost.

A variable fractional delay FIR filter optimization design method based on an intelligent optimization algorithm comprises the steps that S1, the design problem of a Farrow structure variable fractional delay filter is converted into solving of two ill-conditioned linear equation sets; s2, solving the ill-conditioned linear equation set by adopting an improved principal component weighted iterative algorithm, wherein weighting factors of the principal component weighted algorithm are associated with optimization parameters through an exponential mapping relation; s3, constructing a collaborative optimization framework by utilizing a Runge-Kutta optimization algorithm, and performing joint optimization on parameters and orders of a filter by taking an error norm of a filter coefficient vector solution as an optimization target; and iteratively solving the ill-conditioned linear equation set to obtain an optimal filter coefficient sum, and completing the filter design. According to the method, the defect of high calculation complexity of a traditional linear programming method and a second-order cone programming method is overcome, the order of the filter is further optimized while the same performance is obtained, and 28% of hardware resources can be saved.

This invention relates to the field of digital signal processing technology and discloses a low-complexity, high-precision delay method based on polyphase filter interpolation, comprising: S1 designing a prototype low-pass filter; S2 performing polyphase decomposition on the interpolated filter, decomposing it into I-phase; S3 decomposing the fractional delay requirement of the input signal, with the integer part implemented through sampling period delay and the fractional part implemented through a fractional delay filter; S4 storing the coefficients of the I-phase filter as a coefficient array, and determining the delay interval of the virtual branch according to the input fractional delay parameters; S5 using polynomial interpolation to fit the filter coefficients of the virtual branch from the coefficient array, configuring them into an FIR filter to form a fractional delay filter; S6 designing the fractional delay filter as a high-speed parallel filter structure, converting serial computation into L-way parallel computation. This invention achieves high-precision variable fractional delay control with a low-complexity, low-computational-load configurable filter structure.

The invention provides an FI-DAC system fractional time delay error calibration method based on an improved CMA-ES, belongs to the technical field of FI-DAC system time delay error calibration, and aims to solve the problems that in existing FI-DAC system time delay error calibration, fractional time delay precision in a filter design pass band is low, and the coefficient frequency band utilization rate of a designed Farrow structure fractional time delay filter is low. Comprising the following steps: S1, converting a design problem of a VFD digital filter into a design problem of a Farrow structure filter; s2, setting a sub-filter coefficient in a Farrow structure filter, and calculating ideal filter group delay and a VFD error; s3, discretizing fractional delay and normalized frequency in the VED error, and converting a Farrow structure filter design problem into an unconstrained continuous optimization problem; and S4, obtaining an optimal approximate solution of an unconstrained continuous optimization problem by adopting a CMA-ES algorithm, and completing FI-DAC system fractional time delay error calibration.

The invention discloses a TIADC sampling time mismatch error estimation and calibration method, and belongs to the technical field of high-speed data acquisition and real-time transmission. According to the method, high-precision time error estimation is realized in a mode of combining improved first-order statistics and LMS adaptive filtering, dynamic correction is carried out by adopting a parallel Farrow fractional delay filter based on Lagrange interpolation, and a sub-ADC is used for sampling a difference value between a signal and an ideal signal and derivative information in an error estimation stage. A time mismatch initial estimation value is calculated through improved first-order statistics, the estimation value is iteratively optimized through an LMS algorithm, dynamic error tracking is achieved, optimized error parameters are input into an improved parallel Farrow filter, and K sub-filter banks are generated through a multi-phase decomposition structure. According to the invention, the spurious-free dynamic range and significant digits of the TIADC system are significantly improved, and the TIADC system is suitable for high-frequency signal acquisition scenes such as 5G communication and radar.

The invention discloses a variable fractional delay filter optimization method and system based on full coefficient compression. The method comprises the following steps: firstly, constructing a variable fractional delay filter frequency response function based on a Farrow structure; then setting an amplitude constraint based on a variable amplitude response peak error and a delay constraint based on a variable fractional delay peak error; setting constraint parameters based on a full-coefficient compression L0 norm, constructing an optimization model based on a full-coefficient compression sensing L0 norm, and converting the optimization model into an L1 norm optimization model; and finally, solving a weighted L1 norm optimization problem to obtain an optimal variable fractional delay filter coefficient. The system is used for realizing the variable fractional delay filter optimization method based on full coefficient compression. According to the method, the variable fractional delay filter with the optimal amplitude error performance can be obtained under the condition of least resource and time consumption, the amplitude error performance of the system is optimized, and the method is suitable for the field of radar signal processing.

A method for optimizing the design of a variable fractional delay (FIR) filter based on an intelligent optimization algorithm includes: S1 transforming the design problem of a Farrow structure FIR filter into solving two ill-conditioned linear equations; S2: using an improved principal component weighted iterative algorithm to solve the ill-conditioned linear equations, where the weighting factors of the principal component weighted algorithm are associated with the optimization parameters through an exponential mapping relationship; S3: constructing a collaborative optimization framework using the Runge-Kutta optimization algorithm, using the error norm of the filter coefficient vector solution as the optimization objective, and jointly optimizing the parameters and the filter order; iteratively solving the ill-conditioned linear equations to obtain the optimal sum of filter coefficients, thus completing the filter design. This invention overcomes the high computational complexity of traditional linear programming and second-order cone programming methods, and further optimizes the filter order while achieving the same performance, saving 28% of hardware resources.

The invention provides a wide and narrow band signal synchronous measurement method based on time mark interpolation and fractional delay filtering. The method comprises the following steps: S1, signal preprocessing; s2, time mark synchronization processing; s3, carrying out phase synchronization processing; s4, carrying out ILS signal processing; s5, processing a station identification code; and S6, processing the DVOR signal. The invention aims to overcome the problem of time delay difference caused by the fact that synchronization of wide and narrow band signals depends on a clock synchronization mode in the prior art, the time delay difference between channels with different sampling rates is eliminated through a time scale interpolation algorithm, and cross-channel phase synchronization is realized by adopting a fractional delay filter in combination with a phase compensation technology. And technical support is provided for accurate analysis of navigation signals.

The invention relates to the field of digital signal processing, and particularly discloses a reactive power filter design method combined with phase angle calibration, which comprises the following steps: building a voltage and current phase shift adjusting unit, setting a current signal delay module and a voltage signal variable fractional delay filter, and cooperatively realizing phase shift adjustment of voltage and current. The variable fractional delay filter is used for processing a non-integer delay scene so as to match the phase relation of voltage and current; a variable fractional delay filter is designed by adopting a symmetric structure, and a filter coefficient is solved based on a weighted least square method, so that the filter approaches target frequency response in a specified passband; obtaining a reactive power residual value in a 1L scene, and determining an angular difference between the voltage and the current through an angular difference calculation unit; phase angle parameters of the phase shift adjusting unit are updated according to the angular difference between the voltage and the current, phase shift adjustment is executed again, and reactive power calibration is completed; and correcting the active power based on the calibrated reactive power to obtain an active power value.

A system may include an analog front-end circuit configured to receive signals from an antenna array and a digital circuit coupled to the analog front end. The digital circuit may include a digital beamforming circuit configured to include a Nyquist fractional delay filter that is piecewise continuous in the frequency domain. The Nyquist fractional delay filter may be implemented as a Gaussian Nyquist filter, a generalized raised cosine Nyquist filter, or another Nyquist filter. The fractional delay filter may be critically sampled and evaluated numerically or with a closed-form time-domain expression. The fractional delay filter may be part of a digital beamforming phased array antenna system.

The application relates to a high-precision estimation and correction method for fractional multiple delay self-interference signals, which adopts Kalman filtering of frequency domain data and a fractional multiple delay estimation and a fractional delay filter of a Farrow structure to perform fractional multiple delay compensation, realizes fractional multiple delay alignment of a local reference signal and a received signal, improves time domain correlation of the local reference signal and the received signal, improves a self-interference cancellation suppression ratio, and meets low-orbit navigation GNSS signal receiving and low-orbit navigation enhancement signal broadcasting requirements.

The embodiment of the invention provides a variable fractional delay filter design method and system. The method is applied to the technical field of communication technology and signal processing, and comprises the following steps: constructing a function relationship between an analog filter and a digital filter through a sampling theory based on a VFD filter principle of a Farrow structure; the analog filter is cut off through a window function method, and a high-order FIR filter is obtained through calculation; the high-order FIR filter coefficient is decomposed into a plurality of different fractional delay filters, and a VFD filter coefficient of a Farrow structure is calculated by using a segmentation fitting method; and designing a variable fractional delay filter through a VFD filter coefficient of a Farrow structure based on the function relationship. In this way, the filter designed by the method has obvious advantages in frequency aliasing resistance, and the designed variable fractional delay filter has better application prospects.

The application discloses a high code rate narrow correlator generation method and device. It relates to the field of high-precision microwave two-way time synchronization. The application realizes the accurate generation of the leading and lagging codes by accurately delaying the generated local code sequence with a non-integer clock through a fractional delay filter, and solves the problem of generating a high code rate and low system sampling rate narrow correlator. The method comprises the following steps: storing a local code sequence in a logic device memory, wherein the local code sequence is a 0 / 1 level pseudo-random sequence; performing level conversion on the local code sequence, keeping the 1 level unchanged, and converting the 0 level into a-1 level; and performing fractional clock delay on the local code sequence after the level conversion to obtain a leading sequence, an instant sequence and a lagging sequence; wherein the correlation interval between the leading sequence and the instant sequence and the correlation interval between the lagging sequence and the instant sequence are both 0.1 chips.

The invention relates to the field of electric energy metering, and particularly discloses a variable fractional delay filter based on a symmetric structure and a weighted least square method, and the filter comprises a signal parameter pre-calculation unit which is used for providing a delay parameter for the filter; the symmetric structure FIR coefficient construction unit is used for calculating a symmetric FIR coefficient framework; the WLS coefficient optimization unit is used for calculating a fixed-point optimization coefficient matrix; the phase shift execution unit is used for realizing integer delay of the current signal through a cache length and realizing fractional delay compensation of the voltage signal through a VFD filter, and the integer delay and the fractional delay compensation cooperate to complete'integer + fractional 'joint phase shift; the self-adaptive calibration and frequency tracking unit is used for calculating an angular difference between the voltage and the current; and adding the calculated angular difference with an original phase shift angle to obtain an updated phase shift angle, and when it is detected that the absolute value of the difference value between the current fundamental frequency and the historical fundamental frequency is larger than a fundamental frequency fluctuation threshold value, synchronously updating the time delay integer part, the decimal delay and the current path signal cache length.