The invention belongs to the technical field of underwater acoustic engineering and digital signalprocessing, and particularly relates to a fractional delay FIR (Finite Impulse Response) phase calibration method and system of a multichannel sonarsystem. Comprising the steps of signal acquisition and reference channel selection; high-precision relative delayestimation; calculating a cross-correlation function of other channel signals and the reference channel signal, performing coarse estimation by searching a peak point of the amplitude of the cross-correlation function, and performing fine estimation on the peak position by using a parabola interpolation method to obtain the delay time of each channel relative to the reference channel; designing an FIR fractional delay filter; digital filtering and phase calibration; verifying a calibration effect; and calculating the phase of each channel signal at the target frequency point after calibration, and counting the standard deviation of each channel signal so as to evaluate the improvement degree of phase consistency. The method aims at overcoming the defect that traditional integral multiple sampling delay correction precision is insufficient, high-precision phase compensation of a sub-sampling point level is achieved, and therefore the performance of algorithms such as beam forming of a multi-channel sonarsystem is remarkably improved.
The invention relates to a multi-beam IQ data synchronization method based on source end pre-bias and receiving end shallow cache. The method comprises the following steps that: a receiving end measures round-trip delay of an optical link and calculates a pre-bias containing integer and decimal components; the sending end adjusts a buffer read pointer and controls a digital fractional delay filter to perform source end compensation; and a receiving end absorbs residual jitter by using a shallow-depth elastic buffer unit, and uniformly triggers reading after a full link is ready. The method has the advantages that the resource consumption of the receiving end is greatly reduced, the certainty low time delay is ensured, the dynamic thermal drift compensation is supported, and the high-precision sample point level alignment is realized.
A variable fractional delay FIR filter optimization design method based on an intelligent optimization algorithm comprises the steps that S1, the design problem of a Farrow structure variable fractional delay filter is converted into solving of two ill-conditioned linear equation sets; s2, solving the ill-conditioned linear equation set by adopting an improved principal component weighted iterative algorithm, wherein weighting factors of the principal component weighted algorithm are associated with optimization parameters through an exponential mapping relation; s3, constructing a collaborative optimization framework by utilizing a Runge-Kutta optimization algorithm, and performing joint optimization on parameters and orders of a filter by taking an error norm of a filter coefficient vector solution as an optimization target; and iteratively solving the ill-conditioned linear equation set to obtain an optimal filter coefficient sum, and completing the filter design. According to the method, the defect of high calculation complexity of a traditional linear programming method and a second-order cone programming method is overcome, the order of the filter is further optimized while the same performance is obtained, and 28% of hardware resources can be saved.
This invention relates to the field of digital signalprocessing technology and discloses a low-complexity, high-precision delay method based on polyphase filter interpolation, comprising: S1 designing a prototype low-pass filter; S2 performing polyphase decomposition on the interpolated filter, decomposing it into I-phase; S3 decomposing the fractional delay requirement of the input signal, with the integer part implemented through sampling period delay and the fractional part implemented through a fractional delay filter; S4 storing the coefficients of the I-phase filter as a coefficient array, and determining the delay interval of the virtual branch according to the input fractional delay parameters; S5 using polynomial interpolation to fit the filter coefficients of the virtual branch from the coefficient array, configuring them into an FIR filter to form a fractional delay filter; S6 designing the fractional delay filter as a high-speed parallel filter structure, converting serial computation into L-way parallel computation. This invention achieves high-precision variable fractional delay control with a low-complexity, low-computational-load configurable filter structure.
The invention discloses a variable fractional delay filter optimization method and system based on full coefficient compression. The method comprises the following steps: firstly, constructing a variable fractional delay filterfrequency response function based on a Farrow structure; then setting an amplitude constraint based on a variable amplitude response peak error and a delay constraint based on a variable fractional delay peak error; setting constraint parameters based on a full-coefficient compression L0 norm, constructing an optimization model based on a full-coefficient compression sensing L0 norm, and converting the optimization model into an L1 norm optimization model; and finally, solving a weighted L1 norm optimization problem to obtain an optimal variable fractional delay filter coefficient. The system is used for realizing the variable fractional delay filter optimization method based on full coefficient compression. According to the method, the variable fractional delay filter with the optimal amplitude error performance can be obtained under the condition of least resource and time consumption, the amplitude error performance of the system is optimized, and the method is suitable for the field of radarsignalprocessing.
A method for optimizing the design of a variable fractional delay (FIR) filter based on an intelligent optimization algorithm includes: S1 transforming the design problem of a Farrow structure FIR filter into solving two ill-conditioned linear equations; S2: using an improved principal component weighted iterative algorithm to solve the ill-conditioned linear equations, where the weighting factors of the principal component weighted algorithm are associated with the optimization parameters through an exponential mapping relationship; S3: constructing a collaborative optimization framework using the Runge-Kutta optimization algorithm, using the error norm of the filter coefficient vector solution as the optimization objective, and jointly optimizing the parameters and the filter order; iteratively solving the ill-conditioned linear equations to obtain the optimal sum of filter coefficients, thus completing the filter design. This invention overcomes the high computational complexity of traditional linear programming and second-order cone programming methods, and further optimizes the filter order while achieving the same performance, saving 28% of hardware resources.
A system may include an analog front-end circuit configured to receive signals from an antenna array and a digital circuit coupled to the analog front end. The digital circuit may include a digital beamforming circuit configured to include a Nyquist fractional delay filter that is piecewise continuous in the frequency domain. The Nyquist fractional delay filter may be implemented as a Gaussian Nyquist filter, a generalized raised cosine Nyquist filter, or another Nyquist filter. The fractional delay filter may be critically sampled and evaluated numerically or with a closed-form time-domain expression. The fractional delay filter may be part of a digital beamformingphased array antenna system.
The application discloses a high code rate narrow correlator generation method and device. It relates to the field of high-precision microwave two-way time synchronization. The application realizes the accurate generation of the leading and lagging codes by accurately delaying the generated local code sequence with a non-integer clock through a fractional delay filter, and solves the problem of generating a high code rate and low system sampling rate narrow correlator. The method comprises the following steps: storing a local code sequence in a logic device memory, wherein the local code sequence is a 0 / 1 level pseudo-random sequence; performing level conversion on the local code sequence, keeping the 1 level unchanged, and converting the 0 level into a-1 level; and performing fractional clockdelay on the local code sequence after the level conversion to obtain a leading sequence, an instant sequence and a lagging sequence; wherein the correlation interval between the leading sequence and the instant sequence and the correlation interval between the lagging sequence and the instant sequence are both 0.1 chips.
The invention relates to the field of electric energy metering, and particularly discloses a variable fractional delay filter based on a symmetric structure and a weighted least square method, and the filter comprises a signal parameter pre-calculation unit which is used for providing a delay parameter for the filter; the symmetric structure FIR coefficient construction unit is used for calculating a symmetric FIR coefficient framework; the WLS coefficient optimization unit is used for calculating a fixed-point optimization coefficient matrix; the phase shift execution unit is used for realizing integer delay of the current signal through a cache length and realizing fractional delay compensation of the voltagesignal through a VFD filter, and the integer delay and the fractional delay compensation cooperate to complete'integer + fractional 'joint phase shift; the self-adaptive calibration and frequency tracking unit is used for calculating an angular difference between the voltage and the current; and adding the calculated angular difference with an original phase shift angle to obtain an updated phase shift angle, and when it is detected that the absolute value of the difference value between the current fundamental frequency and the historical fundamental frequency is larger than a fundamental frequency fluctuation threshold value, synchronously updating the time delay integer part, the decimal delay and the current path signal cache length.