The embodiment of the invention provides a design method for a cascade filter, which comprises the following steps of: determining the interpolation times N of the filter; calculating the filter coefficient of a programmable finite impulse response (PFIR) filter, and obtaining a design scheme of a cascade combined filter of PFIR and cascaded integrator comb (CIC) filters; and when the interpolation times of the cascade combined filter of the PFIR and CIC filters does not reach the predetermined times, designing a half band (HB) filter, so that the filter performance of the cascade combined filter of the PFIR and CIC filters and the HB filter meets the interpolation times requirement of a system, and the design of the PFIR filter is realized by adopting a multistage design scheme. According to the embodiment provided by the invention, by adopting the design device for the multistage filter, the order of the designed filter is in a realizable range of the FPGA, and the indexes such as interpolation times of signals, error vector magnitude (EVM), adjacent channel power ratio (ACPR) and the like can meet the protocol requirement. Moreover, according to the technical scheme provided bythe invention, the resource consumption of the filter is also lower than that of the design method for the traditional filter, and the use of FPGA hardware resources can be effectively reduced.