158results about "Modulation transference" patented technology

A low noise block-downconverter system (LNB system) includes a local oscillator module having first and second phase locked loop circuitry (PLL circuitry) for downconverting an electrical signal to generate a downconverted signal. The first PLL circuitry receives a low-frequency reference signal that is used with an intermediate-frequency oscillator to generate an intermediate-frequency signal. The second PLL circuitry receives and uses the intermediate-frequency signal in conjunction with a high-frequency oscillator, separate from the intermediate-frequency oscillator, to generate a high-frequency signal. The high-frequency signal is used to downconvert the electrical signal. The signal dynamic range of the first PLL circuitry is higher than the signal dynamic range of the second PLL circuitry, thus achieving improved overall dynamic range for the LNB system. The first PLL circuitry may be a first integrated circuit defining a low phase-noise amplifier. A second integrated circuit may include the second PLL circuitry and the high-frequency oscillator.

The current-mode end-to-end signal path includes a digital-to-analog converter (DAC) operating in current mode and an upconverting mixer operating in current mode and operably coupled to the DAC, where analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

Technologies directed to a frequency multiplier circuit of a customer terminal (CT) for doubling and tripling a frequency of a local oscillator are described. One communication device includes a local oscillator (LO) to generate a first differential signal having a first frequency and a frequency multiplier circuit to generate a second differential signal having a second frequency that is double the first frequency or a third differential signal having a third frequency that is triple the first frequency. The frequency multiplier circuit includes a variable capacitance circuit that is programmable to one of multiple capacitances and a variable inductance circuit that is programmed to a first inductance for the second differential signal and to a second inductance for the third differential signal.

A matching network of a radio frequency signal, a mixer, a phase shifter, a radar sensor and an electronic apparatus. The matching network of the radio frequency signal includes a first inductor (L1) having an I input terminal, a second inductor (L2) having a Q input terminal, and a third inductor (L3) inductively coupled to both the first inductor and the second inductor, the third inductor has an output terminal; wherein the I input terminal is configured to receive a radio frequency signal of an I channel, and the Q input terminal is configured to receive a radio frequency signal of a Q channel.

A circuit to detect faults in a MEMS device (2) including a mass (3) that oscillates periodically, which receives a position signal (px[n]) formed by a succession of samples of an analog signal (px(t)) that is a function of the position of the mass (3) and has an amplitude and an oscillation frequency. The circuit includes: a reference stage (32) that generates a first reference signal (xref[n]) and a second reference signal (yref[n]) formed by successions of samples of a first sinusoidal signal and a second sinusoidal signal, respectively, with a frequency equal to the oscillation frequency and phase-shifted by 90°; a first multiplier (34) and a second multiplier (36), which generate, respectively, a first product signal (y[n]) and a second product signal (y[n], x[n]) via multiplication of the position signal by the first reference signal and the second reference signal, respectively; a first filter (40) and a second filter (42) of a lowpass type, which filter, respectively, the first and second product signals (y[n], x[n]) and generate a first filtered signal (YLPF[n]) and a second filtered signal (XLPF[n]); an estimator stage (46), which determines estimates of the amplitude, as a function of the first and second filtered signals (YLPF[n], XLPF[n]); and a decision stage (48), which compares the estimates with a range of values and detects the presence of faults on the basis of the outcomes of the comparisons.

A phase shifter including: an upconversion mixer configured to receive a local oscillator (LO) signal having a LO frequency, and configured to receive and multiply a radio frequency (RF) input signal with the LO signal to produce a modulated signal having two sidebands around the LO frequency, an intermediate IF sideband having frequency below the LO and an image sideband; a filter connected to and configured to receive the modulated signal from the upconversion mixer and to attenuate a range of frequencies corresponding to the image sideband to select and output the intermediate frequency (IF) sideband signal; and a downconversion mixer configured to receive and multiply the IF sideband signal with a phase shifted LO signal to produce an output signal including a phase shifted version of the RF input signal.

One or more systems, devices, or methods of use, or combinations thereof, provided herein relate to a device that can support signal generation. The current-mode end-to-end signal path can include a digital-to-analog converter (DAC) operating in a current mode and an up-converting mixer operating in a current mode and operably coupled to the DAC. The analog inputs and analog outputs of the DAC and the up-converting mixer can be represented as currents, and the DAC can generate a baseband signal. The DAC and the up-converting mixer can each comprise the same type of switching transistor, such as a p-type metal-oxide semiconductor (PMOS) switching transistor. In one or more embodiments, a current source and a diode-connected transistor can be placed in parallel in the current-mode signal path, with the current source passing a static current, while the diode-connected transistor passing both the static and dynamic currents.

Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly, to wireless transmitters. One example apparatus generally includes: an in-phase direct-current (DC) level shifter; a quadrature DC level shifter; an in-phase voltage-to-current (V2I) converter having an input coupled to an output of the in-phase DC level shifter; a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter; a bias control circuit having inputs coupled to the in-phase V2I converter and the quadrature V2I converter, an output of the bias control circuit being coupled to at least one of the in-phase DC level shifter or the quadrature DC level shifter; an in-phase mixer having an input coupled to an output of the in-phase V2I converter; and a quadrature mixer having an input coupled to an output of the quadrature V2I converter.

Certain aspects of the present disclosure generally relate to radio frequency (RF) front-end circuit systems. For example, certain aspects provide a device having a first converter circuit and a second converter circuit, the first converter circuit being configured to up-convert a first baseband (BB) signal to a first radio frequency (RF) signal based on an operating mode, and the second converter circuit being configured to up-convert a second BB signal to a second RF signal based on an operating mode. The device also includes a first RF weight adjustment circuit and a controller, the first RF weight adjustment circuit being configured to selectively apply an amplitude weight or a phase weight to at least one of the first RF signal or the second RF signal based on an operating mode, and the controller being configured to control a power state of the second converter circuit according to the operating mode.

The invention provides a large dynamic receiving and processing system and method for ADS-B receiving signals, relates to the technical field of avionics communication, and solves the problem of how to realize receiving of ADS-B IN signals in a 84dBm large dynamic range. In the system, an upper channel receiving circuit and a lower channel receiving circuit both receive input of ADS-B IN signals, and the input of the ADS-B IN signals is transmitted to an AD processing unit after being amplified; the upper channel receiving circuit preprocesses a signal part with a first dynamic range in an ADS-B IN signal, and the lower channel receiving circuit preprocesses a signal part with a second dynamic range in the ADS-B IN signal; the upper limit value of the first dynamic range is within the second dynamic range or is equal to the lower limit value of the second dynamic range; the AD processing unit is used for selecting, fusing and outputting the signals from the two types of receiving circuits; according to the invention, a domestic, autonomous and controllable received signal large dynamic range processing scheme is successfully realized.

An electronic device may include an antenna, a receiver, and a transmission line path that couples the antenna to the receiver. A peak detector may receive a radio-frequency signal from the transmission line path and may output a DC voltage indicative of a peak voltage level of the signal. The peak detector may include a pair of square law transistors having source-drain terminals coupled to an output of the peak detector. The peak detector may include a differential pair of transistors coupled between a power supply voltage and the output. The peak detector may include diode-connected transistors coupled between the source-drain terminals and gate terminals of the square law transistors. The diode-connected transistors may cause noise current to flow along feedback loop paths from the source-drain terminals onto the gate terminals of the square law transistors. This may remove noise from the output of the peak detector.

The present invention belongs to the technical field of hardware platform design, and more particularly, relates to a hardware design method for an integrated distance sensing and communication system. The present invention proposes an integrated communication and distance sensing platform that uses a high-isolation radio frequency switch to switch mixer inputs. By switching the mixer reference signal inputs of the transmitting and receiving parts of each communicating party, three modes, namely communication, distance sensing master, and distance sensing slave, are implemented. Compared with the prior art, the hardware design method of the present invention can rationally utilize existing resources to complete multiple functions.

To provide a receiver.SOLUTION: A receiver according to the present invention includes: an I branch including an I branch mixer that down-converts an RF (radio frequency) signal and outputs an I component and an I branch channelization filter that separates a baseband signal from the output signal of the I branch mixer; a Q branch including a Q branch mixer that down-converts the RF signal and outputs a Q component and a Q branch channelization filter that separates the baseband signal from the output signal of the Q branch mixer; a frequency-dependent mismatch estimator that calculates frequency-dependent mismatch between the I branch and the Q branch; and a frequency-dependent mismatch compensation unit that compensates for the frequency-dependent mismatch between the I branch and the Q branch on the basis of the calculation result of the frequency-dependent mismatch estimator.SELECTED DRAWING: Figure 1

The present application discloses an equalizer circuit, which includes a current source module, an RC network, and a differential transistor pair, the current source module being electrically connected to the RC network, the RC network being electrically connected to the differential transistor pair, the equalizer circuit further including an adjustable active inductor module electrically connected to the first transistor and the second transistor in the differential transistor pair, respectively, and a control module electrically connected to the current source module, the RC network, and the adjustable active inductor module, respectively, for adjusting the performance parameters of the current source module, the RC network, and the adjustable active inductor module to change the frequency of the dominant pole and the non-dominant pole of the equalizer circuit. The equalizer circuit can obtain compensation curves for different frequency peaking, and can well and harmoniously solve the channel compensation problem in different protocols and different rates, solving the problem that the gain boost of each frequency peaking cannot be adjusted within 0-15 dB in the related art due to the channel attenuation to be compensated by the equalizer being different in different protocols and different rates.

The present invention relates to the technical field of wireless communications, and provides a communication circuit, method, apparatus, and system. The communication circuit comprises a modulation element, an energy convergence network, and a second resonant network. The modulation element disperses energy of a first microwave signal at a first frequency at a first port and transmits same to an energy network via a second port. The energy convergence network converges the dispersed energy to obtain a second microwave signal. The second resonant network performs secondary frequency selection on the second microwave signal and generates an oscillation signal at a second resonant frequency, and transmits the oscillation signal to the modulation element via a third port to mix with the first microwave signal, thereby obtaining a frequency-converted signal at a second frequency. The present invention provides multiple signal transmission paths from the energy convergence network to the second resonant network that bypass the modulation element, thereby reducing the loss of the second microwave signal and acquiring a frequency-converted signal with increased power, and correspondingly lowering the transmit power requirements of a transceiver apparatus and the microwave drive power threshold of the communication circuit.

This modulator comprises: a carrier signal generation unit that outputs a carrier signal; and a plurality of modulation units which are cascade-connected downstream from the carrier signal generation unit and into which transmission signals of mutually different frequencies are input. Each of the modulation units comprises a distribution unit, a multiplication unit, a multiplexing unit, and a phase adjustment unit. The distribution unit outputs a first signal and a second signal obtained by bifurcating one carrier signal output by the carrier signal generation unit located upstream or one signal output by another modulation unit located upstream. The multiplication unit multiplies the first signal by the transmission signal inputted into the corresponding modulation unit. The multiplexing unit multiplexes the first signal which the multiplication unit multiplied by the transmission signal with the second signal which was output by the distribution unit, and outputs the resulting multiplexed signal. The phase adjustment unit rotates the phase of the first signal output from the distribution unit to the multiplication unit or the phase of the second signal output from the distribution unit to the multiplexing unit.

A low noise block-downconverter system (LNB system) includes a local oscillator module having first and second phase locked loop circuitry (PLL circuitry) for downconverting an electrical signal to generate a downconverted signal. The first PLL circuitry receives a low-frequency reference signal that is used with an intermediate-frequency oscillator to generate an intermediate-frequency signal. The second PLL circuitry receives and uses the intermediate-frequency signal in conjunction with a high-frequency oscillator, separate from the intermediate-frequency oscillator, to generate a high-frequency signal. The high-frequency signal is used to downconvert the electrical signal. The signal dynamic range of the first PLL circuitry is higher than the signal dynamic range of the second PLL circuitry, thus achieving improved overall dynamic range for the LNB system. The first PLL circuitry may be a first integrated circuit defining a low phase-noise amplifier. A second integrated circuit may include the second PLL circuitry and the high-frequency oscillator.

A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.

An electronic device applies a frequency offset function to a first signal having a first frequency. The device includes a delay element configured to output a second signal corresponding to the first signal delayed by a duration equal to a first period of said signal divided by four. A circuit branch includes a first circuit configured to divide the frequency of the first signal by a given number coupled in series with a second circuit configured to implement an integration. The circuit branch outputs a third signal and a fourth signal. A single side band mixing circuit processes the first signal, second signal, third signal and fourth signal to generate an output signal.

An NPF radiofrequency device includes a first end terminal E1, four first branches BR10, BR11, BR12, BR13 connected to E1 and each including a capacitor, respectively C0, C1, C2, C3, having the same capacitance, including a first terminal and a second terminal connected to ground, and a switch arranged between E1 and the first terminal of the capacitor of the first branch; the device being designed to, in each first branch BR1i, close the switch at each time pT0+(i)T0 / 4, for T0 / 4, where p is a natural number and T0 is the period of the clock signal; the device including at least two successive second branches from among an ordered set of second branches BR20, BR21, BR22, BR23, the second branch BR2i including a second end terminal E2i, and each second branch BR2k of the device including, for each first branch, BR11, i=0 to 3, a switch between the first terminal of the capacitor Ci and the second branch, the device being designed to close the switch at each pT0+(i+k)T0 / 4, for T0 / 4.

Embodiments of this application provide a communication apparatus and a communication method. The communication apparatus is configured to receive a first signal and a second signal from a same device, and the second signal indicates the communication apparatus to enter a connected state. The communication apparatus includes a first branch and a second branch. The first branch includes a first frequency-amplitude converter, configured to obtain first amplitude information of a third signal, where the third signal is a signal obtained by performing frequency mixing on the first signal and a first local oscillator signal. The second branch is configured to demodulate a fourth signal, where the fourth signal is a signal obtained by performing frequency mixing on the second signal and a second local oscillator signal, the second local oscillator signal is a signal obtained by performing frequency offset correction on the first local oscillator signal based on the first amplitude information, the second branch includes a second frequency-amplitude converter, and a linear working interval of the second frequency-amplitude converter is smaller than a linear working interval of the first frequency-amplitude converter. In this way, signal demodulation performance of the communication apparatus can be improved.

A high-frequency signal is input to a first node. A high-frequency signal is output from each of a plurality of second nodes. A first branch transmission line connects the first node to each of the plurality of second nodes. The first branch transmission line includes a plurality of cascade-connected dividers, each of which has one input node and two output nodes. At least one of the dividers is an unequal divider with a distribution ratio of 2 or less. The first branch transmission line is configured to equally divide a high-frequency power input to the first node to the plurality of second nodes.

An apparatus such as a user equipment configured to support an irregular bandwidth signal. The apparatus comprising multiple means for frequency translating a wireless communication signal in a frequency bandwidth that is different to a predefined bandwidth and for filtering said frequency translated wireless communication signals. Means for adjusting a centre frequency used by the multiple means for frequency translating; and control means. The control means being responsive to receipt of a signal indicating a wireless communication network is currently supporting an irregular channel bandwidth, said irregular channel bandwidth covering two partially overlapping regular channel bandwidths each having said predefined bandwidth, to route a received wireless communication signal to each of the multiple means for frequency translating and to control the means for adjusting to set a respective centre frequency of the multiple means for frequency translating such that said centre frequency of each of the multiple means for frequency translating is offset with respect to each other

The present invention provides a filter configured to receive an input signal to generate a filtered signal. The filter includes a first component, a first capacitor and a second component. The first component is coupled between the input signal and a first terminal. The first capacitor is coupled between the first terminal and a second terminal. For the second component, a first node of the second component is coupled to the second terminal, and a second node of the second component is used to output the filtered signal. The first component and the second component are inductive components.

A pulse generation circuit in a quantum controller operates synchronously with a pulse computation circuit. The pulse generation circuit generates a pulse associated with a quantum element operation. The pulse computation circuit is able to determine characteristics of a signal that is based on the pulse. These characteristics are used by the pulse generation circuit to modify the pulse.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

An example of a receiver circuit is disclosed. The receiver circuit comprises an input for receiving a radio frequency signal, an output for providing an output signal of the receiver circuit, a receive path, wherein the receive path is connected between the input and the output of the receiver circuit, and a feedback path, wherein an input of the feedback path is connected to the output of the receiver circuit. The receiver circuit also comprises a transformer, wherein an output signal of the feedback path is combined with the received radio frequency signal in the receive path to form a first signal. The receive path comprises a first mixer for downconverting the first signal by a local oscillator frequency, and an amplifier for amplifying the downconverted first signal. The feedback path comprises a second mixer for upconverting a signal in the feedback path by said local oscillator frequency. The combination of the output signal of the feedback path with the received radio frequency signal is achieved by means of the transformer.

Embodiments of the present disclosure relate to electronic devices that form digital-to-analog converters and mixers. An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. A first processing stage and a second processing stage receive the first digital signal and the second digital signal and generate therefrom a first analog signal and a second analog signal using a first complementary clock signal and a second complementary clock signal in time. An output stage generates an internal clock signal equivalent to one of the following: a first clock signal that is phase-shifted by the duration of a transient that occurs during a period of the first clock signal, or a second clock signal that is phase-shifted by the duration of a transient that occurs during a period of the second clock signal. When the internal clock signal is at a first logic level, the output stage generates an analog output signal equal to the first analog signal, and when the internal clock signal is at a second logic level, the output stage generates an analog output signal equal to the second analog signal.

A multi-path radio frequency (RF) system includes a reference oscillation circuit, a local oscillation (LO) generator circuit, and mixer circuits. The reference oscillation circuit generates a reference oscillation signal. The LO generator circuit receives the reference oscillation signal, and generates LO signals according to the reference oscillation signal, where a frequency of the reference oscillation signal is a non-integer multiple of a frequency of at least one of the LO signals. The mixer circuits are located on different signal paths, respectively, and used to receive the LO signals from the LO generator circuit, respectively.