112results about "Modulation transference" patented technology

The current-mode end-to-end signal path includes a digital-to-analog converter (DAC) operating in current mode and an upconverting mixer operating in current mode and operably coupled to the DAC, where analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

Technologies directed to a frequency multiplier circuit of a customer terminal (CT) for doubling and tripling a frequency of a local oscillator are described. One communication device includes a local oscillator (LO) to generate a first differential signal having a first frequency and a frequency multiplier circuit to generate a second differential signal having a second frequency that is double the first frequency or a third differential signal having a third frequency that is triple the first frequency. The frequency multiplier circuit includes a variable capacitance circuit that is programmable to one of multiple capacitances and a variable inductance circuit that is programmed to a first inductance for the second differential signal and to a second inductance for the third differential signal.

A phase shifter including: an upconversion mixer configured to receive a local oscillator (LO) signal having a LO frequency, and configured to receive and multiply a radio frequency (RF) input signal with the LO signal to produce a modulated signal having two sidebands around the LO frequency, an intermediate IF sideband having frequency below the LO and an image sideband; a filter connected to and configured to receive the modulated signal from the upconversion mixer and to attenuate a range of frequencies corresponding to the image sideband to select and output the intermediate frequency (IF) sideband signal; and a downconversion mixer configured to receive and multiply the IF sideband signal with a phase shifted LO signal to produce an output signal including a phase shifted version of the RF input signal.

Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly, to wireless transmitters. One example apparatus generally includes: an in-phase direct-current (DC) level shifter; a quadrature DC level shifter; an in-phase voltage-to-current (V2I) converter having an input coupled to an output of the in-phase DC level shifter; a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter; a bias control circuit having inputs coupled to the in-phase V2I converter and the quadrature V2I converter, an output of the bias control circuit being coupled to at least one of the in-phase DC level shifter or the quadrature DC level shifter; an in-phase mixer having an input coupled to an output of the in-phase V2I converter; and a quadrature mixer having an input coupled to an output of the quadrature V2I converter.

Certain aspects of the present disclosure generally relate to radio frequency (RF) front-end circuit systems. For example, certain aspects provide a device having a first converter circuit and a second converter circuit, the first converter circuit being configured to up-convert a first baseband (BB) signal to a first radio frequency (RF) signal based on an operating mode, and the second converter circuit being configured to up-convert a second BB signal to a second RF signal based on an operating mode. The device also includes a first RF weight adjustment circuit and a controller, the first RF weight adjustment circuit being configured to selectively apply an amplitude weight or a phase weight to at least one of the first RF signal or the second RF signal based on an operating mode, and the controller being configured to control a power state of the second converter circuit according to the operating mode.

An electronic device may include an antenna, a receiver, and a transmission line path that couples the antenna to the receiver. A peak detector may receive a radio-frequency signal from the transmission line path and may output a DC voltage indicative of a peak voltage level of the signal. The peak detector may include a pair of square law transistors having source-drain terminals coupled to an output of the peak detector. The peak detector may include a differential pair of transistors coupled between a power supply voltage and the output. The peak detector may include diode-connected transistors coupled between the source-drain terminals and gate terminals of the square law transistors. The diode-connected transistors may cause noise current to flow along feedback loop paths from the source-drain terminals onto the gate terminals of the square law transistors. This may remove noise from the output of the peak detector.

The present invention belongs to the technical field of hardware platform design, and more particularly, relates to a hardware design method for an integrated distance sensing and communication system. The present invention proposes an integrated communication and distance sensing platform that uses a high-isolation radio frequency switch to switch mixer inputs. By switching the mixer reference signal inputs of the transmitting and receiving parts of each communicating party, three modes, namely communication, distance sensing master, and distance sensing slave, are implemented. Compared with the prior art, the hardware design method of the present invention can rationally utilize existing resources to complete multiple functions.

To provide a receiver.SOLUTION: A receiver according to the present invention includes: an I branch including an I branch mixer that down-converts an RF (radio frequency) signal and outputs an I component and an I branch channelization filter that separates a baseband signal from the output signal of the I branch mixer; a Q branch including a Q branch mixer that down-converts the RF signal and outputs a Q component and a Q branch channelization filter that separates the baseband signal from the output signal of the Q branch mixer; a frequency-dependent mismatch estimator that calculates frequency-dependent mismatch between the I branch and the Q branch; and a frequency-dependent mismatch compensation unit that compensates for the frequency-dependent mismatch between the I branch and the Q branch on the basis of the calculation result of the frequency-dependent mismatch estimator.SELECTED DRAWING: Figure 1

The present invention relates to the technical field of wireless communications, and provides a communication circuit, method, apparatus, and system. The communication circuit comprises a modulation element, an energy convergence network, and a second resonant network. The modulation element disperses energy of a first microwave signal at a first frequency at a first port and transmits same to an energy network via a second port. The energy convergence network converges the dispersed energy to obtain a second microwave signal. The second resonant network performs secondary frequency selection on the second microwave signal and generates an oscillation signal at a second resonant frequency, and transmits the oscillation signal to the modulation element via a third port to mix with the first microwave signal, thereby obtaining a frequency-converted signal at a second frequency. The present invention provides multiple signal transmission paths from the energy convergence network to the second resonant network that bypass the modulation element, thereby reducing the loss of the second microwave signal and acquiring a frequency-converted signal with increased power, and correspondingly lowering the transmit power requirements of a transceiver apparatus and the microwave drive power threshold of the communication circuit.

A low noise block-downconverter system (LNB system) includes a local oscillator module having first and second phase locked loop circuitry (PLL circuitry) for downconverting an electrical signal to generate a downconverted signal. The first PLL circuitry receives a low-frequency reference signal that is used with an intermediate-frequency oscillator to generate an intermediate-frequency signal. The second PLL circuitry receives and uses the intermediate-frequency signal in conjunction with a high-frequency oscillator, separate from the intermediate-frequency oscillator, to generate a high-frequency signal. The high-frequency signal is used to downconvert the electrical signal. The signal dynamic range of the first PLL circuitry is higher than the signal dynamic range of the second PLL circuitry, thus achieving improved overall dynamic range for the LNB system. The first PLL circuitry may be a first integrated circuit defining a low phase-noise amplifier. A second integrated circuit may include the second PLL circuitry and the high-frequency oscillator.

A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.

An electronic device applies a frequency offset function to a first signal having a first frequency. The device includes a delay element configured to output a second signal corresponding to the first signal delayed by a duration equal to a first period of said signal divided by four. A circuit branch includes a first circuit configured to divide the frequency of the first signal by a given number coupled in series with a second circuit configured to implement an integration. The circuit branch outputs a third signal and a fourth signal. A single side band mixing circuit processes the first signal, second signal, third signal and fourth signal to generate an output signal.

An NPF radiofrequency device includes a first end terminal E1, four first branches BR10, BR11, BR12, BR13 connected to E1 and each including a capacitor, respectively C0, C1, C2, C3, having the same capacitance, including a first terminal and a second terminal connected to ground, and a switch arranged between E1 and the first terminal of the capacitor of the first branch; the device being designed to, in each first branch BR1i, close the switch at each time pT0+(i)T0 / 4, for T0 / 4, where p is a natural number and T0 is the period of the clock signal; the device including at least two successive second branches from among an ordered set of second branches BR20, BR21, BR22, BR23, the second branch BR2i including a second end terminal E2i, and each second branch BR2k of the device including, for each first branch, BR11, i=0 to 3, a switch between the first terminal of the capacitor Ci and the second branch, the device being designed to close the switch at each pT0+(i+k)T0 / 4, for T0 / 4.

A high-frequency signal is input to a first node. A high-frequency signal is output from each of a plurality of second nodes. A first branch transmission line connects the first node to each of the plurality of second nodes. The first branch transmission line includes a plurality of cascade-connected dividers, each of which has one input node and two output nodes. At least one of the dividers is an unequal divider with a distribution ratio of 2 or less. The first branch transmission line is configured to equally divide a high-frequency power input to the first node to the plurality of second nodes.

An apparatus such as a user equipment configured to support an irregular bandwidth signal. The apparatus comprising multiple means for frequency translating a wireless communication signal in a frequency bandwidth that is different to a predefined bandwidth and for filtering said frequency translated wireless communication signals. Means for adjusting a centre frequency used by the multiple means for frequency translating; and control means. The control means being responsive to receipt of a signal indicating a wireless communication network is currently supporting an irregular channel bandwidth, said irregular channel bandwidth covering two partially overlapping regular channel bandwidths each having said predefined bandwidth, to route a received wireless communication signal to each of the multiple means for frequency translating and to control the means for adjusting to set a respective centre frequency of the multiple means for frequency translating such that said centre frequency of each of the multiple means for frequency translating is offset with respect to each other

The present invention provides a filter configured to receive an input signal to generate a filtered signal. The filter includes a first component, a first capacitor and a second component. The first component is coupled between the input signal and a first terminal. The first capacitor is coupled between the first terminal and a second terminal. For the second component, a first node of the second component is coupled to the second terminal, and a second node of the second component is used to output the filtered signal. The first component and the second component are inductive components.

A pulse generation circuit in a quantum controller operates synchronously with a pulse computation circuit. The pulse generation circuit generates a pulse associated with a quantum element operation. The pulse computation circuit is able to determine characteristics of a signal that is based on the pulse. These characteristics are used by the pulse generation circuit to modify the pulse.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

An example of a receiver circuit is disclosed. The receiver circuit comprises an input for receiving a radio frequency signal, an output for providing an output signal of the receiver circuit, a receive path, wherein the receive path is connected between the input and the output of the receiver circuit, and a feedback path, wherein an input of the feedback path is connected to the output of the receiver circuit. The receiver circuit also comprises a transformer, wherein an output signal of the feedback path is combined with the received radio frequency signal in the receive path to form a first signal. The receive path comprises a first mixer for downconverting the first signal by a local oscillator frequency, and an amplifier for amplifying the downconverted first signal. The feedback path comprises a second mixer for upconverting a signal in the feedback path by said local oscillator frequency. The combination of the output signal of the feedback path with the received radio frequency signal is achieved by means of the transformer.

A multi-path radio frequency (RF) system includes a reference oscillation circuit, a local oscillation (LO) generator circuit, and mixer circuits. The reference oscillation circuit generates a reference oscillation signal. The LO generator circuit receives the reference oscillation signal, and generates LO signals according to the reference oscillation signal, where a frequency of the reference oscillation signal is a non-integer multiple of a frequency of at least one of the LO signals. The mixer circuits are located on different signal paths, respectively, and used to receive the LO signals from the LO generator circuit, respectively.

The present invention belongs to the technical field of signal transmission, and discloses a remote transmission method and device based on a short-range transmission protocol data frame. The present invention performs digital design of digital signals by moving the high level of the idle period and the period of sending data 1 in the short-range transmission protocol data frame to the high-frequency digital carrier frequency for transmission, and not sending the digital carrier in the low-level period when sending data 0. The receiving end first samples the received modulated signal twice within a digital carrier cycle using a digital clock signal that is twice the digital carrier frequency of the transmitting end, and then performs an XOR operation on the two sampled values, thereby restoring the high level and low level in the short-range transmission protocol data frame, and realizing that the remote transmission signal receiving end directly demodulates the digital carrier signal without using relevant or non-related demodulation means and filters, thereby greatly simplifying the digital demodulation circuit.

Device comprising: a quadrature demodulator configured to receive an input signal, a first reference signal, and a second reference signal in quadrature with the first reference signal, the quadrature demodulator further configured to produce a plurality of output signals from the input signal and the first and second reference signals, the plurality of output signals indicative of the amplitude and phase of the input signal; one or more inverting circuits, the inverting circuits having a first and a second programmable output polarity, the plurality of output signals being output by the quadrature demodulator when the inverting circuits are set to the first programmable output polarity, the plurality of output signals being inverted and output by the quadrature demodulator when the inverting circuits are set to the second programmable output polarity, and a controller (508) coupled to the quadrature demodulator, the controller (508) being configured to determine the amplitude and phase of the input signal according to the plurality of output signals, the one or more inverting circuits being configured to be coupled to the controller (508), the controller (508) further being configured to set the inverting circuits to the first programmable output polarity while determining first values ​​of the plurality of output signals, set the inverting circuits to the second programmable output polarity while determining second values ​​of the plurality of output signals, and determine one or more error values ​​from the first and second values ​​of the plurality of output signals, the controller (508) further being configured toto determine the error values ​​by subtracting the first values ​​of the plurality of output signals from the second values ​​of the plurality of output signals, wherein determining comprises subtracting the second values ​​of the plurality of output signals from respective ones of the first values ​​of the plurality of output signals to produce the one or more error values.

This application provides a radio frequency receive circuit, a receiver, and an electronic device, to reduce interference of noise to a first voltage signal, improve a signal-to-noise ratio of the first voltage signal, and implement wide-range switching between a high gain and a low gain of a second radio frequency signal through a gain adjustment circuit, thereby expanding an application scope of the radio frequency receive circuit. The radio frequency receive circuit may include a coupling circuit, the gain adjustment circuit, and a dual balanced frequency mixer. The coupling circuit may be configured to: convert a first radio frequency signal into at least two second radio frequency signals, and output the at least two second radio frequency signals to the gain adjustment circuit. The gain adjustment circuit may be configured to: selectively amplify or attenuate a gain of each second radio frequency signal, and output at least two third radio frequency signals to the dual balanced frequency mixer. The dual balanced frequency mixer may be configured to mix the at least two third radio frequency signals based on a local oscillation signal.

Provided is an array antenna device that can be used in a 300 GHz band. An array antenna device 100 comprises: a first layer 10 in which a plurality of antenna elements 11 are arranged in a grid shape; and a second layer 20 stacked on the first layer 10. The second layer 20 includes: a plurality of mixers 21 that are arranged in a plurality of grid regions 30 overlapping the plurality of antenna elements 11 in plan view, that each include an LO signal terminal 23, an IF signal terminal 24, and an RF signal terminal 22, with the RF signal terminals 22 electrically connected to the plurality of antenna elements 11; a plurality of LO signal lines 25 which are provided to respective columns of the plurality of mixers 21 and to each of which the LO signal terminals of mixers 21 of the same column are commonly connected; and a plurality of IF signal lines 27 that are provided to respective rows of the plurality of mixers 21 and to each of which the IF signal terminals of mixers 21 of the same row are commonly connected.

Passive IQ Mixer with Improved Conversion Gain This description relates to an IQ mixer (12) comprising a mixing stage (18) including a first mixer (MixI) and a second mixer (MixQ), and a first inductive block (BI) connected to the first mixer (MixI) and including at least one first inductive component, and a second inductive block (BQ) connected to the second mixer (MixQ) and including at least one second inductive component. Figure for the abbreviation: Fig. 4

A system for reference clock frequency correction is described. The system comprises a compensation module configured to (i) receive, as input, an oscillator signal and one or more control signals, (ii) generate a compensation signal based on the oscillator signal and the one or more control signals, wherein the generated compensation signal is a discretized sinusoidal signal having a controllable frequency, and (iii) output the generated compensation signal. The system further comprises a mixer block configured to (i) receive, as input, the generated compensation signal and the oscillator signal, and (ii) generate an output clock signal by mixing the generated compensation signal with the oscillator signal. A soft-switching method to reduce the effect of quantization noise is further described.

The invention relates to a receiver system. There is provided a system comprising a plurality of receivers, each receiver comprising a local oscillator configured to generate a local oscillation signal; a primary mixer configured to mix an input signal with a reference signal at a reference frequency to generate a first output signal; a frequency divider configured to divide the reference signal into a second reference signal at a second frequency; and a secondary mixer coupled to the primary mixer and configured to mix the first output signal with a second reference signal at a second frequency. In the first mode, a reference signal of a first receiver in the plurality of receivers is a local oscillation signal from the first receiver; in the second mode, the reference signal is a local oscillation signal from another receiver of the plurality of receivers.

Receiving device, comprising: a frequency mixer (11) configured to mix a received signal input therein and a local signal generated by a local oscillator (12) in order to convert a frequency of the received signal into a baseband; an envelope demodulator (13) configured to perform an envelope demodulation of an output of the frequency mixer (11); an upper sideband demodulator (14) configured to demodulate only one upper sideband of an output from the frequency mixer (11) by single-sideband demodulation; a lower sideband demodulator (15) configured to demodulate only one lower sideband of the output from the frequency mixer (11) by single-sideband demodulation; a first adder (16) configured to add an output from the envelope demodulator (13) and a first inverted output obtained by inverting an output from the upper sideband demodulator (14); a second adder (17) configured to add the output from the envelope demodulator (13) and a second inverted output obtained by inverting an output from the lower sideband demodulator (15); and a third adder (18) configured to add the output from the envelope demodulator (13), a third inverted output obtained by inverting an output from the first adder, and a fourth inverted output obtained by inverting an output from the second adder to produce a demodulation signal.

Radio Frequency Device (10) of NPF type comprising a first end terminal E1, four first branches named BR10, BR11, BR12, BR13 connected to E1 and each comprising: a capacitor, respectively C0, C1, C2, C3, of the same capacitance, comprising a first terminal and a second terminal connected to ground, and a switch arranged between E1 and the first terminal of the capacitor of said first branch; said device (10) being adapted to, in each first branch BR1i, close the switch at each instant , during , with natural integer and period of the clock signal;the device comprising at least two successive second branches from an ordered set of second branches BR20, BR21, BR22, BR23, the second branch BR2i comprising a second end terminal E2i, and each second branch of the device BR2k comprising, for each first branch, BR1i, i = 0 to 3, a switch between the first terminal of the capacitor Ci and said second branch, said device being adapted to close said switch at each , during . Figure for the abstract: Fig. 6;