837 results about "Transconductance" patented technology

The invention provides a broadband low-noise amplifier based on a three-coil coupling transformer. The broadband low-noise amplifier comprises an input matching network, a common-source differential output driving stage amplifier, an inter-stage matching network, a common-source differential output power stage amplifier and an output matching network which are connected in sequence, broadband matching is realized by using the input matching network and the inter-stage matching network, and the effective transconductance of the transistor is improved; through the cross-coupled capacitors, the LNA gain and stability on a broadband are improved, better isolation is realized, and input and output are decoupled; due to the design of the grounding capacitor, the linearity of the LNA is improved; through the combination of the three-coil coupling transformer and the differential topology, output signals are superposed in the same direction at the output end, and noise is cancelled in the reverse direction at the output end, so that the thermal noise is greatly inhibited, the isolation is improved through the output matching network, the insertion loss is reduced, and the output matching performance is optimized.

The invention relates to the technical field of integrated circuit design, and particularly discloses a low-noise programmable amplifier, which comprises a first fully-differential amplifier, a second fully-differential amplifier, a third fully-differential amplifier and a fourth fully-differential amplifier, the second fully differential amplifier comprises a pair of differential input ends and is electrically connected with the first fully differential amplifier through an interstage chopper switch; a pair of input chopping switches, wherein the input end of each input chopping switch is electrically connected with a differential input signal; the output end of each output chopping switch is electrically connected with the output end of the second fully differential amplifier; the input capacitance network is positioned between the pair of input chopping switches and the two pairs of differential input ends; the feedback capacitance network is positioned between the pair of output chopping switches and the two pairs of differential input ends; and the plurality of zeroing switches are positioned between the input and the output of the first fully differential amplifier. The two transconductance amplifiers in the first fully-differential amplifier share the same current, the overall transconductance is doubled compared with single-pair differential input, and the noise of the amplifier is reduced.

A calibration circuit includes a replica transconductance stage that is a replica of a transconductance amplifier in a serializer / deserializer (SerDes) interface and a replica transimpedance stage that is a replica of a transimpedance amplifier in the SerDes interface. The replica transimpedance stage has an input coupled to its output. A comparison circuit is configured to generate a difference signal representative of a difference between voltage levels of an input signal received at an input of the replica transconductance stage and an output signal representative of voltage level at the output of the replica transimpedance stage. Replica feedback resistors are configured to couple an output of the replica transimpedance stage to the input of the replica transconductance stage. The difference signal can be used to select resistance values provided by the replica feedback resistors and by corresponding gain control resistors in the transimpedance amplifier in the SerDes interface.

The embodiment of the invention discloses a load transient enhancement circuit of a voltage mode DCDC converter, which is characterized in that a traditional 3-type compensation network is improved, a zero-point adjustable compensation network is generated by a compensation transconductance amplifier to carry out loop compensation, and then zero-point adjustment is carried out by detecting output voltage. When the output voltage exceeds the threshold due to the overshoot current, the transconductance can be increased through the change of the tail current, so that the zero point moves to the low frequency, the bandwidth can be increased, and the transient response capability is improved. According to the embodiment of the invention, a zero point adjustable compensation network is generated by adding a feedback path to compensate the loop, and the adjustable zero point is adjusted by detecting the output voltage. And when the load jumps, the bandwidth is increased to low frequency through zero point shift, so that the load response capability is enhanced, and the overshoot of the output voltage is reduced.

The invention belongs to the technical field of semiconductor devices, and particularly relates to a high-heat-dissipation GaN nanowire radio frequency device and a preparation method thereof.The radio frequency device comprises a heterogeneous bonding substrate, a bonding middle layer, an AlGaN / GaN nanowire (a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a GaN cap layer), a passivation layer and an electrode layer, and the electrode layer comprises a source electrode, a gate electrode and a drain electrode; the passivation layer covers the gaps between the nanowires through front deposition, so that the preparation of the high-heat-dissipation nanowire transistor is realized, and the problem that the linearity of the device is reduced due to a self-heating effect is solved; holes are formed in the grid electrode, the thickness of the passivation layer on each nanowire is controlled, equal difference distribution is achieved, the linearity of the device is improved through the transconductance compensation effect, the grid voltage swing of the radio frequency device can be effectively improved, and therefore the available range of the device is greatly widened.

An even harmonic multiplier employing complementary current reuse is disclosed. The even harmonic multiplier employs supply voltage and current density scaling to reduce power consumption. Further, by using complimentary NMOS and PMOS transistors, the even harmonic multiplier achieves high areal efficiency. Current reuse causes a reduction in noise at the first harmonic, as the corresponding first harmonic currents from the NMOS and PMOS transistors are in opposite, i.e., canceling, directions. Complementary current reuse is now feasible, as the performance of PMOS transistors at current process nodes is similar to those of NMOS transistors, with appropriate sizing leading to approximately equivalent transconductances. Multiple even harmonic multiplier configurations are possible, with many using transformer circuits at the input and / or the output. The resultant even harmonic multipliers find ready application in millimeter wave radio frequency receivers. The most common even harmonic multiplier is a frequency doubler, which produces a strong second harmonic signal.

A monitoring device is provided. The monitoring device comprises one or more circuitry operable to obtain measurements of one or more pins of a battery system, the one or more circuitry comprising at least one circuit for monitoring current, which comprise: at least one other circuit for amplifying variance comprising at least one differential amplifier, one voltage reference in electrical connection with a first input of the differential amplifier; at least one transconductance means comprising at least one output in electrical connection with a second input of the differential amplifier and at least one input in electrical connection with an output of the differential amplifier; at least one current source in electrical connection with at least one output of the at least one transconductance means; and an output in electrical connection with at least one output of the at least one transconductance means.

A circuit to suppress ringing in a Controller Area Network (CAN) bus having a CAN high (CANH) wire and a CAN low (CANL) wire is provided. The circuit may include processing circuitry to generate a CAN control signal, and a transconductance amplifier to receive a first input signal corresponding to the CAN control signal and a voltage signal from the CANL wire, and to generate an output current signal based on a difference between the first input signal and the voltage signal from the CANL wire. An output terminal of the transconductance amplifier may be coupled to the CANH wire to source current to or sink current from the CANH wire.

The invention discloses a transient enhancement circuit applied to a COT mode buck converter in the technical field of integrated circuits, and the transient enhancement circuit comprises an output voltage sampling circuit and a fully differential transconductance amplifier GM. The input end of the output voltage sampling circuit is connected with the output end of the COT mode buck converter; the output voltage sampling circuit is used for sampling an output voltage signal of the COT mode buck converter and sending the sampled voltage signal to the input end of the fully differential transconductance amplifier GM. According to the invention, the transient enhancement circuit applied to the COT mode buck converter is introduced, so that the effective improvement on the up-down rush and the recovery time in the load switching process of the buck converter is realized, and the system is continuous and the system response is optimized by dynamically changing the conduction time.

The invention discloses an ultra-wideband low-noise amplifier based on a double-coupling structure, relates to the field of electronic devices, and is used for solving the problems of large occupied area and large noise coefficient of a distributed amplifier in the prior art. Comprising a broadband input matching network acting on a first-stage circuit, a transconductance enhancement coupling structure and an active bias structure; the parallel RC negative feedback structure and the series-parallel coupling inductance peaking structure act on the second-stage circuit; the transconductance enhancement coupling structure at least comprises a first transistor, a first microstrip line connected with a source electrode of the first transistor and a second microstrip line connected with a drain electrode of the first transistor, and the first microstrip line and the second microstrip line are mutually coupled. Part of drain electrode current signals are coupled to the source electrode to be secondarily amplified, the high-frequency gain of the first-stage circuit is effectively improved, post-stage noise can be restrained, meanwhile, minimum noise matching under high frequency is carried out through the source electrode degeneration inductor and the broadband input matching network, and the noise performance is excellent; and the area can be saved.

The invention provides a continuous time Sigma-Delta modulator with constant transconductance bias and negative resistance compensation. The continuous time Sigma-Delta modulator comprises a loop filter, a quantizer and a digital-to-analog converter, the loop filter is used for amplifying a signal in an effective signal bandwidth and attenuating an out-of-band signal at the same time, and the loop filter comprises a first-stage negative resistance compensation integrator and a second-stage negative resistance compensation integrator which are connected in sequence, the first-stage negative resistance compensation integrator comprises a first negative resistance unit containing a negative resistance of a constant transconductance bias circuit and a first integrator unit containing an operational amplifier, and a single operational amplifier resonator structure is formed to generate a second-order response; the integrator of the second-stage negative resistance compensation comprises a second negative resistance unit and a second integrator unit comprising an operational amplifier; and the quantizer is connected with the loop filter, adopts a successive approximation analog-to-digital converter, and is used for converting the analog voltage signal into a digital signal and outputting the digital signal. And the digital-to-analog converter is used for converting the digital signal into an analog signal and feeding back the analog signal to the loop filter.

AED pulse generation circuits that provide floating, adjustable, bias voltages for driving a solid-state defibrillation waveform therapy generator circuit are provided. The provided bias voltages allow to reverse polarity of provided electric shock to increase chances of successful defibrillation and survival. In one of the provided configurations, energy stored in the pulse capacitor can be discharged by activating the waveform therapy generator in the high-resistance transconductance region. The circuits can be positioned on a self-contained module potted with an insulating material to reduce unintended interactions with other AED components. Through the use of the disclosed circuits, AED size can be reduced to promote pocketability while simultaneously increasing AED reliability.

The invention discloses a continuous time linear equalizer which comprises a transconductance circuit, a transimpedance amplifier circuit and a common-mode voltage feedback circuit. The transconductance circuit comprises a pair of PMOS (P-channel Metal Oxide Semiconductor) tubes, a pair of NMOS (N-channel Metal Oxide Semiconductor) tubes, six current sources and two RC (Resistance-Capacitance) networks; two branches are arranged between the power supply and the ground. A grid electrode of the first PMOS tube is connected with a grid electrode of the first NMOS tube, a grid electrode of the second PMOS tube is connected with a grid electrode of the second NMOS tube, and the first PMOS tube and the second PMOS tube respectively receive a pair of differential input voltages. The drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and a pair of differential intermediate signals is output respectively. The circuit is simple in structure and only has a primary circuit; a complementary structure of PMOS input geminate transistors and NMOS input geminate transistors is adopted, bias current is utilized to the maximum extent, power consumption is low, and compared with a traditional circuit, the current utilization rate is improved; balancing of a wide frequency band can be realized under the condition of low power consumption, and the gain is high.

The invention discloses a high-speed and high-linearity margin amplifier and an analog-to-digital converter, belongs to the technical field of integrated circuits, and solves the technical problem that an existing source follower cannot meet high-speed and high-linearity indexes. The amplifier comprises a margin amplifier bias and output module, a phase inverter and a linear transconductance unit based on an AB-class super source follower structure, wherein the bias and output module, the linear transconductance unit and the phase inverter are connected in sequence. The linear transconductance unit can generate high-linearity transconductance, so that the linearity of the whole margin amplifier is improved, the symmetry of the positive output end and the negative output end of the margin amplifier under the condition of high-frequency or large-swing input can be ensured, and the high-speed and high-linearity index can be effectively met. In addition, a gain calibration module resistant to temperature and process changes is further introduced, and the influence caused by follow-up system environment temperature changes can be automatically compensated.

The invention provides a low-noise amplification circuit, a radio frequency front-end module and an electronic terminal.The low-noise amplification circuit comprises an input matching adjustment circuit, a common-source amplification circuit, a first inductor, an inter-stage feedback circuit, a common-gate amplification circuit, an input and output feedback circuit, an output matching adjustment circuit and an output attenuation circuit; the common-source amplification circuit comprises at least two first signal amplification units; each first signal amplification unit comprises a first field effect transistor; the common-gate amplification circuit comprises at least two second signal amplification units; and each second signal amplification unit comprises a second field effect transistor. According to the low-noise amplification circuit, transconductance nonlinearity of devices under different bias signals can be mutually counteracted, so that the linearity fluctuation of the low-noise amplification circuit at different temperatures is optimized, and the linearity of the low-noise amplification circuit is kept basically not to change along with the temperature change.

The invention discloses a staggered PFC circuit control method, a control device and a switching power supply. The control method comprises the following steps: acquiring a first voltage sampling signal representing the magnitude of current flowing through a first power loop and a second voltage sampling signal representing the magnitude of current flowing through a second power loop; the operational transconductance amplifier generates an error current according to a difference value between the first voltage sampling signal and the second voltage sampling signal, and then the filter circuit filters the error current to obtain a current-sharing compensation voltage signal; generating a first power loop driving pulse width modulation signal; and generating a second power loop driving pulse width modulation signal under the regulation of the current-sharing compensation voltage signal, increasing the duty ratio of the second power loop driving pulse width modulation signal when the current-sharing compensation voltage signal is greater than the set threshold voltage, and otherwise, reducing the duty ratio of the second power loop driving pulse width modulation signal. On the basis of reducing the number of the peripheral pins of the IC, the problem of non-uniform current in staggered application can be effectively solved.

The invention provides a continuous time linear equalizer based on a low-pass and band-pass mixed structure. The continuous time linear equalizer comprises a frequency selection coupler, a low-pass transconductance unit, a band-pass transconductance unit and a load unit. The frequency selection coupler is used for separating the differential analog signal into a first voltage component in a first band-pass frequency range and a second voltage component in a low-pass frequency range, the first band-pass frequency range comprises a target frequency expected to be compensated, and the frequency in the first band-pass frequency range is greater than the frequency in the low-pass frequency range; the band-pass transconductance unit is used for converting the first voltage component into current and synchronously realizing gain amplification to obtain a first current signal; the low-pass transconductance unit is used for converting the second voltage component into current and synchronously realizing gain amplification to obtain a second current signal; the load unit is used for summing the first current signal and the second current signal and converting the sum to a differential output voltage signal. According to the invention, the frequency corresponding to the gain peak point and the gain amplitude can be improved.

The invention discloses a peak current sampling circuit suitable for a DC / DC converter with a wide load range, and belongs to the field of switching power supply DC / DC converter control. The circuit comprises a power PMOS switch tube P1, a power NMOS tube N1, an inductor L1, a sensing resistor RS, a sensing capacitor CS, an output capacitor COUT, divider resistors RFB1 and RFB2, a sampling circuit, a low-pass filter, a differential amplifier, an adder / subtractor, a transconductance amplifier, a compensation resistor RC, a compensation capacitor CC, a PWM comparator, a slope compensation circuit, an oscillator, an RS trigger and a logic and driving circuit. An equivalent series resistor DCR of an inductor is utilized, and a low-pass RC sensing network is connected to two ends of the inductor in parallel to sense an inductive current, so that power consumption caused by a traditional sampling resistor RSENSE is eliminated, and the efficiency of the DC / DC converter is improved; through reasonable arrangement of the values of the sensing resistor RS and the sensing capacitor CS and an internal signal processing circuit, an inductance ripple current signal is amplified on the basis of retaining the inductance average current, the sampling signal-to-noise ratio is improved, and noise interference is reduced.

An integrated circuit device includes: one or more switches of a Buck converter; and a control circuit for the Buck converter, including: a comparator configured to compare a feedback voltage of the Buck converter with a compensation ramp voltage; a pulse generator configured to generate, in response to a rising edge in a comparator output signal, a pulse signal for controlling the Buck converter; a transconductance amplifier (TA) configured to generate, at an output terminal of the TA, a current proportional to a difference between a reference voltage and the feedback voltage; a capacitor coupled between an output terminal of the TA and a reference voltage node; and a ramp signal generator configured to generate the compensation ramp voltage by adding a voltage at the output terminal of the TA and a ramp voltage having a gradient proportional to a switching frequency of the Buck converter.

An error amplifier includes a first transistor having a first error amplifier input and having first and second current terminals, a second transistor having a second error amplifier input and having third and fourth current terminals, a first resistor coupled between a supply voltage terminal and the first current terminal, and a second resistor coupled between the supply voltage terminal and the third current terminal. The error amplifier has a second stage circuit coupled to the first and second resistors. The second stage circuit has an error amplifier output. The second stage circuit is configured to cause less current to flow through the second stage circuit than a current that flows through either of the first or second resistors or the first or second transistors.

The invention discloses a CMOS power amplifier which comprises a transconductance tube and a common gate tube, the transconductance tube comprises a first CMOS transistor and a second CMOS transistor, the common gate tube comprises a third CMOS transistor and a fourth CMOS transistor, and sources of the first CMOS transistor and the second CMOS transistor are grounded respectively to form a pseudo differential pair; the drain electrode of the first CMOS transistor and the drain electrode of the second CMOS transistor are connected with the source electrode of the third CMOS transistor and the source electrode of the fourth CMOS transistor respectively to form a common-gate structure. A pre-stage driving amplifier of the CMOS power amplifier outputs a main path and an auxiliary path, the main path is connected with the grid electrode of the first CMOS transistor and the grid electrode of the second CMOS transistor through AC double capacitors, and the auxiliary path outputs direct current bias voltage through an envelope detection circuit to be connected to the grid electrode of the third CMOS transistor and the grid electrode of the fourth CMOS transistor.

A monitoring device is provided. The monitoring device comprises one or more circuits operable to obtain measurements of one or more pins of a battery system, the one or more circuits comprising at least one circuit for monitoring current, the at least one circuit comprising at least one differential amplifier, at least one other circuit for amplifying a variance, comprising one voltage reference electrically connected to a first input of the differential amplifier, at least one output electrically connected to a second input of the differential amplifier, and at least one transconductance means comprising at least one input electrically connected to an output of the differential amplifier, at least one current source electrically connected to at least one output of the at least one transconductance means, and an output electrically connected to at least one output of the at least one transconductance means.

A cascade amplification circuit module based on complementary parameter amplifiers belongs to the technical field of integrated circuit amplifiers and comprises a first-stage complementary parameter amplifier (CPA) and a second-stage amplifier (floating inverting type or transconductance resistance type). The first-stage CPA adopts an NMOS and PMOS complementary structure, passive amplification is achieved through grid multiplexing, a grid capacitor is used for storing signals in the sampling stage, a depletion layer capacitor is switched to improve gain in the amplification stage, common-mode voltage is stabilized through complementary design, and an extra feedback circuit is not needed. And the second-stage amplifier provides driving capability and is combined with passive gain to suppress noise. The cascade structure does not need frequency compensation, the design is simplified, the problem of balancing gain, noise and power consumption of a traditional amplifier is solved, and the cascade amplifier has the advantages of being high in energy efficiency and low in complexity.

The invention discloses a ClassAB output stage bias structure based on a negative feedback loop, which belongs to the technical field of integrated circuit design and comprises a ClassAB output stage structure and a negative feedback loop floating current source structure. The ClassAB output stage structure is used for realizing the rail-to-rail output performance of the operational amplifier, and the negative feedback loop floating current source structure is used for determining the static bias current of the ClassAB output stage structure; the negative feedback loop floating current source structure comprises a floating current source structure, a static bias structure, a loop bias structure, a current reference structure and a state conversion structure. According to the invention, static bias is carried out on the ClassAB output stage through a negative feedback loop, the bias precision and good temperature drift resistance are ensured, and the problems of static bias point error, drift and the like caused by the fact that the output stage of the rail-to-rail, low-power-consumption and zero-drift operational amplifier applies traditional linear transconductance ring bias are solved.

The invention relates to the technical field of power circuits, in particular to a voltage margin adjusting circuit, a power management circuit, a chip and electronic equipment. The voltage margin adjusting circuit comprises a voltage margin collecting circuit, a transconductance amplifier and a feedback voltage generating circuit. The voltage margin collecting circuit obtains third voltage according to the difference value of the first output voltage and the second output voltage. The transconductance amplifier obtains a first current according to the first reference voltage and the third voltage; the feedback voltage generation circuit is used for generating corresponding feedback voltage according to the first current; therefore, equivalently, the voltage margin of the low-dropout regulator at the current moment is sampled in real time to adjust the magnitude of the feedback voltage, and finally, the first DC-DC converter adjusts the first output voltage output at the next moment according to the adjusted feedback voltage and the second reference voltage, so that the voltage margin of the low-dropout regulator is dynamically adjusted. Normal work of devices in the circuit can be guaranteed, and electric energy waste is avoided.

The invention discloses an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance. The on-chip automatic calibration system comprises a first part circuit used as a frequency mixer, a second part circuit used as a local oscillator leakage and image frequency detection circuit and a third part circuit used as a digital control circuit, local oscillator leakage and image frequency signals of an output port of a transmitter are detected through a self-mixing method, local oscillator leakage and I / Q imbalance detection is achieved, and an on-chip digital circuit is used for automatically adjusting output current of a current type DAC in a transconductance stage of a mixer according to a detection result. Automatic calibration of on-chip integrated local oscillator leakage and I / Q imbalance is realized.

A filter stage system comprising a continuous-time baseband filter comprising a feedback loop employing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current, and a mirror component mirrors the filtered current to an output.

The invention relates to the technical field of kits, in particular to a MoS2 back gate field effect transistor based on a wet transfer process and a preparation method of the MoS2 back gate field effect transistor. The MoS2 back gate field effect transistor is formed by sequentially arranging a silicon-based substrate, a SiO2 insulating layer, a MoS2 conducting channel layer and an Ag source drain electrode from bottom to top; a high-quality single-layer MoS2 thin film is prepared through a chemical vapor deposition (CVD) method, PMMA is adopted as a supporting layer, clean Van der Waals contact of the MoS2 thin film and a SiO2 / Si substrate is achieved through a wet transfer process of NaOH solution etching, deionized water cleaning and acetone stripping of the supporting layer, and finally a source electrode and a drain electrode are prepared by combining photoetching and thermal evaporation processes. According to the method, the problems of pollutant residues and traps of an interface between MoS2 and the substrate in the traditional process are effectively solved, the carrier mobility, transconductance and on-state current of the device are remarkably improved, the sub-threshold swing is reduced, and the method is suitable for manufacturing a two-dimensional material integrated circuit device with low power consumption and high performance.

The invention belongs to the related technical field of transistors, and discloses a heterojunction type multi-valued logic transistor and a preparation method and application thereof.The transistor comprises a substrate, an insulating layer, a source electrode, a drain electrode, an N-type channel layer and a P-type channel layer, and the insulating layer is arranged on the substrate; the source electrode, the drain electrode, the N-type channel layer and the P-type channel layer are respectively arranged on the surface, far away from the substrate, of the insulating layer; the source electrode and the drain electrode are electrically connected with the N-type channel layer and the P-type channel layer respectively, the N-type channel layer and the P-type channel layer share the same grid electrode, and the N-type channel layer and the P-type channel layer are partially overlapped. Different grid voltages are applied to the substrate through the grid, resistance state regulation and control can be carried out on a conducting channel, the mixed transconductance effect is achieved, and then a logic circuit with a three-valued logic function is constructed.

The invention discloses a ping-pong self-stabilization zero-loop ripple suppression precision operational amplifier, which comprises a high-frequency path and a low-frequency path, and is characterized in that the high-frequency path comprises a third transconductance amplifier Gm3 and a fourth transconductance amplifier Gm4; the low-frequency path comprises a first transconductance amplifier Gm1-Gm3, a second transconductance amplifier Gm1-Gm3, a first chopper Cop1-Cop2, a second chopper Cop1-Cop2 and a ping-pong self-stabilization zero ripple suppression loop, and the ping-pong self-stabilization zero ripple suppression loop is used for suppressing offset voltage and output ripple generated by the low-frequency path. The invention designs a ping-pong self-stabilizing zero ripple suppression feedback (AZCFB) loop, the self offset voltage of the ripple suppression loop is eliminated by adopting an automatic zeroing technology, and the residual offset is filtered by a chopper and a filter. In addition, a high-pass filter is used for eliminating the influence of AZCFB loop sampling node direct-current potential deviation on output ripples, and the purpose of restraining the output ripples is achieved.