689 results about "Transconductance" patented technology

The invention provides a broadband low-noise amplifier based on a three-coil coupling transformer. The broadband low-noise amplifier comprises an input matching network, a common-source differential output driving stage amplifier, an inter-stage matching network, a common-source differential output power stage amplifier and an output matching network which are connected in sequence, broadband matching is realized by using the input matching network and the inter-stage matching network, and the effective transconductance of the transistor is improved; through the cross-coupled capacitors, the LNA gain and stability on a broadband are improved, better isolation is realized, and input and output are decoupled; due to the design of the grounding capacitor, the linearity of the LNA is improved; through the combination of the three-coil coupling transformer and the differential topology, output signals are superposed in the same direction at the output end, and noise is cancelled in the reverse direction at the output end, so that the thermal noise is greatly inhibited, the isolation is improved through the output matching network, the insertion loss is reduced, and the output matching performance is optimized.

A calibration circuit includes a replica transconductance stage that is a replica of a transconductance amplifier in a serializer / deserializer (SerDes) interface and a replica transimpedance stage that is a replica of a transimpedance amplifier in the SerDes interface. The replica transimpedance stage has an input coupled to its output. A comparison circuit is configured to generate a difference signal representative of a difference between voltage levels of an input signal received at an input of the replica transconductance stage and an output signal representative of voltage level at the output of the replica transimpedance stage. Replica feedback resistors are configured to couple an output of the replica transimpedance stage to the input of the replica transconductance stage. The difference signal can be used to select resistance values provided by the replica feedback resistors and by corresponding gain control resistors in the transimpedance amplifier in the SerDes interface.

The embodiment of the invention discloses a load transient enhancement circuit of a voltage mode DCDC converter, which is characterized in that a traditional 3-type compensation network is improved, a zero-point adjustable compensation network is generated by a compensation transconductance amplifier to carry out loop compensation, and then zero-point adjustment is carried out by detecting output voltage. When the output voltage exceeds the threshold due to the overshoot current, the transconductance can be increased through the change of the tail current, so that the zero point moves to the low frequency, the bandwidth can be increased, and the transient response capability is improved. According to the embodiment of the invention, a zero point adjustable compensation network is generated by adding a feedback path to compensate the loop, and the adjustable zero point is adjusted by detecting the output voltage. And when the load jumps, the bandwidth is increased to low frequency through zero point shift, so that the load response capability is enhanced, and the overshoot of the output voltage is reduced.

An even harmonic multiplier employing complementary current reuse is disclosed. The even harmonic multiplier employs supply voltage and current density scaling to reduce power consumption. Further, by using complimentary NMOS and PMOS transistors, the even harmonic multiplier achieves high areal efficiency. Current reuse causes a reduction in noise at the first harmonic, as the corresponding first harmonic currents from the NMOS and PMOS transistors are in opposite, i.e., canceling, directions. Complementary current reuse is now feasible, as the performance of PMOS transistors at current process nodes is similar to those of NMOS transistors, with appropriate sizing leading to approximately equivalent transconductances. Multiple even harmonic multiplier configurations are possible, with many using transformer circuits at the input and / or the output. The resultant even harmonic multipliers find ready application in millimeter wave radio frequency receivers. The most common even harmonic multiplier is a frequency doubler, which produces a strong second harmonic signal.

A monitoring device is provided. The monitoring device comprises one or more circuitry operable to obtain measurements of one or more pins of a battery system, the one or more circuitry comprising at least one circuit for monitoring current, which comprise: at least one other circuit for amplifying variance comprising at least one differential amplifier, one voltage reference in electrical connection with a first input of the differential amplifier; at least one transconductance means comprising at least one output in electrical connection with a second input of the differential amplifier and at least one input in electrical connection with an output of the differential amplifier; at least one current source in electrical connection with at least one output of the at least one transconductance means; and an output in electrical connection with at least one output of the at least one transconductance means.

A circuit to suppress ringing in a Controller Area Network (CAN) bus having a CAN high (CANH) wire and a CAN low (CANL) wire is provided. The circuit may include processing circuitry to generate a CAN control signal, and a transconductance amplifier to receive a first input signal corresponding to the CAN control signal and a voltage signal from the CANL wire, and to generate an output current signal based on a difference between the first input signal and the voltage signal from the CANL wire. An output terminal of the transconductance amplifier may be coupled to the CANH wire to source current to or sink current from the CANH wire.

The invention provides a continuous time Sigma-Delta modulator with constant transconductance bias and negative resistance compensation. The continuous time Sigma-Delta modulator comprises a loop filter, a quantizer and a digital-to-analog converter, the loop filter is used for amplifying a signal in an effective signal bandwidth and attenuating an out-of-band signal at the same time, and the loop filter comprises a first-stage negative resistance compensation integrator and a second-stage negative resistance compensation integrator which are connected in sequence, the first-stage negative resistance compensation integrator comprises a first negative resistance unit containing a negative resistance of a constant transconductance bias circuit and a first integrator unit containing an operational amplifier, and a single operational amplifier resonator structure is formed to generate a second-order response; the integrator of the second-stage negative resistance compensation comprises a second negative resistance unit and a second integrator unit comprising an operational amplifier; and the quantizer is connected with the loop filter, adopts a successive approximation analog-to-digital converter, and is used for converting the analog voltage signal into a digital signal and outputting the digital signal. And the digital-to-analog converter is used for converting the digital signal into an analog signal and feeding back the analog signal to the loop filter.

AED pulse generation circuits that provide floating, adjustable, bias voltages for driving a solid-state defibrillation waveform therapy generator circuit are provided. The provided bias voltages allow to reverse polarity of provided electric shock to increase chances of successful defibrillation and survival. In one of the provided configurations, energy stored in the pulse capacitor can be discharged by activating the waveform therapy generator in the high-resistance transconductance region. The circuits can be positioned on a self-contained module potted with an insulating material to reduce unintended interactions with other AED components. Through the use of the disclosed circuits, AED size can be reduced to promote pocketability while simultaneously increasing AED reliability.

The invention discloses a high-speed and high-linearity margin amplifier and an analog-to-digital converter, belongs to the technical field of integrated circuits, and solves the technical problem that an existing source follower cannot meet high-speed and high-linearity indexes. The amplifier comprises a margin amplifier bias and output module, a phase inverter and a linear transconductance unit based on an AB-class super source follower structure, wherein the bias and output module, the linear transconductance unit and the phase inverter are connected in sequence. The linear transconductance unit can generate high-linearity transconductance, so that the linearity of the whole margin amplifier is improved, the symmetry of the positive output end and the negative output end of the margin amplifier under the condition of high-frequency or large-swing input can be ensured, and the high-speed and high-linearity index can be effectively met. In addition, a gain calibration module resistant to temperature and process changes is further introduced, and the influence caused by follow-up system environment temperature changes can be automatically compensated.

The invention provides a low-noise amplification circuit, a radio frequency front-end module and an electronic terminal.The low-noise amplification circuit comprises an input matching adjustment circuit, a common-source amplification circuit, a first inductor, an inter-stage feedback circuit, a common-gate amplification circuit, an input and output feedback circuit, an output matching adjustment circuit and an output attenuation circuit; the common-source amplification circuit comprises at least two first signal amplification units; each first signal amplification unit comprises a first field effect transistor; the common-gate amplification circuit comprises at least two second signal amplification units; and each second signal amplification unit comprises a second field effect transistor. According to the low-noise amplification circuit, transconductance nonlinearity of devices under different bias signals can be mutually counteracted, so that the linearity fluctuation of the low-noise amplification circuit at different temperatures is optimized, and the linearity of the low-noise amplification circuit is kept basically not to change along with the temperature change.

The invention provides a continuous time linear equalizer based on a low-pass and band-pass mixed structure. The continuous time linear equalizer comprises a frequency selection coupler, a low-pass transconductance unit, a band-pass transconductance unit and a load unit. The frequency selection coupler is used for separating the differential analog signal into a first voltage component in a first band-pass frequency range and a second voltage component in a low-pass frequency range, the first band-pass frequency range comprises a target frequency expected to be compensated, and the frequency in the first band-pass frequency range is greater than the frequency in the low-pass frequency range; the band-pass transconductance unit is used for converting the first voltage component into current and synchronously realizing gain amplification to obtain a first current signal; the low-pass transconductance unit is used for converting the second voltage component into current and synchronously realizing gain amplification to obtain a second current signal; the load unit is used for summing the first current signal and the second current signal and converting the sum to a differential output voltage signal. According to the invention, the frequency corresponding to the gain peak point and the gain amplitude can be improved.

An integrated circuit device includes: one or more switches of a Buck converter; and a control circuit for the Buck converter, including: a comparator configured to compare a feedback voltage of the Buck converter with a compensation ramp voltage; a pulse generator configured to generate, in response to a rising edge in a comparator output signal, a pulse signal for controlling the Buck converter; a transconductance amplifier (TA) configured to generate, at an output terminal of the TA, a current proportional to a difference between a reference voltage and the feedback voltage; a capacitor coupled between an output terminal of the TA and a reference voltage node; and a ramp signal generator configured to generate the compensation ramp voltage by adding a voltage at the output terminal of the TA and a ramp voltage having a gradient proportional to a switching frequency of the Buck converter.

An error amplifier includes a first transistor having a first error amplifier input and having first and second current terminals, a second transistor having a second error amplifier input and having third and fourth current terminals, a first resistor coupled between a supply voltage terminal and the first current terminal, and a second resistor coupled between the supply voltage terminal and the third current terminal. The error amplifier has a second stage circuit coupled to the first and second resistors. The second stage circuit has an error amplifier output. The second stage circuit is configured to cause less current to flow through the second stage circuit than a current that flows through either of the first or second resistors or the first or second transistors.

The invention discloses a CMOS power amplifier which comprises a transconductance tube and a common gate tube, the transconductance tube comprises a first CMOS transistor and a second CMOS transistor, the common gate tube comprises a third CMOS transistor and a fourth CMOS transistor, and sources of the first CMOS transistor and the second CMOS transistor are grounded respectively to form a pseudo differential pair; the drain electrode of the first CMOS transistor and the drain electrode of the second CMOS transistor are connected with the source electrode of the third CMOS transistor and the source electrode of the fourth CMOS transistor respectively to form a common-gate structure. A pre-stage driving amplifier of the CMOS power amplifier outputs a main path and an auxiliary path, the main path is connected with the grid electrode of the first CMOS transistor and the grid electrode of the second CMOS transistor through AC double capacitors, and the auxiliary path outputs direct current bias voltage through an envelope detection circuit to be connected to the grid electrode of the third CMOS transistor and the grid electrode of the fourth CMOS transistor.

A monitoring device is provided. The monitoring device comprises one or more circuits operable to obtain measurements of one or more pins of a battery system, the one or more circuits comprising at least one circuit for monitoring current, the at least one circuit comprising at least one differential amplifier, at least one other circuit for amplifying a variance, comprising one voltage reference electrically connected to a first input of the differential amplifier, at least one output electrically connected to a second input of the differential amplifier, and at least one transconductance means comprising at least one input electrically connected to an output of the differential amplifier, at least one current source electrically connected to at least one output of the at least one transconductance means, and an output electrically connected to at least one output of the at least one transconductance means.

A cascade amplification circuit module based on complementary parameter amplifiers belongs to the technical field of integrated circuit amplifiers and comprises a first-stage complementary parameter amplifier (CPA) and a second-stage amplifier (floating inverting type or transconductance resistance type). The first-stage CPA adopts an NMOS and PMOS complementary structure, passive amplification is achieved through grid multiplexing, a grid capacitor is used for storing signals in the sampling stage, a depletion layer capacitor is switched to improve gain in the amplification stage, common-mode voltage is stabilized through complementary design, and an extra feedback circuit is not needed. And the second-stage amplifier provides driving capability and is combined with passive gain to suppress noise. The cascade structure does not need frequency compensation, the design is simplified, the problem of balancing gain, noise and power consumption of a traditional amplifier is solved, and the cascade amplifier has the advantages of being high in energy efficiency and low in complexity.

The invention discloses a ClassAB output stage bias structure based on a negative feedback loop, which belongs to the technical field of integrated circuit design and comprises a ClassAB output stage structure and a negative feedback loop floating current source structure. The ClassAB output stage structure is used for realizing the rail-to-rail output performance of the operational amplifier, and the negative feedback loop floating current source structure is used for determining the static bias current of the ClassAB output stage structure; the negative feedback loop floating current source structure comprises a floating current source structure, a static bias structure, a loop bias structure, a current reference structure and a state conversion structure. According to the invention, static bias is carried out on the ClassAB output stage through a negative feedback loop, the bias precision and good temperature drift resistance are ensured, and the problems of static bias point error, drift and the like caused by the fact that the output stage of the rail-to-rail, low-power-consumption and zero-drift operational amplifier applies traditional linear transconductance ring bias are solved.

The invention relates to the technical field of power circuits, in particular to a voltage margin adjusting circuit, a power management circuit, a chip and electronic equipment. The voltage margin adjusting circuit comprises a voltage margin collecting circuit, a transconductance amplifier and a feedback voltage generating circuit. The voltage margin collecting circuit obtains third voltage according to the difference value of the first output voltage and the second output voltage. The transconductance amplifier obtains a first current according to the first reference voltage and the third voltage; the feedback voltage generation circuit is used for generating corresponding feedback voltage according to the first current; therefore, equivalently, the voltage margin of the low-dropout regulator at the current moment is sampled in real time to adjust the magnitude of the feedback voltage, and finally, the first DC-DC converter adjusts the first output voltage output at the next moment according to the adjusted feedback voltage and the second reference voltage, so that the voltage margin of the low-dropout regulator is dynamically adjusted. Normal work of devices in the circuit can be guaranteed, and electric energy waste is avoided.

A filter stage system comprising a continuous-time baseband filter comprising a feedback loop employing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current, and a mirror component mirrors the filtered current to an output.

The invention relates to the technical field of kits, in particular to a MoS2 back gate field effect transistor based on a wet transfer process and a preparation method of the MoS2 back gate field effect transistor. The MoS2 back gate field effect transistor is formed by sequentially arranging a silicon-based substrate, a SiO2 insulating layer, a MoS2 conducting channel layer and an Ag source drain electrode from bottom to top; a high-quality single-layer MoS2 thin film is prepared through a chemical vapor deposition (CVD) method, PMMA is adopted as a supporting layer, clean Van der Waals contact of the MoS2 thin film and a SiO2 / Si substrate is achieved through a wet transfer process of NaOH solution etching, deionized water cleaning and acetone stripping of the supporting layer, and finally a source electrode and a drain electrode are prepared by combining photoetching and thermal evaporation processes. According to the method, the problems of pollutant residues and traps of an interface between MoS2 and the substrate in the traditional process are effectively solved, the carrier mobility, transconductance and on-state current of the device are remarkably improved, the sub-threshold swing is reduced, and the method is suitable for manufacturing a two-dimensional material integrated circuit device with low power consumption and high performance.

The invention discloses a ping-pong self-stabilization zero-loop ripple suppression precision operational amplifier, which comprises a high-frequency path and a low-frequency path, and is characterized in that the high-frequency path comprises a third transconductance amplifier Gm3 and a fourth transconductance amplifier Gm4; the low-frequency path comprises a first transconductance amplifier Gm1-Gm3, a second transconductance amplifier Gm1-Gm3, a first chopper Cop1-Cop2, a second chopper Cop1-Cop2 and a ping-pong self-stabilization zero ripple suppression loop, and the ping-pong self-stabilization zero ripple suppression loop is used for suppressing offset voltage and output ripple generated by the low-frequency path. The invention designs a ping-pong self-stabilizing zero ripple suppression feedback (AZCFB) loop, the self offset voltage of the ripple suppression loop is eliminated by adopting an automatic zeroing technology, and the residual offset is filtered by a chopper and a filter. In addition, a high-pass filter is used for eliminating the influence of AZCFB loop sampling node direct-current potential deviation on output ripples, and the purpose of restraining the output ripples is achieved.

An integrated circuit device includes: one or more switches of a Buck converter; and a control circuit for the Buck converter including: a comparator configured to generate a comparator output signal by comparing a feedback voltage of the Buck converter with a compensation ramp voltage; a pulse generator configured to generate, in response to a rising edge in the comparator output signal, a pulse signal for controlling the Buck converter; a transconductance amplifier configured to generate, at an output terminal of the transconductance amplifier, a current proportional to a difference between a reference voltage and the feedback voltage; a capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate the compensation ramp voltage by adding a voltage at the output terminal of the transconductance amplifier and a ramp voltage generated by the ramp signal generator.

AED pulse generation circuits that provide floating, adjustable, bias voltages for driving a solid-state defibrillation waveform therapy generator circuit are provided. The provided bias voltages allow to reverse polarity of provided electric shock to increase chances of successful defibrillation and survival. In one of the provided configurations, energy stored in the pulse capacitor can be discharged by activating the waveform therapy generator in the high-resistance transconductance region. The circuits can be positioned on a self-contained module potted with an insulating material to reduce unintended interactions with other AED components. Through the use of the disclosed circuits, AED size can be reduced to promote pocketability while simultaneously increasing AED reliability.

Disclosed is a two-stage successive approximation register analog to digital converter based on a difference and differential amplifier, including a first-stage sub-ADC, a difference and differential amplifier, and a second-stage sub-ADC connected in sequence. The first-stage sub-ADC and the second-stage sub-ADC each include capacitor arrays and comparators. The difference and differential amplifier includes a transconductance amplifier GM1, a transconductance amplifier GM2, a resistance load R, and proportional resistors R1 and R2. The transconductance amplifier GM1, the resistance load R, and the transconductance amplifier GM2 form a negative feedback loop. The disclosure adjusts the gain of the amplifiers through the proportional resistors R1 and R2, so that higher conversion accuracy can be achieved.

Voltage data capture circuits and techniques. In one example, a circuit includes a differential transconductance stage, a differential transimpedance stage, and an analog to digital converter (ADC). The differential transconductance stage is configured to convert a differential input voltage into a differential current, and the differential transimpedance stage is configured to convert the differential current into a differential output voltage. The ADC is configured to sample the differential output voltage to produce a digital output signal. The circuit may further include a common-mode voltage regulator configured to regulate a common-mode input voltage for the differential transimpedance stage. The circuit can be used, for instance, in a battery monitoring system, or other voltage monitoring application.

The invention discloses a method for extracting parameters of an equivalent circuit model of a GaN HEMT device. The method at least comprises the following steps of S1, modeling the GaN HEMT device into a small-signal equivalent circuit model; s2, extracting external parasitic parameters based on the model in the step S1; s3, internal intrinsic parameters are extracted; in the step S1, the equivalent circuit model comprises external parasitic parameters and internal intrinsic parameters, and the external parasitic parameters are not affected by applied bias voltage and comprise parasitic capacitances Cpg, Cpd and Cpg between metal electrodes, external parasitic inductances Lg, Ld and Ls and external parasitic resistances Rg, Rd and Rs; internal intrinsic parameters are influenced by a channel structure and a bias condition when the device works, and comprise a channel resistor Rgs, a gate-drain resistor Rgd and a drain-source output conductor Gds; capacitors Cgs, Cgd and Cds are arranged among the ports; the transconductance is gm, and the time delay parameter is tau.

Certain aspects are directed towards amplifiers and techniques for signal amplification. An example amplifier generally includes: a first capacitive element coupled to a first output of the amplifier; a first switch coupled between the first capacitive element and a voltage rail; a transconductance amplifier including a first flipped source follower circuit; a second switch coupled between the first capacitive element and the transconductance amplifier; and switches to activate the transconductance amplifier.

The invention discloses a readout front-end circuit of a continuous time increment tracking zoom sensor and an implementation method of the readout front-end circuit, and belongs to the technical field of integrated circuit design. Preparing a floating transconductance amplifier, and simultaneously realizing current multiplexing and low output point voltage through floating power supply; by directly detecting the output of the fine quantizer, a tracking circuit in the reading front end of the tracking scaling type sensor is simplified, an additional input detection circuit is not introduced, and the digital code of the coarse quantizer is adjusted by utilizing the output of the fine quantizer, so that the dynamic range tracking of a rapid change signal is realized. By adopting the technical scheme of the invention, the sensor readout front-end circuit with high energy efficiency, low noise and high dynamic range is realized, and the sensor readout front-end circuit can adapt to novel edge application scenarios such as the Internet of Things, medical treatment and wearable equipment with a relatively high energy effect on rapid change signals.

The invention relates to the technical field of integrated circuits, and discloses a high-pass filter circuit and a low-noise and high-common-mode-rejection-ratio high-speed instrument amplifier, and the low-noise and high-common-mode-rejection-ratio high-speed instrument amplifier comprises a high-pass filter circuit which is used for providing a high-pass filtering function; the input end of the current feedback instrument amplifier circuit is connected with the high-pass filter circuit and used for providing high input impedance and a high common-mode rejection ratio, and the input end of the transconductance amplifier circuit is connected with the output end of the current feedback instrument amplifier circuit and used for improving the load driving capacity; wherein the high-pass filtering circuit adopts a connection mode of a small-capacitance capacitor and an adjustable pseudo resistor to realize high-pass filtering, and the small-capacitance capacitor refers to an on-chip capacitor of which the capacitance value is less than 100pF so as to realize complete integration. The instrument amplifier effectively solves the problem that a traditional instrument amplifier cannot have high speed, low noise, high common-mode rejection ratio and direct-current voltage offset suppression at the same time.

The invention provides an error amplifier for peak current mode control and a converter system. The error amplifier comprises a transconductance amplifier, a voltage clamping module, a voltage-current converter, a slope compensation module, a current clamping module and a mirror image tube, the negative end of the transconductance amplifier is used for loading feedback voltage, and the positive end is used for loading reference voltage; the output end of the transconductance amplifier, the output end of the voltage clamping module and the input end of the voltage-current converter are electrically connected; the voltage-current converter generates error current; the slope compensation module is used for performing slope compensation on the error current to generate a compensated current; the output end of the slope compensation module, the output end of the current clamping module and the positive end of the high-side comparator are electrically connected with a second reference node; and the mirror image tube is used for loading the comparison voltage to the positive end of the high-side comparator. The error amplifier provided by the invention can realize more stable mode switching and more accurate current limiting control.