134results about "Amplification control details" patented technology

Provided are automatic level control (ALC) circuit, signal source, method for controlling signal source output power, and storage medium. The ALC circuit includes: at least two stages of ALC loops, each ALC loop including an amplifier, a coupler, a power detector, and an attenuation control module connected sequentially. An output end of an adjustable attenuator is connected to an input node of first stage of ALC loop; an output node of each stage of ALC loop, other than last stage of ALC loop, is connected to a normally on end of a two-way single-on switch, a first gating end of the two-way single-on switch is connected to an input node of a next stage of ALC loop, and the output node of the last stage of ALC loop and a second gating end of each two-way single-on switch are connected to an output end of the ALC circuit.

Amplifiers with new circuit topologies for gain shaping and gain control are described herein. An example amplifier circuit with gain control includes a differential transistor pair, a main transistor pair coupled to the differential transistor pair, an auxiliary transistor pair coupled to the differential transistor pair, and a resistive impedance coupled between base terminals of the auxiliary transistor pair. The resistive impedance can include a pair of matched resistors coupled between base terminals of the auxiliary transistor pair. The amplifier can also include a capacitor coupled from a virtual ground node between the pair of matched resistors to ground. The amplifier circuits described herein can present a preferred gain response as compared to other amplifiers, at both midband and peaking frequencies. The amplifier circuits also offer additional options for control of gain at midband frequencies, among other benefits.

Circuits and methods include amplification circuitry coupled to a plurality of input signal paths and an output signal path and a unified signal path combining a feedback path couplable between a feedback node in the output signal path and the input signal path via a plurality of input switches and a passive gain path couplable between the feedback node in the output signal path and one or more input signal paths through the input switch. The circuit may include a first capacitor and a variable resistor coupled in series and a second capacitor coupled in series with a feedback path switch and a power supply rejection resistor. The passive gain path may further include a shunt switch coupled in series between a plurality of bypass switches to form a T-switch. A fast charging switch may be configurable to couple a second capacitor to a reference potential during a state change of the unified signal path.

A programmable gain amplifier (PGA) architecture provides for robust operation over a bandwidth and for a multitude of gain settings. For instance, the PGA architecture may include multiple switches to implement different current paths by bypassing resistors in a resistor ladder. The different current paths may result in different gain settings. In some implementations, the switches may be used to hold a value of RA constant while a value of RB may be varied over the different gain settings, where gain may be inferred from the equation Vout=Vin*(1+RB / RA).

Provided are a low-phase-shift variable-gain amplifier and a method for processing a radio frequency signal. The low-phase-shift variable-gain amplifier comprises: a differential cascode amplification circuit, which comprises a common-source transistor and a common-gate transistor, wherein a gate stage of the common-source transistor is connected to a first bias voltage via a target resistor, and a gate stage of the common-gate transistor is connected to a second bias voltage; a current-steering structure, wherein one end of the current-steering structure is connected between the common-source transistor and the common-gate transistor, a third current signal outputted by the current-steering structure is used to adjust a gain of the differential cascode amplification circuit; and a phase compensation circuit, wherein one end of the phase compensation circuit is connected between the common-source transistor and the common-gate transistor.

Amplifiers incorporating equalizer and bias offset correction circuits are described. An example amplifier circuit with equalizer and bias offset correction includes an amplifier with an input, an equalizer circuit coupled to the input of the amplifier, and a bias offset correction circuit coupled to the input of the amplifier. The bias offset correction circuit is configured to adjust a bias potential at the input of the amplifier. In one example, the amplifier is a differential amplifier with differential inputs, the equalizer circuit is coupled to the differential inputs of the amplifier and is configured to adjustably modify a gain of the amplifier over frequency, and the bias offset correction circuit is coupled to the differential inputs of the amplifier and is configured to compensate for modifications to bias potentials at the differential inputs of the amplifier due to operation of the equalizer circuit.

The proposed solution relates to a computer-implemented method for outputting an amplified audio output signal (S2) using an amplification unit (1) for an acoustic vehicle warning system (100) to generate sound audible from persons in the vicinity of a vehicle (200). The method involves receiving an audio input signal (S1) and a temperature value (T) from a temperature sensing unit (20). A control unit (10) of the amplification unit (1) adjusts the amplification of the audio input signal (S1), taking into account at least one temperature reduction measure depending on the temperature value (T), in order to generate the audio output signal (S2). According to the proposed solution, the temperature reduction measure comprises at least one of i.a. adjusting the audio input signal (S1) with respect to at least one frequency (F1) of the audio input signal (S1) while maintaining or increasing the gain of at least one other frequency (F2) of the audio input signal (S1), ii. reducing an operating frequency of the amplification unit (1), and iii. adding at least one frequency (F3) to the audio output signal (S2) that is not included in the audio input signal (S1).

Methods and devices to mitigate the detrimental effects of highly capacitive output routes of multiple gain low noise amplifiers on the overall performance of the circuit are disclosed. The disclosed methods and devices implement the same inductive element across the output load in both the low gain and high gain operational modes. Furthermore, such devices implement switches to control the selection of different signal paths for the high gain and low gain mode. The implemented switches are also used to selectively adjust the isolation of the output stage of the LNA.

Low noise amplifier (LNA) architectures addressing the parasitic challenges in the circuit in order to meet the high gain and bandwidth requirement at higher frequencies are disclosed. The described LNAs include cascode transistors and implement a tunable inductor (Lgate) in series with the gate terminal of a transistor (M2) of the cascode transistors to improve the gain and bandwidth of the LNAs and achieve high gain wideband switching LNAs.

Certain aspects of the present disclosure generally relate to an amplification circuit. The amplification circuit generally includes: a first amplification path (490) including a first amplification transistor (460) and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path (492) comprising a second amplification transistor (486) and coupled between the input node and the output node, where the second amplification path (492) further comprises an attenuator (452, 482, 480) coupled between the input node of the amplification circuit and a control input of the second amplification transistor (486).

A variable gain amplifier for amplifying an input voltage and providing an amplified output voltage includes an input stage including two differential transistor pairs, the input stage coupled to an input of the amplifier. The variable gain amplifier also includes an output stage including a transistor quad and an additional transistor pair, the output stage coupled to an output of the amplifier, the transistor quad including a terminal for receiving a gain control. The variable gain amplifier also includes coupling outputs of the two differential transistor pairs of the input stage to inputs of the transistor quad and additional transistor pair of the output stage to provide a variable gain path and a fixed gain path, respectively. The variable gain amplifier exhibits improved dynamic range of gain variability, lower complexity, and better noise performance.

Feedback methods and devices to reduce gain in RF amplifiers, more in particular LNAs, are disclosed. The described methods are based on providing feedback paths from the drain terminal of one of the LNA cascode transistors to the source terminal of the LNA input transistor, or from the gate terminal of the input transistor to the source terminal of the LNA input transistor. The disclosed methods can be combined with one another or with existing feedback methods to provide further flexibility and improved tradeoffs when designing LNAs for applications having different requirements.

The present disclosure relates to a voltage gain amplifier for automotive radar. Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-to-zero cancellation to yield a desired transfer function without gain peaking at a bandwidth where peaking is desired, and utilizes a low pass filter that is effectively formed by a feedback loop that includes a high pass filter and a differential amplifier to ensure a desired level of attenuation at the desired bandwidth. In some instances, a chopper can be utilized in the feedback loop before the high pass filter and after the differential amplifier in order to reduce the bandwidth of the differential amplifier in the feedback loop.

An integrated circuit (IC), comprising: a first gain stage configured to apply a first gain to a first signal to generate a first gain adjusted signal; a first converter configured to convert the first gain adjusted signal to a first converted signal; a second gain stage configured to apply a second gain to the first converted signal to generate a second gain adjusted signal; and a controller configured to coordinate changes in a first gain of the first gain stage and a second gain of the second gain stage to prevent transients in the second gain adjusted signal.

An attenuator includes passgates for providing attenuation of received signals at desired frequencies. The passgates are controlled by source followers implemented with transistors that receive the differential signals at their control terminals. Current provided to the source follower transistors can be set to provide an attenuation level at a desired frequency to offset the effects of the communications channel and parasitics of the receiver. In some embodiments, the current provided to the source follower transistors maybe programmable.

A high-speed, high-power gallium-nitride-based (GaN-based) operational amplifier ("opamp") and a GaN-based high-power, wideband linear amplitude modulator (LAM) that may be used to implement a dynamic power supply (DPS) in a high- power, wideband polar modulator are disclosed. The high-speed, high-power GaN- based opamp comprises an input differential amplifier having an input-DC-offset¬ minimizing circuit and a class AB push-pull output stage including an efficiency¬ enhancing source follower control circuit that provides for a unique and modified form of buffered frequency compensation. The GaN-based high-power, wideband LAM comprises an input differential amplifier having an input-DC-offset¬ minimizing circuit, similar to that used in the GaN-based opamp, and a current boost circuit that maintains a source follower in an output stage of the LAM in saturation during times the LAM's output voltage is low.

In some aspects, a programmable amplifier (200A) may comprise an n-channel metal-oxide-semiconductor (NMOS) amplification path and a complementary metal-oxide-semiconductor (CMOS) amplification path. In some aspects, the NMOS amplification path may include a first NMOS transistor (N1) and a second NMOS transistor (N2) that are connected in parallel between an input and an output. In some aspects, the CMOS amplification path may include a p-channel metal- oxide-semiconductor (PMOS) transistor (P1) connected in parallel with the first NMOS transistor (N1) between the input and the output. The programmable amplifier (200a) further comprises a plurality of switches that are programmable to switch the PMOS transistor (Pl) off in a first mode, such as an NMOS mode or a high linearity mode, and to switch the second NMOS transistor (N2) off in a second mode, such as a CMOS mode or a low current mode.

An amplifier circuit that includes a capacitor voltage divider that is selectively enabled with a switch. The circuit includes two capacitor banks where the banks are electrically coupled to opposing side terminals of the switch. When the capacitor voltage divider is not enabled, one bank is adjusted to control the gain of the amplifier. When the capacitor voltage divider is enabled, both banks are used to control the gain of the amplifier.

A circuit includes a front end section configured to receive input current signals; a programmable gain amplifier section coupled to the front end section, the programmable gain amplifier section including a plurality of inverters connected in series without a resistor disposed therebetween; and an output buffer section coupled to the programmable gain amplifier section and configured to output voltage signals.

A digitally controlled variable gain amplifier (1) or digitally controlled VGA (1) for generating amplification output levels (10), comprising: - a positive amplification stage (100) comprising at least two positive amplifiers (101;102); - a corresponding negative amplification stage (200) coupled to said positive amplification stage (100), wherein said corresponding negative amplification stage (200) comprises at least two negative amplifiers (201; 202); wherein said positive amplification stage (100) and said corresponding negative amplification stage (200) are digitally controlled by one or more digital codes (240); and wherein: - said corresponding negative amplification stage (200) is coupled in parallel with said positive amplification stage (100) and is equally weighted as said positive amplification stage (100); and - both said positive amplification stage (100) and said corresponding negative amplification stage (200) selectively contribute to the generation of said amplification output levels (10) for said digitally controlled VGA (1).

Provided in the present disclosure is a variable gain amplifier, including: a voltage signal input end; a high level generation module including two high level signal output ends, and configured to convert a voltage signal input from the voltage signal input end into a first high level signal and a second high level signal; a switch signal conversion module including a high level signal input end, N digital signal input ends and N switch signal output ends, and configured to output, through corresponding switch signal output ends and under the control of signals input from the digital signal input ends, gain control signals associated with a signal output from the first high level signal output end; and an amplification module including an amplification unit and N stages of gain control units, where N is a positive integer not less than 1. Further provided is a transmitting apparatus.

A radio frequency (RF) switch employing differential signal cancellation is disclosed. The differential RF switch enables high isolation and extremely small size by employing cascode current steering within a differential switching amplifier. Unlike series RF switches, isolation with the differential RF switch is limited by device mismatch, not switch parasitic capacitance, enabling high frequency operation. Since the differential RF switch can be placed within the already present cascode devices, there is no additional insertion loss from the switch.

A multi-level digital step attenuator (DSA) with a hybrid attenuation circuit is shown. The hybrid attenuation circuit is coupled between an input node and an output node of the multi-level DSA. The bypass switch of the multi-level DSA is controlled to provide a bypass path between the input node and the output node of the of the multi-level DSA when the hybrid attenuation circuit is in a disabled state. In the first active state, the hybrid attenuation circuit is switched to form a T-type structure to provide a first amount of signal attenuation. In the second active state, the hybrid attenuation circuit is switched to form a Pi-type structure to provide a second amount of signal attenuation.

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

Aspects include amplifiers having different cells for improved performance. An amplifier has: a first transistor having a first gate coupled to a control input, and a first drain coupled to a first terminal of an output; and a second transistor having a second gate coupled to the control input and a second drain coupled to the second terminal of the output. The amplifier has: a third transistor having a third drain coupled to the source of the first transistor and a third gate coupled to the first terminal of the input; and a fourth transistor having a fourth drain coupled to the second transistor source and a fourth source gate coupled to a second terminal of the input, where the first transistor source is not connected to the second transistor drain via the one or more transistors.

The amplifier comprises a transconductance amplification module (100), a feedforward transconductance module (200), and a gain control module (300). The input control terminal pair (101P, 101N) of the transconductance amplification module (100) is coupled to an input signal pair (VIP, VIN), and the transconductance amplification module (100) is configured to convert the input signal pair (VIP, VIN) into an output current pair (IOP, ION) and output the output current pair; the feedforward transconductance module (200) comprises a first feedforward control terminal pair (201P, 201N) coupled to an input signal pair (VIP, VIN) and outputting a feedforward current pair;the gain control module (300) comprises a first differential pair (301) and a second differential pair (302), wherein the first output terminal (302P) and the second output terminal (303P) of the first differential pair (301) are each configured to compensate the positive-phase output current and the inverted-phase output current in the output current pair; wherein the first output terminal (302N) and the second output terminal (303N) of the second differential pair (302) are each configured to compensate the positive-phase output current and the inverted-phase output current in the output current pair.

Circuits, semiconductor devices, and systems are provided. An illustrative circuit includes a first pair of transistors cross-coupled with a second pair of transistors. The circuit may further include a gain control circuit coupled with the first pair of transistors and the second pair of transistors, where the gain control circuit provides an error compensation for a beta variation effect in at least one of the first pair of transistors and the second pair of transistors.

Certain aspects of the present disclosure generally relate to an amplification circuit. The amplification circuit generally includes: a first amplification path (490) comprising a first amplification transistor (460) and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path (492) comprising a second amplification transistor (486) and coupled between the input node and the output node, wherein the second amplification path (492) further includes an attenuator (452, 482, 480) coupled between the input node of the amplification circuit and a control input of the second amplification transistor (486).

An amplifier includes a gain stage having a gain stage input and a gain stage output and an impedance matching circuit connected to the gain stage output, the impedance matching circuit including an input and an output. The amplifier also includes a coupling circuit connected to the input of the impedance matching circuit and a shorting circuit connected to the output of the impedance matching circuit. The coupling circuit provides a voltage to the shorting circuit that causes the shorting circuit create a short to ground through a reflecting capacitor which causes a reflection to be provided to the output of the impedance matching circuit and that is transmitted to the coupling circuit to increase the voltage provided to the shorting circuit by the coupling circuit.