91results about "Amplification control details" patented technology

Amplifiers with new circuit topologies for gain shaping and gain control are described herein. An example amplifier circuit with gain control includes a differential transistor pair, a main transistor pair coupled to the differential transistor pair, an auxiliary transistor pair coupled to the differential transistor pair, and a resistive impedance coupled between base terminals of the auxiliary transistor pair. The resistive impedance can include a pair of matched resistors coupled between base terminals of the auxiliary transistor pair. The amplifier can also include a capacitor coupled from a virtual ground node between the pair of matched resistors to ground. The amplifier circuits described herein can present a preferred gain response as compared to other amplifiers, at both midband and peaking frequencies. The amplifier circuits also offer additional options for control of gain at midband frequencies, among other benefits.

Circuits and methods include amplification circuitry coupled to a plurality of input signal paths and an output signal path and a unified signal path combining a feedback path couplable between a feedback node in the output signal path and the input signal path via a plurality of input switches and a passive gain path couplable between the feedback node in the output signal path and one or more input signal paths through the input switch. The circuit may include a first capacitor and a variable resistor coupled in series and a second capacitor coupled in series with a feedback path switch and a power supply rejection resistor. The passive gain path may further include a shunt switch coupled in series between a plurality of bypass switches to form a T-switch. A fast charging switch may be configurable to couple a second capacitor to a reference potential during a state change of the unified signal path.

Provided are a low-phase-shift variable-gain amplifier and a method for processing a radio frequency signal. The low-phase-shift variable-gain amplifier comprises: a differential cascode amplification circuit, which comprises a common-source transistor and a common-gate transistor, wherein a gate stage of the common-source transistor is connected to a first bias voltage via a target resistor, and a gate stage of the common-gate transistor is connected to a second bias voltage; a current-steering structure, wherein one end of the current-steering structure is connected between the common-source transistor and the common-gate transistor, a third current signal outputted by the current-steering structure is used to adjust a gain of the differential cascode amplification circuit; and a phase compensation circuit, wherein one end of the phase compensation circuit is connected between the common-source transistor and the common-gate transistor.

Amplifiers incorporating equalizer and bias offset correction circuits are described. An example amplifier circuit with equalizer and bias offset correction includes an amplifier with an input, an equalizer circuit coupled to the input of the amplifier, and a bias offset correction circuit coupled to the input of the amplifier. The bias offset correction circuit is configured to adjust a bias potential at the input of the amplifier. In one example, the amplifier is a differential amplifier with differential inputs, the equalizer circuit is coupled to the differential inputs of the amplifier and is configured to adjustably modify a gain of the amplifier over frequency, and the bias offset correction circuit is coupled to the differential inputs of the amplifier and is configured to compensate for modifications to bias potentials at the differential inputs of the amplifier due to operation of the equalizer circuit.

The proposed solution relates to a computer-implemented method for outputting an amplified audio output signal (S2) using an amplification unit (1) for an acoustic vehicle warning system (100) to generate sound audible from persons in the vicinity of a vehicle (200). The method involves receiving an audio input signal (S1) and a temperature value (T) from a temperature sensing unit (20). A control unit (10) of the amplification unit (1) adjusts the amplification of the audio input signal (S1), taking into account at least one temperature reduction measure depending on the temperature value (T), in order to generate the audio output signal (S2). According to the proposed solution, the temperature reduction measure comprises at least one of i.a. adjusting the audio input signal (S1) with respect to at least one frequency (F1) of the audio input signal (S1) while maintaining or increasing the gain of at least one other frequency (F2) of the audio input signal (S1), ii. reducing an operating frequency of the amplification unit (1), and iii. adding at least one frequency (F3) to the audio output signal (S2) that is not included in the audio input signal (S1).

Methods and devices to mitigate the detrimental effects of highly capacitive output routes of multiple gain low noise amplifiers on the overall performance of the circuit are disclosed. The disclosed methods and devices implement the same inductive element across the output load in both the low gain and high gain operational modes. Furthermore, such devices implement switches to control the selection of different signal paths for the high gain and low gain mode. The implemented switches are also used to selectively adjust the isolation of the output stage of the LNA.

Low noise amplifier (LNA) architectures addressing the parasitic challenges in the circuit in order to meet the high gain and bandwidth requirement at higher frequencies are disclosed. The described LNAs include cascode transistors and implement a tunable inductor (Lgate) in series with the gate terminal of a transistor (M2) of the cascode transistors to improve the gain and bandwidth of the LNAs and achieve high gain wideband switching LNAs.

Certain aspects of the present disclosure generally relate to an amplification circuit. The amplification circuit generally includes: a first amplification path (490) including a first amplification transistor (460) and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path (492) comprising a second amplification transistor (486) and coupled between the input node and the output node, where the second amplification path (492) further comprises an attenuator (452, 482, 480) coupled between the input node of the amplification circuit and a control input of the second amplification transistor (486).

A variable gain amplifier for amplifying an input voltage and providing an amplified output voltage includes an input stage including two differential transistor pairs, the input stage coupled to an input of the amplifier. The variable gain amplifier also includes an output stage including a transistor quad and an additional transistor pair, the output stage coupled to an output of the amplifier, the transistor quad including a terminal for receiving a gain control. The variable gain amplifier also includes coupling outputs of the two differential transistor pairs of the input stage to inputs of the transistor quad and additional transistor pair of the output stage to provide a variable gain path and a fixed gain path, respectively. The variable gain amplifier exhibits improved dynamic range of gain variability, lower complexity, and better noise performance.

Feedback methods and devices to reduce gain in RF amplifiers, more in particular LNAs, are disclosed. The described methods are based on providing feedback paths from the drain terminal of one of the LNA cascode transistors to the source terminal of the LNA input transistor, or from the gate terminal of the input transistor to the source terminal of the LNA input transistor. The disclosed methods can be combined with one another or with existing feedback methods to provide further flexibility and improved tradeoffs when designing LNAs for applications having different requirements.

An integrated circuit (IC), comprising: a first gain stage configured to apply a first gain to a first signal to generate a first gain adjusted signal; a first converter configured to convert the first gain adjusted signal to a first converted signal; a second gain stage configured to apply a second gain to the first converted signal to generate a second gain adjusted signal; and a controller configured to coordinate changes in a first gain of the first gain stage and a second gain of the second gain stage to prevent transients in the second gain adjusted signal.

An attenuator includes passgates for providing attenuation of received signals at desired frequencies. The passgates are controlled by source followers implemented with transistors that receive the differential signals at their control terminals. Current provided to the source follower transistors can be set to provide an attenuation level at a desired frequency to offset the effects of the communications channel and parasitics of the receiver. In some embodiments, the current provided to the source follower transistors maybe programmable.

A high-speed, high-power gallium-nitride-based (GaN-based) operational amplifier ("opamp") and a GaN-based high-power, wideband linear amplitude modulator (LAM) that may be used to implement a dynamic power supply (DPS) in a high- power, wideband polar modulator are disclosed. The high-speed, high-power GaN- based opamp comprises an input differential amplifier having an input-DC-offset¬ minimizing circuit and a class AB push-pull output stage including an efficiency¬ enhancing source follower control circuit that provides for a unique and modified form of buffered frequency compensation. The GaN-based high-power, wideband LAM comprises an input differential amplifier having an input-DC-offset¬ minimizing circuit, similar to that used in the GaN-based opamp, and a current boost circuit that maintains a source follower in an output stage of the LAM in saturation during times the LAM's output voltage is low.

An amplifier circuit that includes a capacitor voltage divider that is selectively enabled with a switch. The circuit includes two capacitor banks where the banks are electrically coupled to opposing side terminals of the switch. When the capacitor voltage divider is not enabled, one bank is adjusted to control the gain of the amplifier. When the capacitor voltage divider is enabled, both banks are used to control the gain of the amplifier.

A circuit includes a front end section configured to receive input current signals; a programmable gain amplifier section coupled to the front end section, the programmable gain amplifier section including a plurality of inverters connected in series without a resistor disposed therebetween; and an output buffer section coupled to the programmable gain amplifier section and configured to output voltage signals.

A radio frequency (RF) switch employing differential signal cancellation is disclosed. The differential RF switch enables high isolation and extremely small size by employing cascode current steering within a differential switching amplifier. Unlike series RF switches, isolation with the differential RF switch is limited by device mismatch, not switch parasitic capacitance, enabling high frequency operation. Since the differential RF switch can be placed within the already present cascode devices, there is no additional insertion loss from the switch.

A multi-level digital step attenuator (DSA) with a hybrid attenuation circuit is shown. The hybrid attenuation circuit is coupled between an input node and an output node of the multi-level DSA. The bypass switch of the multi-level DSA is controlled to provide a bypass path between the input node and the output node of the of the multi-level DSA when the hybrid attenuation circuit is in a disabled state. In the first active state, the hybrid attenuation circuit is switched to form a T-type structure to provide a first amount of signal attenuation. In the second active state, the hybrid attenuation circuit is switched to form a Pi-type structure to provide a second amount of signal attenuation.

Aspects include amplifiers having different cells for improved performance. An amplifier has: a first transistor having a first gate coupled to a control input, and a first drain coupled to a first terminal of an output; and a second transistor having a second gate coupled to the control input and a second drain coupled to the second terminal of the output. The amplifier has: a third transistor having a third drain coupled to the source of the first transistor and a third gate coupled to the first terminal of the input; and a fourth transistor having a fourth drain coupled to the second transistor source and a fourth source gate coupled to a second terminal of the input, where the first transistor source is not connected to the second transistor drain via the one or more transistors.

Circuits, semiconductor devices, and systems are provided. An illustrative circuit includes a first pair of transistors cross-coupled with a second pair of transistors. The circuit may further include a gain control circuit coupled with the first pair of transistors and the second pair of transistors, where the gain control circuit provides an error compensation for a beta variation effect in at least one of the first pair of transistors and the second pair of transistors.

Certain aspects of the present disclosure generally relate to an amplification circuit. The amplification circuit generally includes: a first amplification path (490) comprising a first amplification transistor (460) and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path (492) comprising a second amplification transistor (486) and coupled between the input node and the output node, wherein the second amplification path (492) further includes an attenuator (452, 482, 480) coupled between the input node of the amplification circuit and a control input of the second amplification transistor (486).

An amplifier includes a gain stage having a gain stage input and a gain stage output and an impedance matching circuit connected to the gain stage output, the impedance matching circuit including an input and an output. The amplifier also includes a coupling circuit connected to the input of the impedance matching circuit and a shorting circuit connected to the output of the impedance matching circuit. The coupling circuit provides a voltage to the shorting circuit that causes the shorting circuit create a short to ground through a reflecting capacitor which causes a reflection to be provided to the output of the impedance matching circuit and that is transmitted to the coupling circuit to increase the voltage provided to the shorting circuit by the coupling circuit.

An example apparatus includes: variable gain amplifier (VGA) circuitry having: an input terminal, an output terminal, and a control terminal; and peak detector circuitry having: an input terminal coupled to the output terminal of the VGA circuitry; an output terminal coupled to the control terminal of the VGA circuitry; the peak detector circuitry configured to: compare a voltage on the output of the VGA circuitry to an offset voltage; and adjust, responsive to the comparison, a gain of the VGA circuitry.

An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.

The present invention provides a radio frequency low noise amplifier circuit and radio frequency chip, comprising a signal input terminal, an input matching circuit, an amplifier circuit, an output matching circuit and a signal output terminal connected in sequence, and further comprising a gain adjustment circuit connected in parallel with the amplifier circuit, the gain adjustment circuit including a tenth transistor, an eleventh transistor, a twelfth transistor, a first resistor, a second resistor, a third resistor and a fourth capacitor, the source of the tenth transistor, the source of the eleventh transistor and the source of the twelfth transistor are connected to each other and grounded, the drain of the tenth transistor is connected to the first end of the first resistor, the drain of the eleventh transistor is connected to the first end of the second resistor, the drain of the twelfth transistor is connected to the first end of the third resistor, and the second end of the first resistor, the second end of the second resistor and the second end of the third resistor are all connected to the first end of the fourth capacitor. The radio frequency low noise amplifier circuit and chip of the present invention have a flexible and adjustable gain and high safety.

The invention provides an adaptive equalizer circuit and an operation method thereof. The adaptive equalizer circuit includes an amplifier circuit and an adaptive circuit. The amplifier circuit is coupled to the adaptive circuit. The amplifier circuit receives an input signal. The amplifier circuit provides a compensation signal to the adaptive circuit based on an input signal. The adaptability circuit provides a compensation setpoint and a feedback signal to the amplifier circuit based on the compensation signal. A low-frequency response and a high-frequency gain of the amplifier circuit are adjusted based on the feedback signal and the compensation setpoint, respectively.

In an example, an amplifier is provided. The amplifier comprises a first transistor. A drain of the first transistor is connected to a first node of the amplifier, a source of the first transistor is connected to a first input node of the amplifier, and a gate of the first transistor is connected to a first gate bias voltage. The first input node is for receiving a first input current signal of an input signal. The amplifier also comprises a second transistor. A drain of the second transistor is connected to a second node of the amplifier, a source of the second transistor is connected to a second input node of the amplifier, and a gate of the second transistor is connected to a second gate bias voltage. The second input node is for receiving a second input current signal of the input signal. The amplifier also comprises a first current source configured to provide a first bias current at the first input node, and a second current source configured to provide a second bias current at the second input node. The amplifier further comprises a first capacitor connected between the first input node and a control node of the second current source, and a second capacitor connected between the second input node and a control node of the first current source.

This application relates to the field of electronic device technologies, and discloses a multi-mode inductive circuit, a control method, a low noise amplifier, and an electronic device. The multi-mode inductive circuit includes an input node, at least two inductors, at least three switches, and an output node. The input node is electrically connected to a first terminal of one of the inductors. The input node is further electrically connected to a first terminal of the other inductor through a switch. A second terminal of the one inductor is electrically connected to the output node through an other switch. The second terminal of the one inductor is further electrically connected to the first terminal of the other inductor through the other switch. A second terminal of the other inductor is electrically connected to the output node. At least four inductance values of the multi-mode inductive circuit are determined through closing and opening of the at least three switches. Based on the solution of this application, inductance values for more modes may be obtained, thereby obtaining more gain modes for the low noise amplifier, and the circuit structure is simple.

A power amplifier includes a transistor, a temperature sensor, and a filter. The transistor is configured to receive a bias signal and amplify a radio frequency signal. The temperature sensor is disposed proximate to the transistor and is configured to detect a temperature of the transistor and provide a voltage signal at a control node in response thereto. The filter is coupled to the temperature sensor and is configured to filter the voltage signal to generate a filtered voltage. The bias signal is adjusted in response to the filtered voltage.

Devices, systems, and methods for adjustable gain amplification for use in communications systems are described. An amplifier has a gain that is adjustable based on a bias current supplied to the amplifier. The amplifier is configured to operate with a first input saturation level to apply a first gain to an input signal with a first maximum amplitude, and operate with a second input saturation level that is greater than the first input saturation level to apply a second gain smaller than the first gain when the input signal has a second maximum amplitude greater than the first maximum amplitude.