299results about "Amplification control details" patented technology

A calibration circuit includes a replica transconductance stage that is a replica of a transconductance amplifier in a serializer / deserializer (SerDes) interface and a replica transimpedance stage that is a replica of a transimpedance amplifier in the SerDes interface. The replica transimpedance stage has an input coupled to its output. A comparison circuit is configured to generate a difference signal representative of a difference between voltage levels of an input signal received at an input of the replica transconductance stage and an output signal representative of voltage level at the output of the replica transimpedance stage. Replica feedback resistors are configured to couple an output of the replica transimpedance stage to the input of the replica transconductance stage. The difference signal can be used to select resistance values provided by the replica feedback resistors and by corresponding gain control resistors in the transimpedance amplifier in the SerDes interface.

Provided are automatic level control (ALC) circuit, signal source, method for controlling signal source output power, and storage medium. The ALC circuit includes: at least two stages of ALC loops, each ALC loop including an amplifier, a coupler, a power detector, and an attenuation control module connected sequentially. An output end of an adjustable attenuator is connected to an input node of first stage of ALC loop; an output node of each stage of ALC loop, other than last stage of ALC loop, is connected to a normally on end of a two-way single-on switch, a first gating end of the two-way single-on switch is connected to an input node of a next stage of ALC loop, and the output node of the last stage of ALC loop and a second gating end of each two-way single-on switch are connected to an output end of the ALC circuit.

According to one embodiment, a low noise amplifier (LNA) circuit includes a first stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with a gate capacitance of the first transistor for a dual-resonance. The LNA circuit includes a second stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second stages, where the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

A transimpedance amplifier circuit (110) is proposed, comprising at least one transimpedance amplifier (112). The transimpedance amplifier comprises at least one variable feedback resistor (114) and at least one operational amplifier (116). The variable feedback resistor (114) is connected between an input of an operational amplifier (116) and an output of the operational amplifier (116).

Low noise amplifiers (LNAs) are disclosed herein. In certain embodiments, an LNA includes an input balun configured to convert a single-ended radio frequency (RF) receive signal to a differential RF receive signal, an amplifier chain configured to amplify the differential RF receive signal to generate a differential amplified RF receive signal, and an output balun configured to convert the differential amplified RF receive signal into a single-ended amplified RF receive signal. The LNA's amplifier chain is operable in multiple gain modes, and includes a first differential amplification stage, a second differential amplification stage, and a third differential amplification stage.

Disclosed in the present invention are a power amplifier module for implementing average power protection, an electronic device, and a method. The power amplifier module comprises: a controller, configured to provide logic control and bias voltage for a radio frequency power amplifier; the radio frequency power amplifier, configured to amplify the power of a radio frequency signal and then output the amplified radio frequency signal to a filter; and a filter for frequency bands, configured to filter the amplified radio frequency signal to obtain a radio frequency signal of a required specific frequency band. When the detected power of the radio frequency power amplifier is greater than or equal to a first power threshold, and the time during which the detected power is greater than or equal to the first power threshold reaches a first time threshold, the power amplifier module enters an average power protection operating mode, and the controller adjusts the gain of a power amplification unit, so as to protect the filter in the power amplifier module from being burnt out.

Amplifiers with new circuit topologies for gain shaping and gain control are described herein. An example amplifier circuit with gain control includes a differential transistor pair, a main transistor pair coupled to the differential transistor pair, an auxiliary transistor pair coupled to the differential transistor pair, and a resistive impedance coupled between base terminals of the auxiliary transistor pair. The resistive impedance can include a pair of matched resistors coupled between base terminals of the auxiliary transistor pair. The amplifier can also include a capacitor coupled from a virtual ground node between the pair of matched resistors to ground. The amplifier circuits described herein can present a preferred gain response as compared to other amplifiers, at both midband and peaking frequencies. The amplifier circuits also offer additional options for control of gain at midband frequencies, among other benefits.

Circuits and methods include amplification circuitry coupled to a plurality of input signal paths and an output signal path and a unified signal path combining a feedback path couplable between a feedback node in the output signal path and the input signal path via a plurality of input switches and a passive gain path couplable between the feedback node in the output signal path and one or more input signal paths through the input switch. The circuit may include a first capacitor and a variable resistor coupled in series and a second capacitor coupled in series with a feedback path switch and a power supply rejection resistor. The passive gain path may further include a shunt switch coupled in series between a plurality of bypass switches to form a T-switch. A fast charging switch may be configurable to couple a second capacitor to a reference potential during a state change of the unified signal path.

An analog front end (AFE) circuit including: a continuous time linear equalizer (CTLE) circuit; a transimpedance amplifier (TIA) connected to the CTLE circuit; and a feedback circuit including: a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source; a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and a first tunable resistor coupled between the first node and the second node, wherein: a first input of the feedback circuit is connected to a first output of the TIA; a second input of the feedback circuit is connected to a second output of the TIA; the second output of the feedback circuit is connected to a first input of the TIA.

A programmable gain amplifier (PGA) architecture provides for robust operation over a bandwidth and for a multitude of gain settings. For instance, the PGA architecture may include multiple switches to implement different current paths by bypassing resistors in a resistor ladder. The different current paths may result in different gain settings. In some implementations, the switches may be used to hold a value of RA constant while a value of RB may be varied over the different gain settings, where gain may be inferred from the equation Vout=Vin*(1+RB / RA).

Provided are a low-phase-shift variable-gain amplifier and a method for processing a radio frequency signal. The low-phase-shift variable-gain amplifier comprises: a differential cascode amplification circuit, which comprises a common-source transistor and a common-gate transistor, wherein a gate stage of the common-source transistor is connected to a first bias voltage via a target resistor, and a gate stage of the common-gate transistor is connected to a second bias voltage; a current-steering structure, wherein one end of the current-steering structure is connected between the common-source transistor and the common-gate transistor, a third current signal outputted by the current-steering structure is used to adjust a gain of the differential cascode amplification circuit; and a phase compensation circuit, wherein one end of the phase compensation circuit is connected between the common-source transistor and the common-gate transistor.

A radio-frequency amplifier can have an input stage that includes an amplifying transistor having an input node and an output node, such that a signal at the input node has a first power level and an amplified signal at the output node has a second power level. The radio-frequency amplifier can further include a bias circuit configured to provide a bias signal to the amplifying transistor, and a feedback circuit that couples the output node of the amplifying transistor to the input node of the amplifying transistor. The feedback circuit can include a resistance and a capacitance arranged in series. The radio-frequency amplifier can further include a gain compensation circuit implemented relative to the input stage such that the second power level is compensated for a variation in temperature associated with the radio-frequency amplifier.

Amplifiers incorporating equalizer and bias offset correction circuits are described. An example amplifier circuit with equalizer and bias offset correction includes an amplifier with an input, an equalizer circuit coupled to the input of the amplifier, and a bias offset correction circuit coupled to the input of the amplifier. The bias offset correction circuit is configured to adjust a bias potential at the input of the amplifier. In one example, the amplifier is a differential amplifier with differential inputs, the equalizer circuit is coupled to the differential inputs of the amplifier and is configured to adjustably modify a gain of the amplifier over frequency, and the bias offset correction circuit is coupled to the differential inputs of the amplifier and is configured to compensate for modifications to bias potentials at the differential inputs of the amplifier due to operation of the equalizer circuit.

Low noise amplifiers (LNAs) are disclosed herein. In certain embodiments, an LNA includes an input balun configured to convert a single-ended radio frequency (RF) receive signal to a differential RF receive signal, an amplifier chain configured to amplify the differential RF receive signal to generate a differential amplified RF receive signal, and an output balun configured to convert the differential amplified RF receive signal into a single-ended amplified RF receive signal. The LNA's amplifier chain is operable in multiple gain modes, and includes a first differential amplification stage, a second differential amplification stage, and a third differential amplification stage.

A control device (100) for controlling at least one actuator (200) for actuating an optical element (310) of an optical system (300), with a power amplifier (110) which is configured to amplify an input voltage (V1) using a quiescent current (I1) of the power amplifier (110) into a drive voltage (V2) for the actuator (200), and a provisioning device (120) which is configured to adjust the quiescent current (I1) for the final stage (110) as a function of at least one parameter (E1, E2, E3, P1) indicative of a power dissipation of the optical system (300).

An apparatus includes a plurality of gain stages connected in parallel between a first bias voltage and ground, where each gain stage includes an amplification portion and a current control portion including a first selectable signal path connected between an output of the amplification portion and a signal output, and a second selectable signal path connected between an output of the amplification portion and a signal output. And a second selectable signal path connected between the output of the amplification section and ground by a shunt device.

A gain stage circuit can include first and second follower circuits arranged as a differential pair and configured to receive respective input signals. The gain stage circuit can include or use a pass stage circuit including an adjustable-impedance signal path that couples the first and second follower circuits. The gain stage circuit can further include or use a control circuit to receive the input signals and, in response, provide a control signal to the pass stage circuit to control an impedance of the signal path that couples the first and second follower circuits.

A differential amplifier with an RF switch function includes an input matching circuit, N (N is an integer of 2 or more) differential amplification circuits connected to the input matching circuit, and N output matching circuits connected to the N differential amplification circuits in a one-to-one manner. The N differential amplification circuits are connected in parallel. Only one of the N differential amplification circuits is driven.

To provide a power amplifier that can reduce gain variation against temperature variation.SOLUTION: A power amplifier 100 includes an amplifier transistor Q1 including an input node and an output node. A signal in the input node has a first power level. An amplification signal in the output node has an input stage with a second power level. The power amplifier further includes a bias circuit 113 that sends a bias signal to the amplifier transistor, and a feedback circuit that couples the output node of the amplifier transistor Q1 to the input node of the amplifier transistor. The feedback circuit includes a resistor R1 and a capacitance C6 arranged in series. The power amplifier further includes a gain compensation circuit including a variable attenuator 110 and mounted on the input stage so that the second power level is compensated against the temperature variation associated with the power amplifier.SELECTED DRAWING: Figure 3

The proposed solution relates to a computer-implemented method for outputting an amplified audio output signal (S2) using an amplification unit (1) for an acoustic vehicle warning system (100) to generate sound audible from persons in the vicinity of a vehicle (200). The method involves receiving an audio input signal (S1) and a temperature value (T) from a temperature sensing unit (20). A control unit (10) of the amplification unit (1) adjusts the amplification of the audio input signal (S1), taking into account at least one temperature reduction measure depending on the temperature value (T), in order to generate the audio output signal (S2). According to the proposed solution, the temperature reduction measure comprises at least one of i.a. adjusting the audio input signal (S1) with respect to at least one frequency (F1) of the audio input signal (S1) while maintaining or increasing the gain of at least one other frequency (F2) of the audio input signal (S1), ii. reducing an operating frequency of the amplification unit (1), and iii. adding at least one frequency (F3) to the audio output signal (S2) that is not included in the audio input signal (S1).

The invention relates to an amplifier with common mode gain reduction. An amplifier (200) circuit includes a first transistor (M1) having a terminal and a second transistor (M2) having a terminal coupled to the terminal of the first transistor (M1). A third transistor (M3) has a first terminal coupled to the terminals of the first and second transistors (M1, M2), and has a control terminal. A fourth transistor (M4) has a control terminal coupled to the terminals of the first and second transistors (M1, M2) and the first terminal of the third transistor (M3). The fourth transistor (M4) has a second terminal. A fifth transistor (M5) has a control terminal coupled to the second terminal of the fourth transistor (M4), and has second and third terminals. A sixth transistor (M6) has a control terminal coupled to the control terminal of the third transistor (M3) and the third terminal of the fifth transistor (M5). A sixth transistor (M6) has a second terminal coupled to the second terminal of the fifth transistor (M5).

Methods and devices to mitigate the detrimental effects of highly capacitive output routes of multiple gain low noise amplifiers on the overall performance of the circuit are disclosed. The disclosed methods and devices implement the same inductive element across the output load in both the low gain and high gain operational modes. Furthermore, such devices implement switches to control the selection of different signal paths for the high gain and low gain mode. The implemented switches are also used to selectively adjust the isolation of the output stage of the LNA.

A method for calibrating an isolator product includes receiving a calibration signal on a differential pair of nodes of a receiver signal path of a first integrated circuit die of the isolator product. The method includes generating a diagnostic signal having a level corresponding to an average amplitude of the calibration signal on the differential pair of nodes. The method includes configuring a programmable receiver signal path based on the diagnostic signal. Generating the diagnostic signal may include providing an analog signal based on a full-wave rectified version of the calibration signal on the differential pair of nodes. Generating the diagnostic signal may include converting the analog signal to a digital signal.

Low noise amplifier (LNA) architectures addressing the parasitic challenges in the circuit in order to meet the high gain and bandwidth requirement at higher frequencies are disclosed. The described LNAs include cascode transistors and implement a tunable inductor (Lgate) in series with the gate terminal of a transistor (M2) of the cascode transistors to improve the gain and bandwidth of the LNAs and achieve high gain wideband switching LNAs.

In some embodiments, a method for processing an audio signal in an audio processing apparatus is disclosed. The method includes receiving an audio signal and a parameter, the parameter indicating a location of an auditory event boundary. An audio portion between consecutive auditory event boundaries constitutes an auditory event. The method further includes applying a modification to the audio signal based in part on an occurrence of the auditory event. The parameter may be generated by monitoring a characteristic of the audio signal and identifying a change in the characteristic.

The present application relates to the technical field of electronic devices, and discloses a multi-mode inductive circuit, a control method, a low-noise amplifier, and an electronic device. The multi-mode inductive circuit comprises an input node, a first inductor, a second inductor, a first switch, a second switch, a third switch, and an output node. The input node is electrically connected to a first end of the first inductor, and the input node is also electrically connected to a first end of the second inductor by means of the first switch. A second end of the first inductor is electrically connected to the output node by means of the second switch, and the second end of the first inductor is also electrically connected to the first end of the second inductor by means of the third switch. A second end of the second inductor is electrically connected to the output node. At least four inductance values of the multi-mode inductive circuit are determined by means of at least three switches being connected and disconnected. On the basis of the solution of the present application, inductance values of more modes can be obtained, so that more gain modes of a low-noise amplifier are obtained, and the circuit structure is simple.

A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

Certain aspects of the present disclosure generally relate to an amplification circuit. The amplification circuit generally includes: a first amplification path (490) including a first amplification transistor (460) and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path (492) comprising a second amplification transistor (486) and coupled between the input node and the output node, where the second amplification path (492) further comprises an attenuator (452, 482, 480) coupled between the input node of the amplification circuit and a control input of the second amplification transistor (486).

A variable gain amplifier for amplifying an input voltage and providing an amplified output voltage includes an input stage including two differential transistor pairs, the input stage coupled to an input of the amplifier. The variable gain amplifier also includes an output stage including a transistor quad and an additional transistor pair, the output stage coupled to an output of the amplifier, the transistor quad including a terminal for receiving a gain control. The variable gain amplifier also includes coupling outputs of the two differential transistor pairs of the input stage to inputs of the transistor quad and additional transistor pair of the output stage to provide a variable gain path and a fixed gain path, respectively. The variable gain amplifier exhibits improved dynamic range of gain variability, lower complexity, and better noise performance.