9042results about "Differential amplifiers" patented technology

A content addressable memory (CAM) device and process for searching a CAM. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration to their respective thresholds to reduce effects of random device variation between adjacent sense amplifiers.

A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluation signal pair corresponding to an input single pair to the first output terminal pair. The second latch latches the evaluation signal pair and outputs the evaluation signal pair to a second output terminal pair. The floating reduction unit is controlled by signals of the first output terminal pair and is operationally connected between current passing nodes of the first latch to prevent the first output terminal pair from floating. The input signal applying unit is disposed between the current passing nodes and a ground terminal, and receives the input signal pair. The ground switch is disposed between the input signal applying unit and the ground terminal, and is controlled by the clock signal. The delay reduction unit is disposed between the input signal applying unit and the ground switch, and reduces a signal delay from when the clock signal to when the evaluation signal pair is output from the second output terminal pair.

An integrated current-to-voltage conversion circuit converts a first current to an output voltage representative of the first current. The circuit includes a first contact pad and second and third contact pads capable of being coupled across a first resistor. A first operational amplifier has a first input coupled to the first contact pad for producing a first voltage thereat, a second input for receiving a reference voltage, and a first output coupled to the third contact pad. A second voltage appears at the third contact pad. A second operational amplifier has a second output at which a third voltage appears, a first input coupled to the second output, and a second input coupled to the second contact pad. The output voltage is substantially equal to the difference between the second and third voltages.

An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.

A fly-back power converter has a current-estimating control loop that senses the primary output current in a transformer to control the secondary output. A primary-side control circuit switches primary current through the transformer on and off. A discharge time when a secondary current through an auxiliary winding of the transformer is flowing is generated by sampling a voltage divider on an auxiliary loop for a knee-point. A normalized duty cycle is calculated by multiplying the discharge time by a current that is proportional to the switching frequency and comparing to a sawtooth signal having the switching frequency. The peak of a primary-side voltage is sensed from the primary current loop and converted to a current and multiplied by the normalized duty cycle to generate an estimated current. An error amp compares the estimated current to a reference to adjust the oscillator frequency and peak current to control primary switching.

A sense amplifier comprises an input node and an output node. An input transistor has a gate connected to the input node, a source connected to a first supply voltage rail, and a drain. A cascode transistor has a gate connected to a cascode node, a source connected to the drain of the input transistor, and a drain connected to the output node. A load transistor has a gate connected to a bias node, a drain connected to the output node, and a source connected to a second supply voltage rail. The gates of the cascode transistor and the load transistor are biased such that the input transistor and the cascode transistor are operated near their threshold and the load transistor is operated above threshold. In a presently preferred embodiment of the present invention, the input transistor and the cascode transistor of the sense amplifier are wide and short, such that they operate in below threshold, whereas the load transistor is made long and relatively narrow, so that it operates above threshold.

Biosensor circuit arrangement including a substrate, a sensor element formed in or on a surface region of the substrate with a physical parameter, which is coupled to a substance to be examined, the type of coupling having a resistive component, the sensor element having an electrically conductive sensor electrode that is coupled to the substance to be examined, the sensor element having a measuring transistor the gate terminal of which is coupled to the electrically conductive sensor electrode, and the physical parameter being the threshold voltage of the measuring transistor, and a calibration device formed in or on the substrate, the calibration device being set up such that it is used to at least partly compensate for an alteration of the value of the physical parameter of the sensor element.

Various embodiments of methods and apparatus for an amplifier with wide output voltage swing are disclosed. The amplifier may include multiple output stages, each associated with a distinct supply voltage. Each output stage may contribute current to the output of the amplifier over a range of amplifier output voltages and these ranges may overlap. Each output stage may contribute current until the amplifier output voltage reaches the supply voltage associated with that output stage. The amplifier output may be as great as the largest supply voltage minus a drop equal to Rdson for an output transistor multiplied by the output current. In a CMOS implementation, this voltage drop may be approximately 0.15V. When the amplifier output voltage is close to the supply voltage associated with an output stage, both that output stage and the output stage associated with the next highest supply voltage may contribute to the amplifier output.

A system is provided for substantially reducing variation in AM to PM distortion of a power amplifier caused by variations in RF drive power and temperature. The system includes power control circuitry and power amplifier circuitry. The power amplifier circuitry includes an input amplifier stage and at least one additional amplifier stage coupled in series with the input amplifier stage. The power control circuitry provides a first supply voltage to the input amplifier stage based on a control signal such that the first supply voltage has a predetermined DC offset with respect to the control signal. The first supply voltage is provided such that the predetermined DC offset substantially reduces variations in the AM to PM distortion of the power amplifier due to variations in radio frequency (RF) drive power.

The present invention provides for dynamic insertion loss control for a 10/100/1000 megahertz Ethernet power on differential cable pairs. A power feed circuit supplies power to a network attached device (PD). An insertion loss control circuit limits power loss in a coupled power feed circuit. The insertion loss control circuit determines an insertion loss limit and senses an average power of the power signals to produce a common mode feedback signal to the power feed circuit. The insertion loss limit is determined for the received signals based on a differential RMS of the received Ethernet power signals as seen by a differential transistor pair. Alternatively, the insertion loss limit may be determined logically by the higher layers of the network protocol based on the AC differential portion of the network power signal. When the insertion loss limit is determined based on the differential RMS, the insertion loss control circuit is operable to automatically reduce the insertion loss based upon transmission losses experienced over the network connection between the power sending equipment and network-attached device.

A data transmission system using a pair of complement signals (STROB/STROB#) as an edge-aligned strobe signal and input/output buffers therein. Several data signals and a pair of STROB/STROB# signals are transmitted from a data output device to a data input device therein. These data signals and the STROB/STROB# signals are edge-aligned and transmitted through the same transmission architecture. The data input device includes several data comparators for generating output signals from the received data signals using the received STROB/STROB# signals as a dynamic reference voltage. In addition, the data input device further includes several comparators and delay elements for generating a pair of non-inverting/inverting latch clock signals from the STROB/STROB# signals. Each of the output signals is sent to two data latch circuits for outputting two latched data based on the latch clock signals.

A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two amplifiers are connected together and each amplifier receives the same differential input signals. The tail-current transistor is self-biased using the current-mirror's gate-bias. This self biasing of each amplifier eliminates the need for an additional voltage reference and allows each amplifier to adjust its biasing over a wide input-voltage range. Thus the common-mode input range is extended using self biasing and complementary amplifiers. The complementary self-biased comparators can be used for receiving binary or multi-level-transition (MLT) inputs by selecting different voltage references for threshold comparison. Using the same reference on both differential inputs eliminates a second reference for multi-level inputs having three levels. Thus binary and MLT inputs can be detected and decoded by the same decoder.