7results about How to "Reduced Miller Capacitance" patented technology

The invention relates to a novel asymmetric groove SiC MOSFET device with low resistance and Miller capacitance, and belongs to the technical field of semiconductor devices. The device comprises a substrate; the drift region is formed on one surface of the substrate; the N-CSL is formed on the surface of the drift region; the low-barrier diode is formed on one side of the surface of the N-CSL; the second P-well is formed on the other side of the surface of the N-CSL; the trench gate and the auxiliary trench gate are formed on the surface of the low-barrier diode and located on the two sides of the low-barrier diode; the P-base is formed on the surface of the N-CSL and is positioned between the second P-well and the trench gate; the source N + region is formed on the surface of the P-base and is positioned between the second P-well and the trench gate; a source electrode formed on the top of the device; and the drain electrode is formed on the other surface of the substrate. The specific on-resistance of the device can be reduced, the Miller capacitance and the gate charge of the device are reduced, and the switching speed of the device is improved.

The invention discloses a split gate IGBT (Insulated Gate Bipolar Translator) structure, and belongs to the field of semiconductor devices. Comprising collector metal, a P-type collector region, an N-type field stop layer and an N-type drift region which are sequentially arranged from bottom to top, an N-type storage layer, a P-type body region and emitter metal are sequentially arranged above the N-type drift region, an N + contact region is arranged in the P-type body region, a first oxide layer medium is arranged in the middle of the bottom of the emitter metal, a cross-shaped groove is formed in the N-type drift region, and a second oxide layer medium is arranged in the cross-shaped groove. The cross-shaped groove divides the N-type drift region, the N-type storage layer, the P-type body region and the N + contact region into a left part and a right part. The top of the cross-shaped groove is provided with a gate oxide layer, the bottom of the cross-shaped groove is provided with a second oxide layer medium, the top of the cross-shaped groove is provided with gate polycrystalline silicon which divides the gate oxide layer into a left part and a right part, and the left wide part and the right wide part of the cross-shaped groove are both internally provided with separation gate polycrystalline silicon. According to the split gate IGBT structure provided by the invention, the Miller capacitance and the conduction voltage drop can be effectively reduced.

The invention discloses a trench gate type IGBT (Insulated Gate Bipolar Translator) and a manufacturing method thereof, and belongs to the technical field of semiconductors, the manufacturing method of the trench gate type IGBT comprises the following steps: providing a substrate; etching the substrate to form a groove; depositing polycrystalline silicon at the bottom of the groove to form an emitter region; continuously depositing an insulating medium with a first preset height on the top of the emitter region; the two sides of the insulating medium are etched to form two containing cavities with second preset heights, and the second preset heights are smaller than the first preset height; depositing polycrystalline silicon in the accommodating cavity to form a gate region; the insulating medium between the two containing cavities continues to be etched, an opening extending to the emitter region is formed between the containing cavities, the critical size of the opening is smaller than the critical size of the remaining insulating medium, and the opening is filled with polycrystalline silicon so that the emitter region can be led out. By setting the relative positions of the gate region and the emitter region, the contact area of the collector and the gate region is reduced, so that the Cres of the IGBT can be reduced, the switching speed of the IGBT can be improved, and the switching loss of the IGBT can be reduced.

The application relates to a full GaN power electronic monolithic integrated circuit and a preparation method thereof, which comprises, from bottom to top, an insulating composite substrate, an AlN layer, a Si layer, a GaN / AlGaN buffer layer, a GaN layer and an AlGaN layer; a 2DEG layer is formed between the GaN layer and the AlGaN layer; the AlGaN layer is etched, a p-GaN layer is grown; a p-GaN layer gate portion is etched and filled with a passivation layer, and a gate metal is grown; source metal and drain metal are respectively grown on both sides of the p-GaN layer gate area; a deep groove is arranged between a driving circuit and a low-voltage tube, between a high-voltage tube and the low-voltage tube, and a medium is filled in the deep groove; and the full GaN power electronic monolithic integrated circuit is obtained through a top via and an interconnection process. The application can realize high efficiency and low power consumption, low parasitic effect, and reduce leakage current and switching loss.

The present invention discloses a trench gate IGBT device with a floating structure, comprising a collector metal; a collector region of a first conductivity type, located on the upper surface of the collector metal; a field stop layer of a second conductivity type, located on the upper surface of the collector region of the first conductivity type; a drift region of a second conductivity type, located on the upper surface of the field stop layer of the second conductivity type; a trench structure, located in the drift region of the second conductivity type, the trench structure comprising a trench, a wide portion, and a narrow portion, the wide portion comprising a wide portion electrode; a floating region of the first conductivity type, located between the trench structures; an emitter metal, covering the top of the entire device; the floating region of the first conductivity type and the emitter metal are isolated by a first dielectric layer; the wide portion electrode and the emitter metal have the same potential. The present invention reduces the Miller capacitance of the IGBT, reduces the switching time, improves the dv / dt control capability of the IGBT during the opening process, reduces the EMI interference during the switching process, and improves the withstand voltage of the IGBT device.

The invention discloses an anti-radiation super-junction power MOS device and a preparation method thereof, the device comprises a substrate layer, a buffer layer and an epitaxial layer which are sequentially stacked from bottom to top, a plurality of super-junction columns arranged at intervals are arranged in the epitaxial layer, and a body region is arranged above each super-junction column; a hole doping region and a source doping region which are in contact with each other are arranged in the body region; a gate oxide layer is arranged on the upper surface of the epitaxial layer, and the lower surface of the gate oxide layer is in contact with part of the upper surfaces of the epitaxial layer, the body region and the source doping region; the upper surface of the gate oxide layer is covered with a polycrystalline silicon layer, and the gate oxide layer and the polycrystalline silicon layer form a gate electrode; and an interval doping injection region is also arranged on the epitaxial layer which is not covered by the gate oxide layer between the adjacent body regions. According to the invention, through the interval doping injection region, the hole gathering number below the gate oxide region after particle incidence can be reduced, and the SEGR capability is improved; the current passing through a parasitic transistor base region resistor is reduced, and the threshold value of SEB is improved.

The invention discloses a metal oxide semiconductor field effect transistor and a preparation method thereof. Each cell in the metal oxide semiconductor field effect transistor comprises a drain metal layer, a substrate, an epitaxial layer, a current expansion layer, a base region layer, an injection layer, a source metal region and a gate region, the drain metal layer, the substrate, the epitaxial layer, the current expansion layer, the base region layer and the injection layer are stacked in sequence; the upper part of the source electrode metal region covers the injection layer and the upper surface of the gate region, and the lower part of the source electrode metal region penetrates through the injection layer, the base region layer and the current expansion layer and extends to a buried layer region in the epitaxial layer; the side wall of the source metal region comprises a Schottky contact region and a gate region with the side wall as a longitudinal center line. According to the embodiment of the invention, the dynamic characteristics of the metal oxide semiconductor field effect transistor are improved while the conduction voltage drop and the reliability of the silicon carbide metal oxide semiconductor field effect transistor are ensured.