93results about How to "Reduced Miller Capacitance" patented technology

The present invention discloses an LDO (Low DropOut) linear voltage regulator, which is based on an NMC (Nested Miller Compensation) architecture and can be capacitor-free, wherein an active resistor is added to the feedback path of the Miller compensation capacitor to increase the controllability of the damping factor, solve the problem of extensively using the output capacitor with a parasitic resistance, and solve the problem that a compromise must be made between the damping factor control and the system loop gain. Further, the present invention utilizes a capacitor-sharing technique to reduce the Miller capacitance required by the entire system and accelerate the stabilization of output voltage without influencing stability.

A dual sensitivity image sensor provides a standard mode and a high-sensitivity mode of operation via iSoC integration. In addition to boosting sensitivity, the high sensitivity mode also reduces temporal noise thereby optimally boosting the Signal-to-Noise Ratio (SNR) of the image sensor. The circuit does not significantly increase pixel complexity and requires minimal changes to the support circuits in the iSoC including the addition of support and control circuitry to facilitate seamless mode change.

A semiconductor gate structure includes a shielding electrode and a switching electrode. Portions of a shield electrode are located over the drain region and the well region. The first dielectric layer is located between the shielding electrode and the drain and well regions. Portions of switch electrodes are located over the well region and the source region. A second dielectric layer is located between the switch electrode and the well and source regions. A third dielectric layer is located between the shield electrode and the switch electrode.

The invention provides a silicon carbide MOSFET device and a manufacturing method thereof. Discontinuous gate structures are formed on the basis of the common silicon carbide MOSFET structure, two silicon carbide deep P injection regions are introduced between the two gate structure and metal or polycrystalline silicon is introduced between the two silicon carbide deep P injection regions. The metal or the polycrystalline silicon directly contacts the silicon carbide N-epitaxy so as to form the Schottky contact or the heterojunction contact having the rectification characteristic. The improvement greatly optimizes the conventional silicon carbide UMOSFET basic characteristics, realizes integration of multiple sub-rectifiers and greatly optimizes the third quadrant performance of the device. Meanwhile, the silicon carbide MOSFET device has the characteristics of low Miller capacitance, simple process and easy implementation.

The invention discloses an insulated gate bipolar transistor. Compared with the prior art, polycrystalline silicon filled in a trench is separated by a dielectric layer into an upper polycrystalline silicon layer and a lower polycrystalline silicon layer, the upper polycrystalline silicon layer and the lower polycrystalline silicon layer are mutually contacted with an oxide layer at the upper part of the trench and an oxide layer at the lower part of the trench respectively, the upper polycrystalline silicon layer is connected with a gate electrode, and the lower polycrystalline silicon layer is connected with an emitting electrode; and bottom part of the upper polycrystalline silicon layer in the trench is deeper than a P-type well region of an active primitive cell. The structure disclosed by the invention reduces the Miller capacitance and the turn-on power consumption of the device.

The invention belongs to the technical field of power semiconductor devices, and relates to a RET IGBT with a self-biased PMOS and a manufacturing method thereof. According to the RET IGBT with the self-biased PMOS and the manufacturing method thereof, a N-type charge storage layer is arranged between a P-type base region and a P-type buried layer, so that the influence of the N-type charge storage layer on the breakdown voltage of the device can be shielded while the forward conduction characteristic of the device is improved; by introducing a PMOS structure, an extra path is provided for theextraction of holes, the extraction speed of current carriers is accelerated, the switching speed of the device is improved, and the turn-off loss of the device is reduced; and meanwhile, an emitterembedded type separation gate structure can meet the requirement that a table top of the device is further narrowed to improve the forward conduction characteristic of the device, metal and contact holes of the emitter of the device can be easily and irregularly made, and meanwhile, the Miller capacitance of the device can be reduced further.

The present invention achieves technical advantages as a current monitoring circuit for DC-DC switching converters, including a track and latch comparator circuit (30) having a preamplifier (32) that is controlled independently of a latch circuit (34). Advantageously, the comparator is small and operates very fast and with improved sensitivity. For example, the preamplifier circuit is disabled when the latch stage is making its decision to avoid noise and input disturbances from affecting the latch stage. This selective disabling feature speeds up the signal processing of the comparator and allows it to work in parallel with other circuits. The latch stage can make its decision later, regardless of any further activity at the inputs of the comparator.

A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

The invention provides a silicon carbide MOSFET device and a manufacturing method thereof. The invention aims at a conventional silicon carbide UMOSFET structure, and proposes a multi-sub rectifier device integration mode, and includes implementation methods of Schottky contact and Si/SiC heterojunction contact. While effectively improving the basic characteristics of the traditional carbonize UMOSFET and optimizing the long-term application reliability of the device, the invention realizes the integration of the multi-sub rectifier devices, thereby greatly optimizing the work performance of the device in the third quadrant. The implementation process of the structure is compatible with the traditional silicon carbide UMOSFET process, and has the characteristic of easy fabrication.

The present invention provides a transverse groove-type MOSFET device, belonging to the technical field of semiconductor power devices. A polycrystalline silicon region or a Schottky contact metal region is formed at the circumference side of the gate structure to allow polycrystalline silicon region or the Schottky contact metal region and the drift region to form heterojunction or Schottky contact with rectification characteristics. Because the heterojunction or Schottky contact is multiple sub devices and is lower in conduction pressure drop compared to a traditional parasitic diode, the reverse recovery characteristic of the device can be optimized, and an excellent three-quadrant on-state performance is achieved; and compared to an external antiparallel diode mode, the size of the electrical power system can be significantly reduced, the package cost is reduced, interconnection lines are reduced, and the parasitic effect of the interconnection lines is reduced so as to improve thereliability of the system. Aiming at the problem that the device gate medium electric field is too high, the optimization is design to improve the long application reliability performance of the device. Besides, the preparation method of the device is simple and controllable and easy to achieve, and promotes the popularization of the semiconductor power device in the many actual applications.

The invention discloses an anti-EMI SGT device. The device comprises a substrate of a first conductive type, an epitaxial layer of the first conductive type which is positioned on the upper surface ofthe substrate of the first conductive type, a trench gate structure located in the epitaxial layer of the first conductive type, a trench source structure located above the side surface of the epitaxial layer of the first conductive type, a first dielectric layer and a heavily doped body region of the first conductive type located between the trench source structure and the epitaxial layer of thefirst conductive type, and a second dielectric layer located above the trench gate structure, wherein the trench gate structure comprises a gate trench, and a shielding gate and a polycrystalline silicon gate which are positioned in the gate trench; the trench source structure includes a source trench and a source metal located within the source trench. According to the device disclosed in the invention, the SGT source-drain capacitance Cds is increased, the switching oscillation is reduced, and therefore the voltage oscillation dv/dt failure possibility and EMI noise of the device are reduced.

The invention provides a trench insulated gate bipolar transistor device and a generating method thereof. A relatively thick gate oxide film is formed at the bottom of a trench region through a plasmafilm forming process. Due to the fact that the thickness of the gate oxide film at the bottom of a trench is increased, the consistency of the gate oxide thickness is guaranteed, the defect that a gate oxide layer at the bottom of the trench is easy to break down is eliminated, and the robustness of a gate oxide breakdown voltage is improved. Meanwhile, the area of a gate-drain capacitor is reduced, so that the Miller capacitance is reduced, the switch delay time is shortened, the switch dynamic loss of a device is reduced, and the switch characteristic of the device is improved. Meanwhile, the relatively thick gate oxide film is formed at the bottom of the trench, so that the upper surface of polycrystalline silicon subjected to back etching can be leveled and is slightly higher than thesurface of a silicon wafer of a N-type base region; and higher N+ emitter junction depth can be formed without increasing the injection energy of an N+ emitter and carrying out longer-time high-temperature trap pushing, so that the vertical overlapping area of the gate and the source is reduced, the gate-source capacitance is reduced, and the switch loss of an IGBT is reduced.

The invention discloses a bidirectional IGBT and a manufacturing method therefor, and belongs to the technical field of power semiconductor devices. According to the invention, a split electrode whichis equipotential with a surface metal and a thick dielectric layer located at a peripheral side of the split electrode are introduced to a conventional trench gate structure, and a floating P-type body region is introduced to one side of a split trench gate structure, thereby achieving the symmetric forwarding and reverse on/off characteristics of an IGBT structure under the condition that a threshold voltage and connection of an IGBT device are not affected. The adverse effect caused by the Miller effect is improved, and the drive power consumption is reduced. The current and voltage oscillation and EMI problems are avoided in a start dynamic process of the device. The short-circuit safety working area of the device is improved. The gate capacitance is reduced, the switching speed of thedevice is improved, and the switching loss of the device is reduced. The concentration of an electric field at the bottom of a trench is improved, and the breakdown voltage of the device is improved.The carrier enhancement effect of an emitter electrode is improved, the carrier concentration distribution of the whole N-type drift region is improved, and the compromise between the forwarding conduction voltage drop and switching-off loss is improved.

The invention provides an IGBT (Insulated Gate Bipolar Translator) device with a MOS (Metal Oxide Semiconductor) control hole path, and belongs to the technical field of power semiconductor devices. AMOS control gate structure formed by a gate dielectric layer, a MOS control gate electrode and a P-type MOS channel area is introduced into a P+ floating pbody area of a traditional IGBT device, anda MOS region is equivalent to a switch under gate voltage control. When the device is conducted forwardly, the potential of the pbody area floats, so that hole storage is realized, and the saturated on-off voltage drop of the device is reduced. When the device is off and short-circuited, a hole discharge path is provided; the Miller capacitance is reduced; and the low on-off loss and more stable short circuit capability are realized.

Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method for forming an oxide layer at the bottom of a trench comprises providing a first substrate with at least one trench therein; forming a first oxide layer on the bottom and sidewalls of the trench; removing the first oxide layer at the bottom of the trench; and forming a second oxide layer at the bottom of the trench.