14 results about "Miller effect" patented technology

The application discloses a planar SiC MOSFET integrated with a reverse freewheeling diode, and belongs to the technical field of semiconductors. The gate of the device is a split gate structure, the gate polysilicon is divided into left and right parts through source polysilicon, and an additional P-shield area is added at the bottom, and the source polysilicon is connected with the P-shield area through a through freewheeling tube oxide. The structure makes the channel diode integrated at the bottom of the planar structure oxide replace the body diode as the freewheeling diode in the device, reduces the bipolar degradation effect caused by the combination of electrons and holes in the traditional SiC MOSFET, and the opening voltage drop of the freewheeling diode is smaller than that of the body diode, thereby reducing the power consumption of the circuit system. The split gate structure of the application replaces the traditional whole gate structure, reduces the directly opposite area of the capacitor between the gate and the drain, improves the capacitor characteristics and the Miller effect of the device, and reduces the switching loss and switching time of the device.

The invention relates to the technical field of semiconductors, and particularly discloses an MOSFET device with low grid charge and a preparation method of the MOSFET device. A LOCOS isolation layer; a P-type electric field regulation and control layer is shallowly buried under the channel; a transverse doping gradient channel; a gate dielectric layer; a main gate; a shield grid structure; the source side doping concentration of the asymmetric LDD region is 1 * 10 < 18 > cm <-3 >, the width is 0.1 mu m, and the depth is 50nm; the doping concentration of the drain side is 5 * 10 < 17 > cm <-3 >, the width is 0.15 mu m, and the depth is 50nm; a drain region is provided with a two-stage stepped groove; a source-drain heavily doped region; and the metal electrode comprises a source electrode, a main grid electrode, a shielding grid and a drain electrode. Through the synergistic effect of the shallow-buried P-type electric field regulation and control layer under the channel, the shield gate, the drain region two-stage stepped groove and the composite gate dielectric, the gate-drain coupling capacitance and the gate capacitance are reduced in principle, the Miller effect is inhibited, the ultra-thin gate and the NiSi silicide are combined to reduce the gate driving loss, meanwhile, sub-threshold electric leakage is inhibited, static and dynamic power consumption is doubly reduced, and the reliability of the device is improved. And the sensor endurance is prolonged.

The invention discloses a multi-stage feedback broadband low-noise amplifier which comprises a first-stage amplifier, a second-stage amplifier and an output-stage buffer amplifier. The first-stage amplifier is composed of a cascode structure and a current multiplexing structure; the second-stage amplification electric appliance is composed of a complementary common-source structure and a current multiplexing structure. The output stage buffer amplification circuit is composed of a common source buffer structure and a current multiplexing structure. According to the invention, the cascade structure and the complementary common-source structure are connected in parallel, and inter-stage capacitance offset, source inductance and current multiplexing are adopted. By means of the mode, the use efficiency of current in the circuit is improved, the circuit gain and noise performance and the like are improved, on the other hand, the Miller effect is effectively restrained, a dominant pole is pushed to high frequency, and therefore the circuit bandwidth is greatly expanded.

A bias circuit includes a control loop, configured to output a bias current to the input end of the RF power amplifier; a regulation circuit, configured to adjust loop bandwidth of the control loop based on Miller effect when it is determined that the bias current output by the control loop can meet a first condition, so that stability and noise suppression degree of the control loop can meet a second condition.

This invention relates to the field of drive circuit technology, and discloses a highly reliable gate drive circuit, drive chip, and power semiconductor device. The circuit breaks through the existing passive compromise scheme that relies solely on adjusting the turn-off resistor. It uses a detection unit to collect the gate voltage of the IGBT unit in real time, a latch unit to output a stable square wave signal when the voltage reaches a preset threshold, and a pull-down unit to simultaneously provide a low-impedance discharge path, actively suppressing abnormal gate voltage rise caused by the Miller effect. The design of the Miller suppression unit avoids the switching speed reduction and device overheating problems caused by increasing the turn-off resistor, while effectively suppressing the risk of mis-turn-on caused by crosstalk between the upper and lower bridge arms, achieving dual optimization of crosstalk suppression and switching performance. This significantly improves the reliability and stability of the gate drive, extends the lifespan of the power semiconductor device, and is suitable for various power topologies such as half-bridge and full-bridge, with wide application scenarios and strong practicality.

The invention provides a semiconductor device and a forming method thereof, and the semiconductor device comprises a conductive layer which is provided with a drift region of a first conduction type and a floating region of a second conduction type, and the floating region is located above the drift region; the trench gate structure penetrates through part of the conductive layer, and the bottom of the trench gate structure is located in the floating region; the Miller effect can be suppressed, the purpose of reducing switch oscillation and delay loss is achieved, and meanwhile the advantages of being free of an additional photomask, high in process compatibility, easy to manufacture and low in cost are achieved.

This application relates to delay adjustment circuits. An amplifier (e.g., a differential amplifier) ​​may function similarly to a variable capacitor (e.g., due to the Miller effect) to control the delay of signals between buffer (e.g., a transition driver) stages. The gain of the amplifier can be adjusted by changing the current passing through it, which alters the apparent capacitance experienced by the signal lines (due to the Miller effect). The capacitance of each amplifier may be the intrinsic capacitance of the input transistors that make up the amplifier, or it may be a discrete capacitor. In some instances, two differential stages may be inserted into a four-phase timing system (e.g., one on the 0 and 180° phases, and another on the 90 and 270° phases) and may be differentially controlled to control the inter-phase delay.

The utility model discloses an ultra wide band low noise amplifier based on a GaAs technology, which comprises an input port, an output port, N stages of power amplification units, a first active bias circuit and a second active bias circuit, wherein the N stages of power amplification units are positioned between the input port and the output port and are sequentially cascaded; the first active bias circuit is connected in parallel between the input port and the grounding end, the input end of the second active bias circuit is grounded, and the output end of the second active bias circuit is connected with the output end of the grid electrode of each stage of power amplification unit. An active bias circuit is embedded into the amplifier for integrated design, the chip amplitude consistency is improved, the Miller effect of a first-stage transistor is reduced by using a cascode structure circuit, so that the frequency bandwidth range is expanded, the gain value is higher than that of a distributed amplifier circuit of a cascode structure under the condition that the stages of gain units are the same, and the gain value is higher than that of the distributed amplifier circuit of the cascode structure. And the reverse isolation of the circuit is improved, and the loss of an output transmission line is reduced.

The invention relates to a semi-arc air field plate structure of a GaN HEMT and a preparation method thereof. The preparation method comprises the following steps: defining an active region range of a high-frequency semiconductor device; defining patterns of a source electrode and a drain electrode of the device, performing metal evaporation on the source electrode and the drain electrode, and performing high-temperature tempering at the same time; defining a device gate pattern to form a Y-shaped gate; after a photoresist is deposited in the Gate region to cover the gate, the photoresist is baked and hardened to protect the Gate region, and then a dielectric layer is deposited above the device; defining a field plate pattern above the dielectric layer, etching the dielectric layer at the position where field plate metal needs to be deposited in a wet etching or dry etching mode, and directly depositing the field plate metal; the photoresist is removed after metal deposition, the photoresist which is originally protected above the grid electrode is removed together, and an air cavity structure formed by an arc-shaped field plate is formed at the position of the grid electrode of the device. Air is used as an ultra-low dielectric material, so that the parasitic capacitance of the device is remarkably reduced, the Miller effect is reduced, the high-frequency characteristic is improved, and the switching loss is reduced.

The application discloses a Miller effect elimination circuit, which is electrically connected between a control electrode of a power semiconductor device and a first current-carrying terminal, and comprises an elimination trigger circuit and an energy storage capacitor. The elimination trigger circuit is activated during the turn-off of the power semiconductor device in response to a control signal, and connects the energy storage capacitor in parallel between the control electrode and the first current-carrying terminal while applying a turn-off negative voltage to the control electrode. At this time, the energy storage capacitor, together with a Miller capacitor, a parasitic capacitor and a loop parasitic inductance of the power semiconductor device, forms a low-frequency resonance network. The application solves the problems of the suspended gate and high-frequency resonance in the traditional scheme, and is suitable for reliable driving of SiC MOSFET, IGBT and other devices in high-voltage high-speed switching occasions.

The utility model discloses an IGBT fast turn-off voltage stabilization drive circuit based on Miller capacitance suppression, which relates to the technical field of power electronics and comprises a two-stage IGBT drive circuit composed of an upper layer circuit and a lower layer circuit. Each of the upper layer circuit and the lower layer circuit comprises a driving chip, a divider resistor, an overcurrent resistor, a filter capacitor and an IGBT (Insulated Gate Bipolar Translator); the divider resistor is connected between grid electrodes of the driving chip IGBT, two ends of the divider resistor are also connected in parallel with a current limiting loop, the grid electrodes of the IGBT are connected with the bidirectional voltage-regulator tube, and the overcurrent resistor and the filter capacitor are connected in parallel and are connected between the bidirectional voltage-regulator tube and the emitter electrode of the IGBT. By adding the current-limiting loop channel and the voltage-regulator tube which are rapidly turned off in the circuit, the misconduction phenomenon caused by the Miller effect can be effectively inhibited, the normal turn-off of the IGBT is ensured, the switching performance of the IGBT is improved, and the reliability and the stability of the circuit are improved.

The invention relates to a driving device and method for solving secondary conduction of a lower tube in a BUCK system, the driving device comprises an upper tube driving module, a lower tube driving module and a lower tube grid voltage control module, and the lower tube grid voltage control module comprises a sequential control logic unit and a charge pump. The sequential control logic unit receives a first signal indicating the conduction state of the upper tube and a second signal indicating the conduction state of the lower tube, and generates a charge pump control signal according to the first signal and the second signal; the charge pump receives the charge pump control signal and controls the charging and discharging processes under the control of the charge pump control signal, and the output end of the charge pump is coupled with the grid electrode of the lower tube. According to the invention, the influence of Miller effect on the grid voltage of the lower tube can be effectively weakened or even offset, the problem of secondary conduction of the lower tube is solved, and the reliability of the BUCK system is enhanced.

The application provides a low-jitter millimeter wave multi-phase clock generation circuit, and relates to the technical field of high-frequency clock signal generation.The frequency multiplier module adopts a Gilbert structure frequency multiplier with a common base-emitter cascade structure to suppress the Miller effect, reduce nonlinear distortion and phase noise, and reduce clock jitter in the frequency multiplication process.Secondly, the multi-phase frequency divider module adopts a dynamic CML master-slave flip-flop, which omits the latch transistor and relies on the node capacitor to temporarily store data, eliminates the additional parasitic capacitance and delay mismatch caused by the latch transistor, and further suppresses random jitter.Finally, the phase calibration module uses the error signal of an external analog-to-digital converter to eliminate the fixed phase deviation by dynamically compensating the phase offset.Through the cooperative work of the frequency multiplier module, the multi-phase frequency divider module and the phase calibration module, the clock jitter in the millimeter wave frequency band is reduced, the phase accuracy is improved, and the signal-to-noise ratio and sampling accuracy of the ultrahigh-speed analog-to-digital converter are improved.

The application relates to the technical field of semiconductors, and particularly discloses a MOSFET device with low gate charge and a preparation method thereof, which comprises a P-type Si substrate, a LOCOS isolation layer, a shallowly-buried P-type electric field regulating layer under a channel, a transversely-doped gradient channel, a gate dielectric layer, a main gate, a shielding gate structure, an asymmetric LDD region, a source-side doping concentration of 1*10 18 cm ‑3 , a width of 0.1 mu m and a depth of 50 nm, a drain-side doping concentration of 5*10 17 cm ‑3 , a width of 0.15 mu m and a depth of 50 nm, two-stage stepped grooves in a drain region, a source-drain heavily-doped region and a metal electrode comprising a source, a main gate, a shielding gate and a drain. The application reduces the gate-drain coupling capacitance and the gate capacitance, suppresses the Miller effect, reduces the gate driving loss by combining the ultrathin gate and the NiSi silicide, simultaneously suppresses the sub-threshold leakage, doubly reduces the static and dynamic power consumption and prolongs the endurance of a sensor.