96 results about "Static timing analysis" patented technology

A method (of manufacturing a semiconductor device) includes migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, the migrating including: expanding a first version of the first netlist and a first precursor of the second netlist correspondingly to form a second version of the first netlist and a second precursor of the second netlist; before conducting (A) placement and routing (P&R) of a layout diagram corresponding to the second netlist or (B) a static timing analysis of the layout diagram; performing a logic equivalence check (LEC) between the second version of the first netlist and the second precursor of the second netlist, thereby identifying migration errors, and revising the second precursor of the second netlist to reduce the migration errors, thereby resulting in a third precursor of the second netlist.

A method includes: receiving a circuit design including circuit stages; deriving initial logic conditions for nets in a fanout cone from an input port in accordance with a primordial event; initializing a priority queue of logic transition events with the primordial event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all others in the priority queue and representing a logic transition at an input pin of a current circuit stage; simulating an arc of the circuit design from the input pin of the current circuit stage to an input pin of a fanout circuit stage to generate a propagated event; computing a propagated event timestamp based on: the trigger event timestamp; and a delay associated with the arc; enqueuing the propagated event on the priority queue; and generating a static analysis report based on the propagated event timestamp.

The invention provides a DFT clock architecture establishment method and device and electronic equipment, and belongs to the technical field of EDA, and the DFT clock architecture establishment method comprises the steps that a structured data file corresponding to clock planning information of a chip is acquired, the structured data file at least comprises an index field used for identifying clock uniqueness and a type field used for indicating a clock type, and the index field is used for identifying the clock uniqueness; and a parameter field for indicating clock attributes; generating a corresponding clock information object based on the values of the index field, the type field and the parameter field; based on the clock information object, a first configuration file and a second configuration file are generated, the first configuration file is used for driving a DFT tool to execute circuit insertion, and the second configuration file is used for driving a comprehensive or static timing analysis tool. The problems of configuration ambiguity, floating point error, asynchronous path omission, inconsistent OCC insertion and the like caused by dispersed and unstructured DFT clock planning information and dependence on manual transmission can be solved.

The invention provides a chip verification method and device, equipment and a storage medium, and relates to the technical field of chip verification, and the method comprises the steps: determining a static time sequence analysis result corresponding to a to-be-verified chip; according to the static time sequence analysis result, determining a plurality of target time sequence paths of which the time sequence allowances meet a preset time sequence allowance condition from the time sequence paths corresponding to the to-be-verified chip; and based on the target time sequence path, in combination with a preset verification strategy, executing a verification operation on the to-be-verified chip, the preset verification strategy is a verification strategy constructed based on low-power-consumption verification, gate-level simulation verification and interface verification. In this way, the target time sequence path can be screened out according to the static time sequence analysis result and the time sequence margin, targeted verification operation can be performed on the to-be-verified chip based on the target time sequence path, and the chip verification efficiency is improved; and chip verification is carried out in combination with multiple verification strategies, so that the chip verification effect can be further improved.

The invention belongs to the technical field of semiconductor design automation, and provides a digital circuit engineering correction method and related equipment. The method comprises the following steps: after wiring of a digital circuit is completed, performing static time sequence analysis based on actual circuit resistance-capacitance parasitic parameters of a time sequence path in the digital circuit to obtain global time sequence information of the time sequence path, and screening out an abnormal time sequence path containing an abnormal logic unit from the digital circuit based on the global time sequence information; performing logic unit change on the abnormal time sequence path containing the abnormal logic unit, and performing wiring change on the digital circuit after the logic unit change; and if the wiring violation does not exist in the digital circuit, returning to execute the step of performing the static time sequence analysis based on the actual circuit resistance-capacitance parasitic parameter of each time sequence path in the digital circuit until the abnormal time sequence path does not exist in the digital circuit. According to the technical scheme provided by the invention, the correction efficiency of the digital circuit engineering can be improved.

The invention belongs to the field of digital integrated chips, particularly relates to a clock tree generation and optimization method for quickly realizing time sequence convergence, and aims to solve the problems that an existing clock tree does not completely optimize a time sequence violation path and is difficult to realize quick time sequence convergence. The method comprises the following steps: carrying out logic synthesis on RTL codes to obtain a time sequence convergence netlist after logic synthesis; performing chip layout planning and hardware unit placement based on the time sequence convergence netlist; performing clock tree generation and clock tree comprehensive optimization on the chip with the hardware unit to obtain to-be-wired chip data with time sequence convergence; and based on the to-be-wired chip data, wiring of the to-be-wired chip is carried out according to preset parameters, and static time sequence analysis is carried out. According to the method, the frequency index of the chip is effectively optimized by combining an EDA tool, manually adjusting the clock tree structure and guiding the file, the number of iterations in the clock tree generation process and the time sequence optimization process after the clock tree generation process can be reduced, and the method is effective, reliable, convenient and practical.

The invention provides a cross-level error tracking and repairing method and system for a stacked chip system, and the method comprises the steps: marking a register, a signal or a state machine state when an RTL code is written during chip design, and keeping a first label written during the writing of the RTL code in a gate-level netlist when a comprehensive tool generates the RTL code into the gate-level netlist; when the gate-level netlist is converted into the physical layout in the physical implementation and layout wiring process, label information of marked objects on the gate-level netlist is reserved on the physical layout when the physical layout is generated; in the integrated design process of the chip, a new second label is injected for the interconnection channel in a packaging design tool; in the simulation analysis process, when it is found that a chip simulation result is abnormal, cross-level tracking and repairing are conducted on the position of an error through static time sequence analysis and power consumption analysis. The invention also provides a system for realizing the method. According to the method, error codes can be quickly positioned and repaired.

The invention provides a post-simulation method of an integrated circuit, electronic equipment and a storage medium, and relates to the technical field of chip design. The method comprises the following steps: based on a static time sequence analysis STA environment, obtaining a static time sequence analysis result of a physical implementation PR netlist corresponding to a register transfer level RTL module in a target integrated circuit; according to a static time sequence analysis result, obtaining an average clock network delay corresponding to an interface register in the PR netlist, a target establishment time and a target retention time of each input interface signal and a target output delay of each output interface signal, and constructing an interface signal delay model corresponding to the RTL module according to the average clock network delay, the target establishment time and the target retention time of each input interface signal and the target output delay of each output interface signal; according to the interface signal delay model and the RTL module, post-simulation processing is carried out, the interface signal delay model matched with the RTL module in time sequence can be constructed, in addition, the interface signal delay model can be combined with the RTL module to reduce the verification scale of a whole chip, the verification efficiency is improved, and the verification process is simplified.

The invention belongs to the technical field of integrated circuit post-simulation verification, and discloses an integrated circuit post-simulation system and method based on BFM and SDF inverse labeling, the system comprises a BFM packaging module used for describing a time sequence path of a port output signal and instantiating a BFM module or connecting an interface signal of a verification IP, an SDF generating assembly used for generating a BFM signal, and an SDF generating assembly used for generating an SDF signal. The static time sequence analysis database module is used for extracting delay information corresponding to a port output signal in a BFM or verification IP interface from the static time sequence analysis database and generating an SDF file according to the delay information, and the top layer verification environment module is used for reversely marking the SDF file to the BFM packaging module and running a test case. According to the method, the delay information of the BFM under each process corner is rapidly extracted by using the SDF generation component, the independent SDF file is generated and is reversely marked to the BFM packaging module, so that a real port time sequence can be simulated, multiple iterations are not needed, a large amount of manpower and time cost is saved, the delay information adding speed of the BFM is remarkably improved, and the error rate is reduced.

The embodiment of the invention discloses an asynchronous path acquisition method and device for a chip, electronic equipment and a storage medium. According to the scheme, in the process of performing static time sequence analysis on the test chip, time sequence violation check can be performed on the test chip by adding the time sequence analysis command, the asynchronous path is obtained based on the time sequence violation check result, and the starting endpoint and the ending endpoint of the asynchronous path are traversed, so that the accuracy of the static time sequence analysis is improved. And carrying out preliminary screening on the asynchronous paths according to the traversed clock signals, and excluding associated registers in the asynchronous paths according to beating nodes of a synchronizer so as to realize secondary screening on the asynchronous paths. According to the method, the asynchronous path is captured from the time sequence report in a mode of constructing the time sequence violation, and screening is performed based on the end points of the asynchronous path, so that the capturing and screening efficiency of the asynchronous path is effectively improved.

The invention provides a circuit energy efficiency automatic optimization method. The method comprises the following steps: firstly, modeling a circuit gate-level netlist into a directed graph; extracting a key path by using a static time sequence analysis tool, and extracting a context sensing key sub-graph containing the path and a first-order neighborhood node of the path; thirdly, feature coding is conducted on the key sub-graphs through a graph neural network, and state vectors representing the local state of the circuit are generated; the state vector is input to a reinforcement learning policy network to decide a drive capability adjustment action for a particular standard cell. And the system modifies the netlist according to the action, calls the static time sequence analysis tool again to evaluate the modified performance, power consumption and area indexes, and generates a reward signal to iteratively optimize the strategy network. By constructing the closed-loop optimization process, the problems of low manual optimization efficiency and unbalanced power consumption and area balance are solved, automatic and intelligent collaborative optimization of circuit energy efficiency is realized, and the design quality and efficiency are remarkably improved.

The invention relates to the technical field of chip simulation, in particular to a chip simulation method, a chip simulation device, chip simulation equipment and a medium, the method comprises the following steps: in a comprehensive logic stage of a chip, performing comprehensive logic simulation after reading an actual layout plan to obtain a comprehensive netlist, the comprehensive netlist comprises interconnection line delay data and time sequence library information, the layout planning comprises specific position information of a hard core and a standard unit of the chip; generating a standard delay format file according to the interconnection line delay data and the time sequence library information; the integrated netlist and the standard delay format file are read into a static time sequence analysis tool for integration post-simulation, and a time sequence report is obtained; and determining whether a time sequence problem exists or not according to the time sequence report, and if so, repairing the path with the time sequence problem. According to the method, the accurate delay problem can be obtained through quick simulation.

The invention relates to a method for rapidly counting and analyzing massive time sequence violation paths. The method comprises the following steps of: performing read operation on a time sequence report file generated by a static time sequence analysis tool by adopting a storage I / O mapping technology in a shared memory, and separating an original file into a plurality of independent fragments according to a multi-mode character string matching algorithm, starting a plurality of sub-threads and distributing information of corresponding fragments of the original file to the sub-threads; adopting a multi-mode character string matching algorithm to obtain specific attributes of a time sequence violation path according to the keyword information; the sub-threads are used for carrying out attribute extraction and distribution statistics according to specific attributes in sequence, and after the main thread receives that the sub-threads complete attribute extraction and distribution statistics, various kinds of distribution statistics information of the sub-threads is merged into a total statistical table of the main thread according to a rapid sorting algorithm to generate various kinds of distribution statistics sorting information. By adopting the method, rapid statistics and analysis of massive time sequence violation paths can be realized.

In an embodiment of the present disclosure, a timing optimization method is provided, comprising: performing static timing analysis on the integrated circuit and obtaining a path to be processed in the integrated circuit; determining a network to be processed based on the path to be processed, wherein the network to be processed includes a network appearing on the path to be processed; isolating the load in each network to be processed, wherein the load isolation includes classifying the load in the network to be processed, wherein the classification results include critical loads and non-critical loads, and adding buffer units around the non-critical loads; and the load classification includes trying different load marking schemes, estimating the delay variation of each marking result, and selecting the best scheme to classify the loads. The processing scheme disclosed in the present disclosure can improve the efficiency of timing convergence on critical paths.

The invention provides a static time sequence analysis method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the voltage drop analysis of at least one logic unit on a target time sequence path, obtaining an original voltage drop file, and carrying out the voltage drop analysis of at least one logic unit from the original voltage drop file according to the reading information indicated by a reading command of a static time sequence analysis tool, acquiring a signal overturning direction of each logic unit and a dynamic voltage drop corresponding to the signal overturning direction, and according to a data form indicated by a write-in command of a static time sequence analysis tool, generating a target voltage drop file from the signal overturning direction and the dynamic voltage drop according to the data form, and performing static time sequence analysis on the target voltage drop file by adopting a static time sequence analysis tool. Required information is read out and written into the generated target voltage drop file in a tool command form, redundant information is abandoned, the information can be directly called in a static time sequence analysis tool, and the execution efficiency and iteration speed of static time sequence analysis are improved.

The invention provides a method for repairing retention time violation. The method comprises the following steps: acquiring a network list and a layout result of an FPGA (Field Programmable Gate Array); the network list comprises a connection relationship between the target sending unit and the target receiving unit, and the layout result comprises respective layout coordinates of the target sending unit and the target receiving unit; the target sending unit and the target receiving unit are driven by the same time signal; based on the respective layout coordinates of the target sending unit and the target receiving unit, evaluating the path time delay of the connection path by using a static time sequence analysis tool; and when the path time delay is smaller than a path time delay threshold value, adding an unused lookup table of at least one FPGA into the connection relation, and on the premise of not changing a layout result, determining respective layout coordinates of the at least one unused lookup table based on the layout result so as to repair retention time violation of the connection path. Therefore, the retention time violation of the connection path can be quickly repaired by adding the unused lookup table of the FPGA in the layout stage.

The invention discloses a stress simulation excitation waveform construction method and device, electronic equipment and a storage medium, and relates to the technical field of electronic design automation, and the method comprises the steps: extracting clock constraint, a time sequence path and waveform activeness data based on a static time sequence analysis tool, and building a reference time sequence library and a waveform activeness library; for an input pin of a target unit instance, the transmission time, the average signal static probability and the average signal activeness of the input pin are obtained. And generating a regular pulse waveform for the clock input pin, generating a random fragment linear waveform for the data input pin, performing rationality verification on waveform parameters, generating a stress simulation excitation waveform if the waveform parameters pass the rationality verification, and adaptively adjusting the waveform parameters if the waveform parameters do not pass the rationality verification until the stress simulation excitation waveform is generated. The method has the technical effects that stress simulation is carried out by taking the unit instance as granularity, the uniqueness of degradation parameters of the same unit instance is ensured, the generated excitation waveform better fits an actual working scene, and the aging simulation analysis accuracy is improved.

The present application belongs to the technical field of low power consumption of integrated circuit design, and discloses a multi-threshold voltage unit distribution method, comprising the following steps: step 1: data preparation: obtaining a simplified path set according to a full high threshold circuit, and obtaining unit delay, timing increase / decrease factor and static power consumption value of the full high / low threshold circuit; step 2: distributing threshold according to the path set: distributing threshold point by point in the full high threshold circuit according to path weight and unit weight until the paths in the path set all meet timing requirements; and step 3: updating the path set: applying the threshold distribution result and performing static timing analysis, if the static timing analysis result does not meet timing, updating the path set and performing the threshold distribution operation according to the path set again until the static timing analysis result meets timing. The present application effectively reduces the method running time through the simplified path set, and ensures threshold distribution accuracy and timing convergence through updating the path set.

The invention discloses a digital integrated circuit layout stage buffer insertion prediction method, electronic equipment and a storage medium, and the method comprises the steps: firstly, carrying out the physical design and static time sequence analysis of a circuit through a physical design tool and a static time sequence analysis tool, and extracting the time sequence and physical information of each unit before layout; secondly, learning the dependency relationship among the units of the circuit through a self-attention mechanism, and predicting the type and position of buffer insertion after layout in combination with multi-task learning; compared with a heuristic algorithm and a traditional machine learning algorithm, the method has the advantages that the buffer insertion type and position after layout can be efficiently predicted before layout, so that guidance is provided for the early stage of digital integrated circuit design, and the design iteration period is remarkably shortened.

Embodiments of the invention are directed to a computer-implemented method of analyzing timing constraints of a component-under-design (CUD). The computer-implemented method includes performing an initial iteration of a common path pessimism removal (CPPR) analysis on circuit elements of the CUD. The circuit elements includes inputs and outputs, and the circuit elements further include a transparent circuit element. The computer-implemented method further includes storing an initial list of the inputs and the outputs for which timing was adjusted during the initial iteration; and applying a second iteration of the CPPR analysis to the initial list of the inputs and the outputs.

The present technology includes performance-driven logic optimization for logic synthesis. A ground-truth dataset is generated based on technology mapping and static timing analysis of a set of gate-level netlists generated from a set of And-Inverter Graphs (AIGs). The ground-truth dataset is used to train a machine learning (ML) model to predict area and delay metrics. The trained ML model is used to predicted area and delay metrics for each AIG in another set of AIGs. A reward is calculated for each AIG in the other set of AIGs based on the predicted area and delay metrics. An AIG in the other set of AIGs having a smallest reward is selected as an optimal AIG. Technology mapping is performed on the optimal AIG to generate another gate-level netlist for use in one or more physical integrated circuit design processes.

The invention provides a static time sequence analysis method and device of a chip, electronic equipment and a storage medium, and relates to the technical field of chips. Comprising the following steps: determining punch-through paths of a clock source among sub-modules and internal time sequence information of the sub-modules according to an initial time sequence analysis result of a target chip; according to the punch-through path of the clock source among the sub-modules and the internal time sequence information of the sub-modules, simplifying and adjusting the netlist of the target chip, and retaining a time sequence association module and a time sequence association logic block of the target sub-module; and performing static time sequence analysis according to the time sequence association module and the time sequence association logic block of the target sub-module to generate a time sequence analysis result of the target sub-module. According to the method, the analysis data volume during static time sequence analysis is reduced, and the operation time of time sequence analysis is shortened. The dependence of static time sequence analysis on the chip development progress is relieved, and the overall progress of static time sequence analysis is improved.

The invention provides a static time sequence analysis method and device before chip layout based on machine learning. And more accurate local delay is obtained by utilizing machine learning, so that the accuracy of static time sequence analysis before layout is improved. In order to solve the challenge of line length information loss, the invention provides a first pin-level line length predictor, and a Manhattan distance between pins is estimated by using a distributed gradient enhancement library as an approximate value of a pin-level lead length. In order to solve the challenge that the unit type is variable, the invention designs a dynamic increment delay prediction scheme, and the method uses a local delay calculated by Synopsys IC Compiler before layout as an input feature to predict the increment of the Synopsys IC Compiler. In addition, due to the fact that the calculation load is reduced, the running speed of the prediction method based on the machine learning algorithm is higher than that of a deterministic algorithm in a current electronic design automation tool.

The application provides a critical path monitoring point screening method and system combining path activation rate and similarity, comprising: obtaining timing information of all paths of a target circuit based on static timing analysis, and screening paths with timing margin less than a preset timing margin threshold to form a critical path set; based on a preset benchmark test set, performing signal flip statistics on monitoring points of each path in the critical path set, calculating the activation rate of each path, and filtering out paths with zero activation rate to obtain an effective path set; grouping paths in the effective path set according to the starting points of the paths to obtain a plurality of path groups; for each path group, calculating the similarity between paths based on the logical topology structure sequence of the paths in the group, and clustering the paths according to the similarity, and screening at least one path from each cluster; and collecting paths obtained after screening of all path groups to form a final monitoring point set.

The application provides a stacked chip system cross-level error tracking repair method and system, which comprises the following steps: during chip design, marking registers, signals or state machine states when writing RTL code; during the process of generating a gate-level netlist from the RTL code, reserving the first label written in the gate-level netlist by a synthesis tool; during the process of converting the gate-level netlist into a physical layout, reserving the label information of the marked objects on the gate-level netlist on the physical layout when the physical layout is generated; during the process of integrated design of the chip, injecting a new second label into an interconnection channel in a packaging design tool; during the process of simulation analysis, locating the error position and repairing the error through static timing analysis and power consumption analysis when an abnormal chip simulation result is found. The application also provides a system for implementing the above method. The application can quickly locate error code and repair the error.

The application relates to the field of integrated circuit design and verification technology, and discloses a fast repairing method and device for establishing time violation in static timing analysis. The method comprises the following steps: obtaining a static timing analysis report; extracting a target timing path according to the static timing analysis report; calculating a plurality of types of redundancy values of each module passed through by the target timing path; calculating a redundancy value set of a data path of the target timing path and a redundancy value subset corresponding to each module according to the redundancy values of the modules corresponding to the target timing path; determining a repairing sequence of each module according to the redundancy values of the modules corresponding to the target timing path; analyzing each module according to the redundancy value set and the redundancy value subset of each module in sequence to determine a repairing scheme of each module; and obtaining a repairing strategy of the target timing path according to the repairing schemes of the modules passed through by the target timing path. The application provides an efficient solution for an early stage of time repairing.

The invention discloses an AI-assisted time sequence report analysis method, and belongs to the technical field of integrated circuit design automation. The method comprises the following steps: acquiring a static time sequence analysis report; analyzing the report through an analysis rule base, and extracting structured information of a time sequence path; performing hierarchical grouping on the plurality of analyzed time sequence paths according to time sequence grouping, clock domains and violation types to generate time sequence statistical characteristics; and identifying a key path according to the time sequence statistical characteristics, and outputting a structured analysis result and an optimization suggestion. Through automatic analysis and intelligent analysis, the time sequence debugging efficiency is remarkably improved, dependence on experience of engineers is reduced, and the method is suitable for time sequence convergence scenes of large-scale integrated circuit design.

The invention provides a static time sequence analysis method and device, a server and a storage medium, and is applied to the technical field of computers. The method comprises the following steps: obtaining an average voltage drop value corresponding to each polarity overturning event of each logic unit in an integrated circuit in a target time interval; determining the actual voltage value of each logic unit in each clock period, determining the actual unit delay corresponding to the actual voltage value of each logic unit, and finally determining the establishment time margin and the retention time margin of the time sequence path according to the actual unit delay of each logic unit. According to the method, the actual voltage value of the corresponding logic unit is determined based on the difference between the nominal voltage and the average voltage drop value, the influence of voltage fluctuation in the power supply network on the actual working voltage of the logic unit is considered, and the actual unit delay determined based on the actual voltage value is reversely marked; and the reliability of the retention time margin and the establishment time margin obtained through calculation is ensured, so that the accuracy of a static time sequence analysis result is improved.

The invention discloses a digital circuit aging simulation method based on a critical path. The method comprises the following steps: extracting the critical path of a digital circuit by using a static time sequence analysis tool; screening potential critical paths by utilizing an aging worst-case analysis method; obtaining a key path and a netlist file excited by the key path; obtaining time delay, not including aging, of the key path through simulation before aging; changing the excitation of the key path and generating dynamic simulation excitation; performing key path dynamic aging simulation in combination with an existing aging model to obtain electrical parameter degradation amounts of all devices; converting the device degradation amount into an aged model netlist; and in combination with the aged model netlist, performing simulation after aging of the key path to obtain delay after aging of the path. According to the method, SPICE-level aging simulation is carried out on the critical path of the digital circuit to predict the actual performance degradation condition of the circuit, so that more accurate data support is provided for circuit optimization design.

The invention relates to the technical field of digital circuits, in particular to a method, device and equipment for reducing peak current, a medium and a digital circuit, and the method comprises the steps: obtaining the peak moment of the maximum instantaneous peak current of a target circuit; performing static time sequence analysis on the target circuit, acquiring arrival time and required time of each path in the target circuit, and taking a difference value obtained by subtracting the arrival time from the required time as a time sequence margin; determining the path of which the time sequence margin is greater than 0 as a non-critical path; acquiring a non-critical path where a target logic gate flipped at the peak moment is located as an insertion path; the time delay units are inserted into the insertion paths, so that the target logic gates of the insertion paths are staggered in the overturning time, the total time delay D of the time delay units inserted into the insertion paths meets the condition that D is smaller than or equal to Si-delta, Si is the time sequence margin of the insertion paths, and delta is the preset safety time sequence margin. The technical scheme can reduce the peak current of the digital circuit, and is mainly used for digital circuit design.