112 results about "Static timing analysis" patented technology

The invention provides an EDA software implementation method and system for memory IP layout optimization, and relates to the technical field of memorizers, the method comprises the following steps: receiving a memory IP design parameter and an optimization target input by a user, and calling a matched basic unit module from a pre-established hierarchical memory IP library according to the design parameter; an initial memory IP layout scheme is generated based on the basic unit module, the initial memory IP layout scheme is rapidly evaluated by utilizing a neural network model, a plurality of optimized layout candidate schemes are generated by adopting a genetic algorithm, and each optimized layout candidate scheme comprises different basic unit arrangements, metal layer use strategies and buffer insertion positions; performing parallel simulation on the optimal layout candidate scheme, and selecting an optimal layout scheme; and performing post-simulation verification on the optimal layout scheme, wherein the post-simulation verification comprises static time sequence analysis, dynamic power consumption analysis and electromagnetic compatibility analysis.

The present invention relates to the technical field of calculation, estimation or counting. Disclosed is a critical path sorting method based on a graph neural network. The method comprises: first, obtaining a potential critical path set in a netlist by means of a static timing analysis tool; next, converting a netlist file comprising circuit function information into a graph data structure, and obtaining an initial training set on the basis of a relevant process configuration file; then, inputting the initial training set into a graph neural network for training to obtain a critical unit prediction model, wherein the critical unit prediction model consists of three parts, namely, a deep structure auto-encoder, a nonlinear attribute auto-encoder and a joint error reconstruction module; and finally, quantifying the criticality of each path in the potential critical path set on the basis of critical unit information and a path criticality calculation algorithm in the netlist, and obtaining a critical path sequence under process awareness. According to the method, critical paths in circuits influenced by process deviations can be effectively sorted, providing valuable reference for circuit optimization.

The invention discloses a Multi-Point CTS-based chip clock design optimization method, and relates to the technical field of chip clock design optimization, and the method comprises the following steps: using a hardware description language VHDL to compile RTL codes describing circuit behaviors, using a DC EDA tool of Synopsys to convert the RTL codes into a logic netlist, using a standard algorithm H-Tree to construct a preliminary clock tree structure layout, and using the standard algorithm H-Tree to construct the logic netlist. Obtaining a primary clock tree topological graph; a Multi-Point CTS method is introduced, a plurality of clock sources are adopted to optimize the initial clock tree topological graph, and an optimized clock tree topological graph is obtained; a static time sequence analysis tool PrimeTime is adopted to analyze the optimized clock tree topological graph, and a time sequence analysis result is obtained; identifying the longest path from a clock source to a register in the optimized clock tree topological graph according to a time sequence analysis result, marking the longest path as a critical path, and finding the optimal position for placing a buffer in the critical path by adopting a heuristic search algorithm; and calculating a difference value between the actual delay and the maximum allowable delay of the optimized clock tree topological graph by using PrimeTime again.

The embodiment of the invention discloses a static time sequence analysis method and device based on layout features and electronic equipment. According to the scheme, the gate-level netlist of the circuit can be obtained, the time sequence diagram is established according to the gate-level netlist, the nodes and the directed edges in the time sequence diagram are filled with the first statistical characteristics respectively, the first layout characteristics of each connection network in the time sequence diagram are calculated, and the time sequence diagram is expanded according to the first layout characteristics; and constructing a static time sequence analysis prediction model based on the graph neural network and the convolutional neural network, and predicting the delay of a connecting line time sequence arc, the delay of a logic gate time sequence arc and the delay of a pin node in the expanded time sequence diagram, thereby determining a static time sequence analysis result. According to the method, the layout characteristics of the circuit are obtained by extracting and coding the nodes of the connection network, and the static time sequence analysis prediction model is modeled according to the layout characteristics, so that the prediction accuracy of the prediction model in the layout areas with different aspect ratios is improved.

The invention belongs to the field of electronic design automation and static time sequence analysis, particularly relates to a parallel optimization method for FPGA static time sequence analysis, and aims to solve the problems of low calculation efficiency and long compiling time of static time sequence analysis in the prior art. The method comprises the following steps: performing memory layout optimization on a time sequence diagram and time sequence constraints according to a built FPGA-oriented STA data structure; task decomposition is carried out, calculation tasks of nodes and edges of each hierarchy are allocated to a plurality of parallel kernels to be executed in parallel, and single CPU threads are allocated to different hierarchies to be executed in sequence; during execution, traversing the time sequence diagram, and marking to-be-updated nodes and edges; and obtaining effective arrival time and effective demand time of the nodes through bidirectional traversal calculation, determining a key path in FPGA (Field Programmable Gate Array) time sequence static analysis, and generating a parallel optimization report of the FPGA static time sequence analysis. According to the method, the calculation efficiency in static time sequence analysis is improved, and the compiling time is shortened.

A method (of manufacturing a semiconductor device) includes migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, the migrating including: expanding a first version of the first netlist and a first precursor of the second netlist correspondingly to form a second version of the first netlist and a second precursor of the second netlist; before conducting (A) placement and routing (P&R) of a layout diagram corresponding to the second netlist or (B) a static timing analysis of the layout diagram; performing a logic equivalence check (LEC) between the second version of the first netlist and the second precursor of the second netlist, thereby identifying migration errors, and revising the second precursor of the second netlist to reduce the migration errors, thereby resulting in a third precursor of the second netlist.

The invention is applicable to the technical field of integrated circuit design, and provides a method for repairing crosstalk noise violation on a data path, which comprises the following steps of: reading a crosstalk noise violation report of a static time sequence analysis STA tool; finding an interconnection line corresponding to each violation in the report from a layout wiring tool, and finding adjacent interconnection line position information and connected logic unit information of the current interconnection line; selecting a corresponding repairing scheme according to the specific conditions of the interconnection lines and the connected logic units, and executing and adjusting the repairing scheme so as to repair crosstalk noise on a data path; and after a round of repair is completed, if crosstalk noise violation is also detected in the STA tool, the steps need to be executed again until all crosstalk noise problems are solved. According to the method provided by the invention, the crosstalk problem is efficiently identified and solved through an automatic process, the signal integrity and the function correctness of circuit design are ensured, and compared with a traditional scheme, the method is more targeted, and the gain brought by single change is favorably improved.

The invention discloses a chip network weight time sequence driven global layout method, which belongs to the technical field of computer aided design, and comprises the following steps: carrying out initial layout according to a global layout algorithm to obtain an initial layout chip network; optimizing the initial layout chip network; updating the time sequence and layout parameters of the chip network after layout optimization by using a Nadam gradient optimization algorithm; and judging whether the updated parameters are converged or not, if not, continuing iterative optimization, and if yes, entering a legalization stage. According to the method, the chip network weight after layout optimization is dynamically updated through static time sequence analysis, the convergence of a layout objective function is improved by using first-order and second-order momentum gradients of a Nadam method, and a historical gradient is added in gradient descent to reduce oscillation. According to the invention, the efficiency and performance of circuit design are effectively improved, time sequence violation is reduced, and time sequence convergence is ensured.

A method includes: receiving a circuit design including circuit stages; deriving initial logic conditions for nets in a fanout cone from an input port in accordance with a primordial event; initializing a priority queue of logic transition events with the primordial event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all others in the priority queue and representing a logic transition at an input pin of a current circuit stage; simulating an arc of the circuit design from the input pin of the current circuit stage to an input pin of a fanout circuit stage to generate a propagated event; computing a propagated event timestamp based on: the trigger event timestamp; and a delay associated with the arc; enqueuing the propagated event on the priority queue; and generating a static analysis report based on the propagated event timestamp.

The invention relates to the technical field of microcircuit analysis, and discloses a classification method and equipment for static time sequence analysis reports. The method comprises the following steps: determining the type of a static time sequence analysis report of a target time sequence path; if the static time sequence analysis report is of an establishment time type, dividing a data path of the target time sequence path into an intra-module path and a cross-module path; dividing violations existing in the paths in the modules to the corresponding modules to obtain a first violation division result; determining a plurality of target modules corresponding to the cross-module path with violation; calculating the violation value contribution degree of each target module; according to the violation value contribution degree of each target module, dividing violations existing in the cross-module path to the corresponding target modules to obtain a second violation division result; and determining the violation of the target time sequence path belonging to each module according to the first violation division result and the second violation division result. The static time sequence analysis report can be efficiently processed, and efficiency and accuracy are improved.

The invention provides a DFT clock architecture establishment method and device and electronic equipment, and belongs to the technical field of EDA, and the DFT clock architecture establishment method comprises the steps that a structured data file corresponding to clock planning information of a chip is acquired, the structured data file at least comprises an index field used for identifying clock uniqueness and a type field used for indicating a clock type, and the index field is used for identifying the clock uniqueness; and a parameter field for indicating clock attributes; generating a corresponding clock information object based on the values of the index field, the type field and the parameter field; based on the clock information object, a first configuration file and a second configuration file are generated, the first configuration file is used for driving a DFT tool to execute circuit insertion, and the second configuration file is used for driving a comprehensive or static timing analysis tool. The problems of configuration ambiguity, floating point error, asynchronous path omission, inconsistent OCC insertion and the like caused by dispersed and unstructured DFT clock planning information and dependence on manual transmission can be solved.

The invention provides a chip verification method and device, equipment and a storage medium, and relates to the technical field of chip verification, and the method comprises the steps: determining a static time sequence analysis result corresponding to a to-be-verified chip; according to the static time sequence analysis result, determining a plurality of target time sequence paths of which the time sequence allowances meet a preset time sequence allowance condition from the time sequence paths corresponding to the to-be-verified chip; and based on the target time sequence path, in combination with a preset verification strategy, executing a verification operation on the to-be-verified chip, the preset verification strategy is a verification strategy constructed based on low-power-consumption verification, gate-level simulation verification and interface verification. In this way, the target time sequence path can be screened out according to the static time sequence analysis result and the time sequence margin, targeted verification operation can be performed on the to-be-verified chip based on the target time sequence path, and the chip verification efficiency is improved; and chip verification is carried out in combination with multiple verification strategies, so that the chip verification effect can be further improved.

The invention belongs to the technical field of semiconductor design automation, and provides a digital circuit engineering correction method and related equipment. The method comprises the following steps: after wiring of a digital circuit is completed, performing static time sequence analysis based on actual circuit resistance-capacitance parasitic parameters of a time sequence path in the digital circuit to obtain global time sequence information of the time sequence path, and screening out an abnormal time sequence path containing an abnormal logic unit from the digital circuit based on the global time sequence information; performing logic unit change on the abnormal time sequence path containing the abnormal logic unit, and performing wiring change on the digital circuit after the logic unit change; and if the wiring violation does not exist in the digital circuit, returning to execute the step of performing the static time sequence analysis based on the actual circuit resistance-capacitance parasitic parameter of each time sequence path in the digital circuit until the abnormal time sequence path does not exist in the digital circuit. According to the technical scheme provided by the invention, the correction efficiency of the digital circuit engineering can be improved.

The invention belongs to the field of digital integrated chips, particularly relates to a clock tree generation and optimization method for quickly realizing time sequence convergence, and aims to solve the problems that an existing clock tree does not completely optimize a time sequence violation path and is difficult to realize quick time sequence convergence. The method comprises the following steps: carrying out logic synthesis on RTL codes to obtain a time sequence convergence netlist after logic synthesis; performing chip layout planning and hardware unit placement based on the time sequence convergence netlist; performing clock tree generation and clock tree comprehensive optimization on the chip with the hardware unit to obtain to-be-wired chip data with time sequence convergence; and based on the to-be-wired chip data, wiring of the to-be-wired chip is carried out according to preset parameters, and static time sequence analysis is carried out. According to the method, the frequency index of the chip is effectively optimized by combining an EDA tool, manually adjusting the clock tree structure and guiding the file, the number of iterations in the clock tree generation process and the time sequence optimization process after the clock tree generation process can be reduced, and the method is effective, reliable, convenient and practical.

The invention provides an integrated circuit winding optimization method and device, electronic equipment and a storage medium, and belongs to the technical field of integrated circuits. The method comprises the following steps: acquiring time sequence path index threshold information and winding index threshold information; performing static time sequence analysis on the wound integrated circuit to obtain static time sequence information; determining key path information according to the static time sequence information and time sequence path index threshold information; determining a driving position of the interconnection line to be optimized according to the key path information and the winding index threshold information; the winding attribute corresponding to the driving position of the to-be-optimized interconnection line is reset to be the through hole column winding attribute, so that parasitic parameters of the interconnection line in key path information can be reduced, the part with large delay of the interconnection line is effectively reduced, the proportion of the delay of the interconnection line to the delay of the whole circuit is reduced accordingly, the time sequence requirement can be met, and the optimization efficiency of the interconnection line is improved. The area and the number of the driving units are saved, and the power consumption, the performance and the area of the integrated circuit can be more accurately optimized.

The invention provides a cross-level error tracking and repairing method and system for a stacked chip system, and the method comprises the steps: marking a register, a signal or a state machine state when an RTL code is written during chip design, and keeping a first label written during the writing of the RTL code in a gate-level netlist when a comprehensive tool generates the RTL code into the gate-level netlist; when the gate-level netlist is converted into the physical layout in the physical implementation and layout wiring process, label information of marked objects on the gate-level netlist is reserved on the physical layout when the physical layout is generated; in the integrated design process of the chip, a new second label is injected for the interconnection channel in a packaging design tool; in the simulation analysis process, when it is found that a chip simulation result is abnormal, cross-level tracking and repairing are conducted on the position of an error through static time sequence analysis and power consumption analysis. The invention also provides a system for realizing the method. According to the method, error codes can be quickly positioned and repaired.

The invention provides a post-simulation method of an integrated circuit, electronic equipment and a storage medium, and relates to the technical field of chip design. The method comprises the following steps: based on a static time sequence analysis STA environment, obtaining a static time sequence analysis result of a physical implementation PR netlist corresponding to a register transfer level RTL module in a target integrated circuit; according to a static time sequence analysis result, obtaining an average clock network delay corresponding to an interface register in the PR netlist, a target establishment time and a target retention time of each input interface signal and a target output delay of each output interface signal, and constructing an interface signal delay model corresponding to the RTL module according to the average clock network delay, the target establishment time and the target retention time of each input interface signal and the target output delay of each output interface signal; according to the interface signal delay model and the RTL module, post-simulation processing is carried out, the interface signal delay model matched with the RTL module in time sequence can be constructed, in addition, the interface signal delay model can be combined with the RTL module to reduce the verification scale of a whole chip, the verification efficiency is improved, and the verification process is simplified.

The invention belongs to the technical field of integrated circuit post-simulation verification, and discloses an integrated circuit post-simulation system and method based on BFM and SDF inverse labeling, the system comprises a BFM packaging module used for describing a time sequence path of a port output signal and instantiating a BFM module or connecting an interface signal of a verification IP, an SDF generating assembly used for generating a BFM signal, and an SDF generating assembly used for generating an SDF signal. The static time sequence analysis database module is used for extracting delay information corresponding to a port output signal in a BFM or verification IP interface from the static time sequence analysis database and generating an SDF file according to the delay information, and the top layer verification environment module is used for reversely marking the SDF file to the BFM packaging module and running a test case. According to the method, the delay information of the BFM under each process corner is rapidly extracted by using the SDF generation component, the independent SDF file is generated and is reversely marked to the BFM packaging module, so that a real port time sequence can be simulated, multiple iterations are not needed, a large amount of manpower and time cost is saved, the delay information adding speed of the BFM is remarkably improved, and the error rate is reduced.

The embodiment of the invention discloses an asynchronous path acquisition method and device for a chip, electronic equipment and a storage medium. According to the scheme, in the process of performing static time sequence analysis on the test chip, time sequence violation check can be performed on the test chip by adding the time sequence analysis command, the asynchronous path is obtained based on the time sequence violation check result, and the starting endpoint and the ending endpoint of the asynchronous path are traversed, so that the accuracy of the static time sequence analysis is improved. And carrying out preliminary screening on the asynchronous paths according to the traversed clock signals, and excluding associated registers in the asynchronous paths according to beating nodes of a synchronizer so as to realize secondary screening on the asynchronous paths. According to the method, the asynchronous path is captured from the time sequence report in a mode of constructing the time sequence violation, and screening is performed based on the end points of the asynchronous path, so that the capturing and screening efficiency of the asynchronous path is effectively improved.

The invention provides a circuit energy efficiency automatic optimization method. The method comprises the following steps: firstly, modeling a circuit gate-level netlist into a directed graph; extracting a key path by using a static time sequence analysis tool, and extracting a context sensing key sub-graph containing the path and a first-order neighborhood node of the path; thirdly, feature coding is conducted on the key sub-graphs through a graph neural network, and state vectors representing the local state of the circuit are generated; the state vector is input to a reinforcement learning policy network to decide a drive capability adjustment action for a particular standard cell. And the system modifies the netlist according to the action, calls the static time sequence analysis tool again to evaluate the modified performance, power consumption and area indexes, and generates a reward signal to iteratively optimize the strategy network. By constructing the closed-loop optimization process, the problems of low manual optimization efficiency and unbalanced power consumption and area balance are solved, automatic and intelligent collaborative optimization of circuit energy efficiency is realized, and the design quality and efficiency are remarkably improved.

The invention relates to the technical field of chip simulation, in particular to a chip simulation method, a chip simulation device, chip simulation equipment and a medium, the method comprises the following steps: in a comprehensive logic stage of a chip, performing comprehensive logic simulation after reading an actual layout plan to obtain a comprehensive netlist, the comprehensive netlist comprises interconnection line delay data and time sequence library information, the layout planning comprises specific position information of a hard core and a standard unit of the chip; generating a standard delay format file according to the interconnection line delay data and the time sequence library information; the integrated netlist and the standard delay format file are read into a static time sequence analysis tool for integration post-simulation, and a time sequence report is obtained; and determining whether a time sequence problem exists or not according to the time sequence report, and if so, repairing the path with the time sequence problem. According to the method, the accurate delay problem can be obtained through quick simulation.

The invention relates to a method for rapidly counting and analyzing massive time sequence violation paths. The method comprises the following steps of: performing read operation on a time sequence report file generated by a static time sequence analysis tool by adopting a storage I / O mapping technology in a shared memory, and separating an original file into a plurality of independent fragments according to a multi-mode character string matching algorithm, starting a plurality of sub-threads and distributing information of corresponding fragments of the original file to the sub-threads; adopting a multi-mode character string matching algorithm to obtain specific attributes of a time sequence violation path according to the keyword information; the sub-threads are used for carrying out attribute extraction and distribution statistics according to specific attributes in sequence, and after the main thread receives that the sub-threads complete attribute extraction and distribution statistics, various kinds of distribution statistics information of the sub-threads is merged into a total statistical table of the main thread according to a rapid sorting algorithm to generate various kinds of distribution statistics sorting information. By adopting the method, rapid statistics and analysis of massive time sequence violation paths can be realized.

In an embodiment of the present disclosure, a timing optimization method is provided, comprising: performing static timing analysis on the integrated circuit and obtaining a path to be processed in the integrated circuit; determining a network to be processed based on the path to be processed, wherein the network to be processed includes a network appearing on the path to be processed; isolating the load in each network to be processed, wherein the load isolation includes classifying the load in the network to be processed, wherein the classification results include critical loads and non-critical loads, and adding buffer units around the non-critical loads; and the load classification includes trying different load marking schemes, estimating the delay variation of each marking result, and selecting the best scheme to classify the loads. The processing scheme disclosed in the present disclosure can improve the efficiency of timing convergence on critical paths.

The invention provides a static time sequence analysis method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the voltage drop analysis of at least one logic unit on a target time sequence path, obtaining an original voltage drop file, and carrying out the voltage drop analysis of at least one logic unit from the original voltage drop file according to the reading information indicated by a reading command of a static time sequence analysis tool, acquiring a signal overturning direction of each logic unit and a dynamic voltage drop corresponding to the signal overturning direction, and according to a data form indicated by a write-in command of a static time sequence analysis tool, generating a target voltage drop file from the signal overturning direction and the dynamic voltage drop according to the data form, and performing static time sequence analysis on the target voltage drop file by adopting a static time sequence analysis tool. Required information is read out and written into the generated target voltage drop file in a tool command form, redundant information is abandoned, the information can be directly called in a static time sequence analysis tool, and the execution efficiency and iteration speed of static time sequence analysis are improved.

The invention provides a method for repairing retention time violation. The method comprises the following steps: acquiring a network list and a layout result of an FPGA (Field Programmable Gate Array); the network list comprises a connection relationship between the target sending unit and the target receiving unit, and the layout result comprises respective layout coordinates of the target sending unit and the target receiving unit; the target sending unit and the target receiving unit are driven by the same time signal; based on the respective layout coordinates of the target sending unit and the target receiving unit, evaluating the path time delay of the connection path by using a static time sequence analysis tool; and when the path time delay is smaller than a path time delay threshold value, adding an unused lookup table of at least one FPGA into the connection relation, and on the premise of not changing a layout result, determining respective layout coordinates of the at least one unused lookup table based on the layout result so as to repair retention time violation of the connection path. Therefore, the retention time violation of the connection path can be quickly repaired by adding the unused lookup table of the FPGA in the layout stage.

The invention discloses a stress simulation excitation waveform construction method and device, electronic equipment and a storage medium, and relates to the technical field of electronic design automation, and the method comprises the steps: extracting clock constraint, a time sequence path and waveform activeness data based on a static time sequence analysis tool, and building a reference time sequence library and a waveform activeness library; for an input pin of a target unit instance, the transmission time, the average signal static probability and the average signal activeness of the input pin are obtained. And generating a regular pulse waveform for the clock input pin, generating a random fragment linear waveform for the data input pin, performing rationality verification on waveform parameters, generating a stress simulation excitation waveform if the waveform parameters pass the rationality verification, and adaptively adjusting the waveform parameters if the waveform parameters do not pass the rationality verification until the stress simulation excitation waveform is generated. The method has the technical effects that stress simulation is carried out by taking the unit instance as granularity, the uniqueness of degradation parameters of the same unit instance is ensured, the generated excitation waveform better fits an actual working scene, and the aging simulation analysis accuracy is improved.

The present application belongs to the technical field of low power consumption of integrated circuit design, and discloses a multi-threshold voltage unit distribution method, comprising the following steps: step 1: data preparation: obtaining a simplified path set according to a full high threshold circuit, and obtaining unit delay, timing increase / decrease factor and static power consumption value of the full high / low threshold circuit; step 2: distributing threshold according to the path set: distributing threshold point by point in the full high threshold circuit according to path weight and unit weight until the paths in the path set all meet timing requirements; and step 3: updating the path set: applying the threshold distribution result and performing static timing analysis, if the static timing analysis result does not meet timing, updating the path set and performing the threshold distribution operation according to the path set again until the static timing analysis result meets timing. The present application effectively reduces the method running time through the simplified path set, and ensures threshold distribution accuracy and timing convergence through updating the path set.

The invention discloses a digital integrated circuit layout stage buffer insertion prediction method, electronic equipment and a storage medium, and the method comprises the steps: firstly, carrying out the physical design and static time sequence analysis of a circuit through a physical design tool and a static time sequence analysis tool, and extracting the time sequence and physical information of each unit before layout; secondly, learning the dependency relationship among the units of the circuit through a self-attention mechanism, and predicting the type and position of buffer insertion after layout in combination with multi-task learning; compared with a heuristic algorithm and a traditional machine learning algorithm, the method has the advantages that the buffer insertion type and position after layout can be efficiently predicted before layout, so that guidance is provided for the early stage of digital integrated circuit design, and the design iteration period is remarkably shortened.

The present invention discloses a method for predicting the path delay after wiring of a digital integrated circuit. First, the circuit is physically designed and statically analyzed by commercial physical design tools and static timing analysis tools, and the timing and physical information of the path before the circuit wiring are extracted as the input features of the prediction model. Then, the transformer network is used to capture the timing and physical correlation of each level of units in the path, and the residual prediction structure is used to calibrate the predicted value of the path delay after wiring, and finally the predicted value of the path delay after wiring is output. Compared with the traditional static timing analysis process, the present invention can accurately and efficiently predict the path delay after wiring before wiring, thereby effectively guiding the design and optimization of the circuit before wiring, which is of great significance for accelerating the design process of digital integrated circuits.

Embodiments of the invention are directed to a computer-implemented method of analyzing timing constraints of a component-under-design (CUD). The computer-implemented method includes performing an initial iteration of a common path pessimism removal (CPPR) analysis on circuit elements of the CUD. The circuit elements includes inputs and outputs, and the circuit elements further include a transparent circuit element. The computer-implemented method further includes storing an initial list of the inputs and the outputs for which timing was adjusted during the initial iteration; and applying a second iteration of the CPPR analysis to the initial list of the inputs and the outputs.