63 results about "Static timing analysis" patented technology

The invention provides a DFT clock architecture establishment method and device and electronic equipment, and belongs to the technical field of EDA, and the DFT clock architecture establishment method comprises the steps that a structured data file corresponding to clock planning information of a chip is acquired, the structured data file at least comprises an index field used for identifying clock uniqueness and a type field used for indicating a clock type, and the index field is used for identifying the clock uniqueness; and a parameter field for indicating clock attributes; generating a corresponding clock information object based on the values of the index field, the type field and the parameter field; based on the clock information object, a first configuration file and a second configuration file are generated, the first configuration file is used for driving a DFT tool to execute circuit insertion, and the second configuration file is used for driving a comprehensive or static timing analysis tool. The problems of configuration ambiguity, floating point error, asynchronous path omission, inconsistent OCC insertion and the like caused by dispersed and unstructured DFT clock planning information and dependence on manual transmission can be solved.

The invention provides a chip verification method and device, equipment and a storage medium, and relates to the technical field of chip verification, and the method comprises the steps: determining a static time sequence analysis result corresponding to a to-be-verified chip; according to the static time sequence analysis result, determining a plurality of target time sequence paths of which the time sequence allowances meet a preset time sequence allowance condition from the time sequence paths corresponding to the to-be-verified chip; and based on the target time sequence path, in combination with a preset verification strategy, executing a verification operation on the to-be-verified chip, the preset verification strategy is a verification strategy constructed based on low-power-consumption verification, gate-level simulation verification and interface verification. In this way, the target time sequence path can be screened out according to the static time sequence analysis result and the time sequence margin, targeted verification operation can be performed on the to-be-verified chip based on the target time sequence path, and the chip verification efficiency is improved; and chip verification is carried out in combination with multiple verification strategies, so that the chip verification effect can be further improved.

The invention provides a cross-level error tracking and repairing method and system for a stacked chip system, and the method comprises the steps: marking a register, a signal or a state machine state when an RTL code is written during chip design, and keeping a first label written during the writing of the RTL code in a gate-level netlist when a comprehensive tool generates the RTL code into the gate-level netlist; when the gate-level netlist is converted into the physical layout in the physical implementation and layout wiring process, label information of marked objects on the gate-level netlist is reserved on the physical layout when the physical layout is generated; in the integrated design process of the chip, a new second label is injected for the interconnection channel in a packaging design tool; in the simulation analysis process, when it is found that a chip simulation result is abnormal, cross-level tracking and repairing are conducted on the position of an error through static time sequence analysis and power consumption analysis. The invention also provides a system for realizing the method. According to the method, error codes can be quickly positioned and repaired.

The invention belongs to the technical field of integrated circuit post-simulation verification, and discloses an integrated circuit post-simulation system and method based on BFM and SDF inverse labeling, the system comprises a BFM packaging module used for describing a time sequence path of a port output signal and instantiating a BFM module or connecting an interface signal of a verification IP, an SDF generating assembly used for generating a BFM signal, and an SDF generating assembly used for generating an SDF signal. The static time sequence analysis database module is used for extracting delay information corresponding to a port output signal in a BFM or verification IP interface from the static time sequence analysis database and generating an SDF file according to the delay information, and the top layer verification environment module is used for reversely marking the SDF file to the BFM packaging module and running a test case. According to the method, the delay information of the BFM under each process corner is rapidly extracted by using the SDF generation component, the independent SDF file is generated and is reversely marked to the BFM packaging module, so that a real port time sequence can be simulated, multiple iterations are not needed, a large amount of manpower and time cost is saved, the delay information adding speed of the BFM is remarkably improved, and the error rate is reduced.

The invention provides a circuit energy efficiency automatic optimization method. The method comprises the following steps: firstly, modeling a circuit gate-level netlist into a directed graph; extracting a key path by using a static time sequence analysis tool, and extracting a context sensing key sub-graph containing the path and a first-order neighborhood node of the path; thirdly, feature coding is conducted on the key sub-graphs through a graph neural network, and state vectors representing the local state of the circuit are generated; the state vector is input to a reinforcement learning policy network to decide a drive capability adjustment action for a particular standard cell. And the system modifies the netlist according to the action, calls the static time sequence analysis tool again to evaluate the modified performance, power consumption and area indexes, and generates a reward signal to iteratively optimize the strategy network. By constructing the closed-loop optimization process, the problems of low manual optimization efficiency and unbalanced power consumption and area balance are solved, automatic and intelligent collaborative optimization of circuit energy efficiency is realized, and the design quality and efficiency are remarkably improved.

The invention discloses a stress simulation excitation waveform construction method and device, electronic equipment and a storage medium, and relates to the technical field of electronic design automation, and the method comprises the steps: extracting clock constraint, a time sequence path and waveform activeness data based on a static time sequence analysis tool, and building a reference time sequence library and a waveform activeness library; for an input pin of a target unit instance, the transmission time, the average signal static probability and the average signal activeness of the input pin are obtained. And generating a regular pulse waveform for the clock input pin, generating a random fragment linear waveform for the data input pin, performing rationality verification on waveform parameters, generating a stress simulation excitation waveform if the waveform parameters pass the rationality verification, and adaptively adjusting the waveform parameters if the waveform parameters do not pass the rationality verification until the stress simulation excitation waveform is generated. The method has the technical effects that stress simulation is carried out by taking the unit instance as granularity, the uniqueness of degradation parameters of the same unit instance is ensured, the generated excitation waveform better fits an actual working scene, and the aging simulation analysis accuracy is improved.

The present application belongs to the technical field of low power consumption of integrated circuit design, and discloses a multi-threshold voltage unit distribution method, comprising the following steps: step 1: data preparation: obtaining a simplified path set according to a full high threshold circuit, and obtaining unit delay, timing increase / decrease factor and static power consumption value of the full high / low threshold circuit; step 2: distributing threshold according to the path set: distributing threshold point by point in the full high threshold circuit according to path weight and unit weight until the paths in the path set all meet timing requirements; and step 3: updating the path set: applying the threshold distribution result and performing static timing analysis, if the static timing analysis result does not meet timing, updating the path set and performing the threshold distribution operation according to the path set again until the static timing analysis result meets timing. The present application effectively reduces the method running time through the simplified path set, and ensures threshold distribution accuracy and timing convergence through updating the path set.

Embodiments of the invention are directed to a computer-implemented method of analyzing timing constraints of a component-under-design (CUD). The computer-implemented method includes performing an initial iteration of a common path pessimism removal (CPPR) analysis on circuit elements of the CUD. The circuit elements includes inputs and outputs, and the circuit elements further include a transparent circuit element. The computer-implemented method further includes storing an initial list of the inputs and the outputs for which timing was adjusted during the initial iteration; and applying a second iteration of the CPPR analysis to the initial list of the inputs and the outputs.

The present technology includes performance-driven logic optimization for logic synthesis. A ground-truth dataset is generated based on technology mapping and static timing analysis of a set of gate-level netlists generated from a set of And-Inverter Graphs (AIGs). The ground-truth dataset is used to train a machine learning (ML) model to predict area and delay metrics. The trained ML model is used to predicted area and delay metrics for each AIG in another set of AIGs. A reward is calculated for each AIG in the other set of AIGs based on the predicted area and delay metrics. An AIG in the other set of AIGs having a smallest reward is selected as an optimal AIG. Technology mapping is performed on the optimal AIG to generate another gate-level netlist for use in one or more physical integrated circuit design processes.

The invention provides a static time sequence analysis method and device of a chip, electronic equipment and a storage medium, and relates to the technical field of chips. Comprising the following steps: determining punch-through paths of a clock source among sub-modules and internal time sequence information of the sub-modules according to an initial time sequence analysis result of a target chip; according to the punch-through path of the clock source among the sub-modules and the internal time sequence information of the sub-modules, simplifying and adjusting the netlist of the target chip, and retaining a time sequence association module and a time sequence association logic block of the target sub-module; and performing static time sequence analysis according to the time sequence association module and the time sequence association logic block of the target sub-module to generate a time sequence analysis result of the target sub-module. According to the method, the analysis data volume during static time sequence analysis is reduced, and the operation time of time sequence analysis is shortened. The dependence of static time sequence analysis on the chip development progress is relieved, and the overall progress of static time sequence analysis is improved.

The application provides a critical path monitoring point screening method and system combining path activation rate and similarity, comprising: obtaining timing information of all paths of a target circuit based on static timing analysis, and screening paths with timing margin less than a preset timing margin threshold to form a critical path set; based on a preset benchmark test set, performing signal flip statistics on monitoring points of each path in the critical path set, calculating the activation rate of each path, and filtering out paths with zero activation rate to obtain an effective path set; grouping paths in the effective path set according to the starting points of the paths to obtain a plurality of path groups; for each path group, calculating the similarity between paths based on the logical topology structure sequence of the paths in the group, and clustering the paths according to the similarity, and screening at least one path from each cluster; and collecting paths obtained after screening of all path groups to form a final monitoring point set.

The application provides a stacked chip system cross-level error tracking repair method and system, which comprises the following steps: during chip design, marking registers, signals or state machine states when writing RTL code; during the process of generating a gate-level netlist from the RTL code, reserving the first label written in the gate-level netlist by a synthesis tool; during the process of converting the gate-level netlist into a physical layout, reserving the label information of the marked objects on the gate-level netlist on the physical layout when the physical layout is generated; during the process of integrated design of the chip, injecting a new second label into an interconnection channel in a packaging design tool; during the process of simulation analysis, locating the error position and repairing the error through static timing analysis and power consumption analysis when an abnormal chip simulation result is found. The application also provides a system for implementing the above method. The application can quickly locate error code and repair the error.

The application relates to the field of integrated circuit design and verification technology, and discloses a fast repairing method and device for establishing time violation in static timing analysis. The method comprises the following steps: obtaining a static timing analysis report; extracting a target timing path according to the static timing analysis report; calculating a plurality of types of redundancy values of each module passed through by the target timing path; calculating a redundancy value set of a data path of the target timing path and a redundancy value subset corresponding to each module according to the redundancy values of the modules corresponding to the target timing path; determining a repairing sequence of each module according to the redundancy values of the modules corresponding to the target timing path; analyzing each module according to the redundancy value set and the redundancy value subset of each module in sequence to determine a repairing scheme of each module; and obtaining a repairing strategy of the target timing path according to the repairing schemes of the modules passed through by the target timing path. The application provides an efficient solution for an early stage of time repairing.

The invention discloses an AI-assisted time sequence report analysis method, and belongs to the technical field of integrated circuit design automation. The method comprises the following steps: acquiring a static time sequence analysis report; analyzing the report through an analysis rule base, and extracting structured information of a time sequence path; performing hierarchical grouping on the plurality of analyzed time sequence paths according to time sequence grouping, clock domains and violation types to generate time sequence statistical characteristics; and identifying a key path according to the time sequence statistical characteristics, and outputting a structured analysis result and an optimization suggestion. Through automatic analysis and intelligent analysis, the time sequence debugging efficiency is remarkably improved, dependence on experience of engineers is reduced, and the method is suitable for time sequence convergence scenes of large-scale integrated circuit design.

The invention discloses a digital circuit aging simulation method based on a critical path. The method comprises the following steps: extracting the critical path of a digital circuit by using a static time sequence analysis tool; screening potential critical paths by utilizing an aging worst-case analysis method; obtaining a key path and a netlist file excited by the key path; obtaining time delay, not including aging, of the key path through simulation before aging; changing the excitation of the key path and generating dynamic simulation excitation; performing key path dynamic aging simulation in combination with an existing aging model to obtain electrical parameter degradation amounts of all devices; converting the device degradation amount into an aged model netlist; and in combination with the aged model netlist, performing simulation after aging of the key path to obtain delay after aging of the path. According to the method, SPICE-level aging simulation is carried out on the critical path of the digital circuit to predict the actual performance degradation condition of the circuit, so that more accurate data support is provided for circuit optimization design.

The invention relates to the technical field of digital circuits, in particular to a method, device and equipment for reducing peak current, a medium and a digital circuit, and the method comprises the steps: obtaining the peak moment of the maximum instantaneous peak current of a target circuit; performing static time sequence analysis on the target circuit, acquiring arrival time and required time of each path in the target circuit, and taking a difference value obtained by subtracting the arrival time from the required time as a time sequence margin; determining the path of which the time sequence margin is greater than 0 as a non-critical path; acquiring a non-critical path where a target logic gate flipped at the peak moment is located as an insertion path; the time delay units are inserted into the insertion paths, so that the target logic gates of the insertion paths are staggered in the overturning time, the total time delay D of the time delay units inserted into the insertion paths meets the condition that D is smaller than or equal to Si-delta, Si is the time sequence margin of the insertion paths, and delta is the preset safety time sequence margin. The technical scheme can reduce the peak current of the digital circuit, and is mainly used for digital circuit design.

The application discloses a high-density integrated circuit layout and wiring method, which realizes high-density layout of the integrated circuit by global and local layout control in the layout and wiring stage. An embodiment of the application discloses local layout control in the ECO stage of static timing analysis to complete convergence of all timing violations. In addition, another embodiment discloses a system for high-density integrated circuit layout and wiring, which adopts a global layout control unit and a local layout control unit in the layout stage to realize high-density layout under the premise of timing convergence, and adopts a local layout control unit and a local wiring control unit in the wiring stage to realize layout optimization.

The invention provides a time sequence violation repairing method and device, electronic equipment and a storage medium, and is applied to the technical field of computers, and the method comprises the steps: after obtaining a violation path set of an integrated circuit under a plurality of process corners, selecting one process corner from the plurality of process corners as a reference process corner, and taking the other process corners as non-reference process corners, and taking the violation path set of the reference process corner and the violation path set of each non-reference process corner as a target violation path set, performing static time sequence analysis on time sequence violation paths in the target violation path set according to the reference process corner, and performing time sequence violation repair according to an obtained target time sequence analysis report. According to the method, on the basis of the violation path set of the reference process corner and the unique time sequence violation paths in the violation path set of other non-reference process corners, the obtained target violation path set does not have repeated time sequence violation paths, so that a large amount of repeated work can be avoided, the data volume of time sequence violation repair is effectively reduced, and the time sequence violation efficiency is improved.

The invention provides a chip simulation method and device. The chip simulation method comprises the steps of obtaining an initial delay data set in static time sequence analysis of a target chip and a violation time sequence unit with a time sequence violation in the target chip; determining a target value according to the establishment time margin and the retention time margin corresponding to the violation time sequence unit; the delay value of a target unit in the initial delay data set is modified based on the target value, a target delay data set is obtained, and the target unit is a standard unit in a data transmission path or a clock path corresponding to the violation time sequence unit; and simulating the target chip based on the target delay data set. By means of the chip simulation method, the technical problem that in the related technology, due to the fact that the adjustment period of layout wiring is long, the starting time of chip post simulation is greatly delayed is solved.

The invention provides a chip layout quality inspection method and device in circuit design, and the method comprises the steps: receiving chip design information and quality inspection options inputted by a user, the chip design information comprises the shapes of a plurality of blocks in a chip, the positions of the blocks, the connection relation among the blocks, the shapes of a plurality of units and the connection relation among the units, and each block comprises at least one unit. The quality inspection option comprises any one or more of data flow inspection, unit layout evaluation, congestion estimation and static time sequence analysis; according to the chip design information, the layout result of the chip is determined, and the layout result comprises the positions of the units; and obtaining a layout quality inspection result of the chip according to the layout result and an inspection rule corresponding to the quality inspection option. According to the method provided by the invention, the chip design efficiency can be improved.

The invention discloses a chip circuit detailed layout optimization method based on dynamic programming, and the method comprises the steps: carrying out the static time sequence analysis of an initial transistor position, recognizing a negative slack region on a critical path, and carrying out the heuristic optimization with the region as a target in a detailed layout process of time sequence driving of chip circuit wiring; defining a self-adaptive search window: dynamically adjusting the movable range of the unit according to the influence of the unit on a path time sequence, so that optimization is focused on a key region, and meaningless disturbance to a non-key region is avoided; and fine-grained unit movement based on dynamic programming: enumerating all legal unit arrangements in a local window, and accurately solving an optimal layout scheme in combination with time sequence cost and legality constraints. According to the method, sufficient generalization ability under different target densities and layout resources can be ensured, and interaction among different units generated in a global layout stage in a local range is considered.

The present disclosure provides a DFT clock architecture establishment method, device and electronic equipment, belonging to the technical field of EDA. The DFT clock architecture establishment method comprises: obtaining a structured data file corresponding to clock planning information of a chip, the structured data file at least comprising an index field for identifying clock uniqueness, a type field for indicating clock type, and a parameter field for indicating clock attribute; generating a corresponding clock information object based on the values of the index field, the type field and the parameter field; generating a first configuration file and a second configuration file based on the clock information object, the first configuration file being used to drive a DFT tool to perform circuit insertion, and the second configuration file being used to drive a synthesis or static timing analysis tool. The problems of configuration ambiguity, floating point error, asynchronous path omission and OCC insertion inconsistency caused by the dispersion, unstructured and manual transmission of DFT clock planning information can be solved.

The present invention proposes an artificial intelligence-based incremental static timing analysis method suitable for analyzing circuit delays during the ECO phase of confirmation in digital circuit design. The method extracts circuit device characteristic data related to the timing data based on circuit timing data from the original design confirmation phase without ECO. A delay prediction model is constructed based on a neural network and trained using the circuit device characteristic data to obtain model parameters. The circuit device characteristic data of the incremental design after ECO is extracted and input into the trained delay prediction model to obtain circuit delay data of the incremental design structure, as well as corresponding delay data and gain data. The delay data and gain data are then fed back to the placer and router. This method ensures static timing prediction accuracy while solving the problem of incremental design results failing to meet timing closure requirements.

An electronic device and a clock jitter analysis method are provided. The electronic device includes a storage device and a processing device. The processing device is configured to: read timing simulation information and voltage drop information of a plurality of clock paths from the storage device; obtain a maximum voltage drop and a minimum voltage drop of each clock path based on the voltage drop information; perform a first static timing analysis (STA) with the maximum voltage drop based on the timing simulation information, to obtain a first timing report; perform a second STA with the minimum voltage drop based on the timing simulation information, to obtain a second timing report; calculate time information corresponding to each clock path based on the first timing report and the second timing report; and select largest time information of the plurality of pieces of time information as a clock jitter.

The invention provides a standard unit time sequence data processing method and device, electronic equipment and a storage medium, and is applied to the technical field of computers.The method comprises the steps that after at least one standard unit and a plurality of process corners are obtained, unit information of all the standard units is extracted, and any standard unit serves as a target standard unit; configuring operation conditions according to unit information of the target standard unit, determining a target time sequence path of the target standard unit, and finally performing static time sequence analysis on the target time sequence path under each process corner according to the operation conditions of the target standard unit to obtain delay data of the target standard unit under different preset working voltages. Compared with the prior art, the method has the advantages that the delay data of each standard unit under different preset working voltages can be obtained before the physical design of the integrated circuit is carried out, and accurate and reliable reference bases meeting project design requirements are provided for the physical design as soon as possible.

The embodiment of the invention provides an integrated circuit path optimization method based on multi-dimensional feature judgment, and the method comprises the steps: determining the signal transmission features of an integrated circuit according to the layout and wiring data of the integrated circuit and the static time sequence analysis data of the integrated circuit, determining the scores of a plurality of signal transmission paths according to the signal transmission features, and determining the signal transmission path with the corresponding score higher than a first threshold value as a replicable path, determining the signal transmission path with the corresponding score lower than a second threshold value as a to-be-optimized path, and optimizing the to-be-optimized path according to the replicable path. According to the scheme, the score of the signal transmission path is calculated through the signal transmission characteristics, the signal transmission path is evaluated from multiple dimensions, and the poor optimization effect caused by single index evaluation is avoided. The path needing to be optimized is determined through the score of the signal transmission path, targeted processing is achieved, the whole integrated circuit does not need to be optimized, and resource waste caused by excessive copying is avoided.

A method of performing static timing analysis for a circuit design includes, in part, identifying a multitude of logic blocks of the circuit design matching a design pattern; determining values of a multitude of electrical properties associated with a first logic block representative of each of the plurality of logic blocks; and determining, during the static timing analysis, a delay associated with each of the multitude of logic blocks using the values of the electrical properties.

The embodiment of the invention discloses a timing constraint generation method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and can effectively improve the timing convergence speed of a circuit. The method comprises the following steps: acquiring simulation waveform data of a simulation signal at a target node of a target circuit module in each working scene; according to the simulation waveform data, determining whether the overturning frequency of the simulation signal at each target node in each working scene is smaller than a preset frequency value; and in response to the situation that the overturning frequency of the simulation signal at any target node in each working scene is smaller than the preset frequency value, generating a target time sequence constraint for the target node so as to relax time sequence check on the target node according to the target time sequence constraint in static time sequence analysis. The method is suitable for chip design.

The invention provides a functional unit creating method, related equipment, a layout design method and a storage medium, and is applied to the technical field of computers.The method comprises the steps that firstly, an integrated circuit is divided into a plurality of logic areas based on a static time sequence analysis result, a target logic area is determined, and then an initial circuit architecture in the target logic area is extracted; according to the method, the initial circuit architecture is subjected to architecture recombination to obtain a target circuit architecture with the same function as the initial circuit architecture, and finally, physical design is performed based on the target circuit architecture to obtain a functional unit corresponding to a target logic area. The logic series of the target circuit architecture is smaller than that of the initial circuit architecture, so that the use amount of standard units in the target circuit architecture can be reduced, the time sequence performance of a logic region is improved, and the time sequence characteristic performance of a low-speed logic region is improved; the problem that the overall performance of an integrated circuit is limited by the time sequence performance of a low-speed logic region in related technologies is solved.