47 results about "Static timing analysis" patented technology

The invention provides a DFT clock architecture establishment method and device and electronic equipment, and belongs to the technical field of EDA, and the DFT clock architecture establishment method comprises the steps that a structured data file corresponding to clock planning information of a chip is acquired, the structured data file at least comprises an index field used for identifying clock uniqueness and a type field used for indicating a clock type, and the index field is used for identifying the clock uniqueness; and a parameter field for indicating clock attributes; generating a corresponding clock information object based on the values of the index field, the type field and the parameter field; based on the clock information object, a first configuration file and a second configuration file are generated, the first configuration file is used for driving a DFT tool to execute circuit insertion, and the second configuration file is used for driving a comprehensive or static timing analysis tool. The problems of configuration ambiguity, floating point error, asynchronous path omission, inconsistent OCC insertion and the like caused by dispersed and unstructured DFT clock planning information and dependence on manual transmission can be solved.

The invention provides a cross-level error tracking and repairing method and system for a stacked chip system, and the method comprises the steps: marking a register, a signal or a state machine state when an RTL code is written during chip design, and keeping a first label written during the writing of the RTL code in a gate-level netlist when a comprehensive tool generates the RTL code into the gate-level netlist; when the gate-level netlist is converted into the physical layout in the physical implementation and layout wiring process, label information of marked objects on the gate-level netlist is reserved on the physical layout when the physical layout is generated; in the integrated design process of the chip, a new second label is injected for the interconnection channel in a packaging design tool; in the simulation analysis process, when it is found that a chip simulation result is abnormal, cross-level tracking and repairing are conducted on the position of an error through static time sequence analysis and power consumption analysis. The invention also provides a system for realizing the method. According to the method, error codes can be quickly positioned and repaired.

The invention belongs to the technical field of integrated circuit post-simulation verification, and discloses an integrated circuit post-simulation system and method based on BFM and SDF inverse labeling, the system comprises a BFM packaging module used for describing a time sequence path of a port output signal and instantiating a BFM module or connecting an interface signal of a verification IP, an SDF generating assembly used for generating a BFM signal, and an SDF generating assembly used for generating an SDF signal. The static time sequence analysis database module is used for extracting delay information corresponding to a port output signal in a BFM or verification IP interface from the static time sequence analysis database and generating an SDF file according to the delay information, and the top layer verification environment module is used for reversely marking the SDF file to the BFM packaging module and running a test case. According to the method, the delay information of the BFM under each process corner is rapidly extracted by using the SDF generation component, the independent SDF file is generated and is reversely marked to the BFM packaging module, so that a real port time sequence can be simulated, multiple iterations are not needed, a large amount of manpower and time cost is saved, the delay information adding speed of the BFM is remarkably improved, and the error rate is reduced.

The invention provides a circuit energy efficiency automatic optimization method. The method comprises the following steps: firstly, modeling a circuit gate-level netlist into a directed graph; extracting a key path by using a static time sequence analysis tool, and extracting a context sensing key sub-graph containing the path and a first-order neighborhood node of the path; thirdly, feature coding is conducted on the key sub-graphs through a graph neural network, and state vectors representing the local state of the circuit are generated; the state vector is input to a reinforcement learning policy network to decide a drive capability adjustment action for a particular standard cell. And the system modifies the netlist according to the action, calls the static time sequence analysis tool again to evaluate the modified performance, power consumption and area indexes, and generates a reward signal to iteratively optimize the strategy network. By constructing the closed-loop optimization process, the problems of low manual optimization efficiency and unbalanced power consumption and area balance are solved, automatic and intelligent collaborative optimization of circuit energy efficiency is realized, and the design quality and efficiency are remarkably improved.

The invention discloses a stress simulation excitation waveform construction method and device, electronic equipment and a storage medium, and relates to the technical field of electronic design automation, and the method comprises the steps: extracting clock constraint, a time sequence path and waveform activeness data based on a static time sequence analysis tool, and building a reference time sequence library and a waveform activeness library; for an input pin of a target unit instance, the transmission time, the average signal static probability and the average signal activeness of the input pin are obtained. And generating a regular pulse waveform for the clock input pin, generating a random fragment linear waveform for the data input pin, performing rationality verification on waveform parameters, generating a stress simulation excitation waveform if the waveform parameters pass the rationality verification, and adaptively adjusting the waveform parameters if the waveform parameters do not pass the rationality verification until the stress simulation excitation waveform is generated. The method has the technical effects that stress simulation is carried out by taking the unit instance as granularity, the uniqueness of degradation parameters of the same unit instance is ensured, the generated excitation waveform better fits an actual working scene, and the aging simulation analysis accuracy is improved.

The present application belongs to the technical field of low power consumption of integrated circuit design, and discloses a multi-threshold voltage unit distribution method, comprising the following steps: step 1: data preparation: obtaining a simplified path set according to a full high threshold circuit, and obtaining unit delay, timing increase / decrease factor and static power consumption value of the full high / low threshold circuit; step 2: distributing threshold according to the path set: distributing threshold point by point in the full high threshold circuit according to path weight and unit weight until the paths in the path set all meet timing requirements; and step 3: updating the path set: applying the threshold distribution result and performing static timing analysis, if the static timing analysis result does not meet timing, updating the path set and performing the threshold distribution operation according to the path set again until the static timing analysis result meets timing. The present application effectively reduces the method running time through the simplified path set, and ensures threshold distribution accuracy and timing convergence through updating the path set.

Embodiments of the invention are directed to a computer-implemented method of analyzing timing constraints of a component-under-design (CUD). The computer-implemented method includes performing an initial iteration of a common path pessimism removal (CPPR) analysis on circuit elements of the CUD. The circuit elements includes inputs and outputs, and the circuit elements further include a transparent circuit element. The computer-implemented method further includes storing an initial list of the inputs and the outputs for which timing was adjusted during the initial iteration; and applying a second iteration of the CPPR analysis to the initial list of the inputs and the outputs.

The present technology includes performance-driven logic optimization for logic synthesis. A ground-truth dataset is generated based on technology mapping and static timing analysis of a set of gate-level netlists generated from a set of And-Inverter Graphs (AIGs). The ground-truth dataset is used to train a machine learning (ML) model to predict area and delay metrics. The trained ML model is used to predicted area and delay metrics for each AIG in another set of AIGs. A reward is calculated for each AIG in the other set of AIGs based on the predicted area and delay metrics. An AIG in the other set of AIGs having a smallest reward is selected as an optimal AIG. Technology mapping is performed on the optimal AIG to generate another gate-level netlist for use in one or more physical integrated circuit design processes.

The invention provides a static time sequence analysis method and device of a chip, electronic equipment and a storage medium, and relates to the technical field of chips. Comprising the following steps: determining punch-through paths of a clock source among sub-modules and internal time sequence information of the sub-modules according to an initial time sequence analysis result of a target chip; according to the punch-through path of the clock source among the sub-modules and the internal time sequence information of the sub-modules, simplifying and adjusting the netlist of the target chip, and retaining a time sequence association module and a time sequence association logic block of the target sub-module; and performing static time sequence analysis according to the time sequence association module and the time sequence association logic block of the target sub-module to generate a time sequence analysis result of the target sub-module. According to the method, the analysis data volume during static time sequence analysis is reduced, and the operation time of time sequence analysis is shortened. The dependence of static time sequence analysis on the chip development progress is relieved, and the overall progress of static time sequence analysis is improved.

The application provides a critical path monitoring point screening method and system combining path activation rate and similarity, comprising: obtaining timing information of all paths of a target circuit based on static timing analysis, and screening paths with timing margin less than a preset timing margin threshold to form a critical path set; based on a preset benchmark test set, performing signal flip statistics on monitoring points of each path in the critical path set, calculating the activation rate of each path, and filtering out paths with zero activation rate to obtain an effective path set; grouping paths in the effective path set according to the starting points of the paths to obtain a plurality of path groups; for each path group, calculating the similarity between paths based on the logical topology structure sequence of the paths in the group, and clustering the paths according to the similarity, and screening at least one path from each cluster; and collecting paths obtained after screening of all path groups to form a final monitoring point set.

The application provides a stacked chip system cross-level error tracking repair method and system, which comprises the following steps: during chip design, marking registers, signals or state machine states when writing RTL code; during the process of generating a gate-level netlist from the RTL code, reserving the first label written in the gate-level netlist by a synthesis tool; during the process of converting the gate-level netlist into a physical layout, reserving the label information of the marked objects on the gate-level netlist on the physical layout when the physical layout is generated; during the process of integrated design of the chip, injecting a new second label into an interconnection channel in a packaging design tool; during the process of simulation analysis, locating the error position and repairing the error through static timing analysis and power consumption analysis when an abnormal chip simulation result is found. The application also provides a system for implementing the above method. The application can quickly locate error code and repair the error.

The application relates to the field of integrated circuit design and verification technology, and discloses a fast repairing method and device for establishing time violation in static timing analysis. The method comprises the following steps: obtaining a static timing analysis report; extracting a target timing path according to the static timing analysis report; calculating a plurality of types of redundancy values of each module passed through by the target timing path; calculating a redundancy value set of a data path of the target timing path and a redundancy value subset corresponding to each module according to the redundancy values of the modules corresponding to the target timing path; determining a repairing sequence of each module according to the redundancy values of the modules corresponding to the target timing path; analyzing each module according to the redundancy value set and the redundancy value subset of each module in sequence to determine a repairing scheme of each module; and obtaining a repairing strategy of the target timing path according to the repairing schemes of the modules passed through by the target timing path. The application provides an efficient solution for an early stage of time repairing.

The invention discloses an AI-assisted time sequence report analysis method, and belongs to the technical field of integrated circuit design automation. The method comprises the following steps: acquiring a static time sequence analysis report; analyzing the report through an analysis rule base, and extracting structured information of a time sequence path; performing hierarchical grouping on the plurality of analyzed time sequence paths according to time sequence grouping, clock domains and violation types to generate time sequence statistical characteristics; and identifying a key path according to the time sequence statistical characteristics, and outputting a structured analysis result and an optimization suggestion. Through automatic analysis and intelligent analysis, the time sequence debugging efficiency is remarkably improved, dependence on experience of engineers is reduced, and the method is suitable for time sequence convergence scenes of large-scale integrated circuit design.

The invention discloses a digital circuit aging simulation method based on a critical path. The method comprises the following steps: extracting the critical path of a digital circuit by using a static time sequence analysis tool; screening potential critical paths by utilizing an aging worst-case analysis method; obtaining a key path and a netlist file excited by the key path; obtaining time delay, not including aging, of the key path through simulation before aging; changing the excitation of the key path and generating dynamic simulation excitation; performing key path dynamic aging simulation in combination with an existing aging model to obtain electrical parameter degradation amounts of all devices; converting the device degradation amount into an aged model netlist; and in combination with the aged model netlist, performing simulation after aging of the key path to obtain delay after aging of the path. According to the method, SPICE-level aging simulation is carried out on the critical path of the digital circuit to predict the actual performance degradation condition of the circuit, so that more accurate data support is provided for circuit optimization design.

The application discloses a high-density integrated circuit layout and wiring method, which realizes high-density layout of the integrated circuit by global and local layout control in the layout and wiring stage. An embodiment of the application discloses local layout control in the ECO stage of static timing analysis to complete convergence of all timing violations. In addition, another embodiment discloses a system for high-density integrated circuit layout and wiring, which adopts a global layout control unit and a local layout control unit in the layout stage to realize high-density layout under the premise of timing convergence, and adopts a local layout control unit and a local wiring control unit in the wiring stage to realize layout optimization.

The invention provides a time sequence violation repairing method and device, electronic equipment and a storage medium, and is applied to the technical field of computers, and the method comprises the steps: after obtaining a violation path set of an integrated circuit under a plurality of process corners, selecting one process corner from the plurality of process corners as a reference process corner, and taking the other process corners as non-reference process corners, and taking the violation path set of the reference process corner and the violation path set of each non-reference process corner as a target violation path set, performing static time sequence analysis on time sequence violation paths in the target violation path set according to the reference process corner, and performing time sequence violation repair according to an obtained target time sequence analysis report. According to the method, on the basis of the violation path set of the reference process corner and the unique time sequence violation paths in the violation path set of other non-reference process corners, the obtained target violation path set does not have repeated time sequence violation paths, so that a large amount of repeated work can be avoided, the data volume of time sequence violation repair is effectively reduced, and the time sequence violation efficiency is improved.

The present disclosure provides a DFT clock architecture establishment method, device and electronic equipment, belonging to the technical field of EDA. The DFT clock architecture establishment method comprises: obtaining a structured data file corresponding to clock planning information of a chip, the structured data file at least comprising an index field for identifying clock uniqueness, a type field for indicating clock type, and a parameter field for indicating clock attribute; generating a corresponding clock information object based on the values of the index field, the type field and the parameter field; generating a first configuration file and a second configuration file based on the clock information object, the first configuration file being used to drive a DFT tool to perform circuit insertion, and the second configuration file being used to drive a synthesis or static timing analysis tool. The problems of configuration ambiguity, floating point error, asynchronous path omission and OCC insertion inconsistency caused by the dispersion, unstructured and manual transmission of DFT clock planning information can be solved.

The invention provides a standard unit time sequence data processing method and device, electronic equipment and a storage medium, and is applied to the technical field of computers.The method comprises the steps that after at least one standard unit and a plurality of process corners are obtained, unit information of all the standard units is extracted, and any standard unit serves as a target standard unit; configuring operation conditions according to unit information of the target standard unit, determining a target time sequence path of the target standard unit, and finally performing static time sequence analysis on the target time sequence path under each process corner according to the operation conditions of the target standard unit to obtain delay data of the target standard unit under different preset working voltages. Compared with the prior art, the method has the advantages that the delay data of each standard unit under different preset working voltages can be obtained before the physical design of the integrated circuit is carried out, and accurate and reliable reference bases meeting project design requirements are provided for the physical design as soon as possible.

A method of performing static timing analysis for a circuit design includes, in part, identifying a multitude of logic blocks of the circuit design matching a design pattern; determining values of a multitude of electrical properties associated with a first logic block representative of each of the plurality of logic blocks; and determining, during the static timing analysis, a delay associated with each of the multitude of logic blocks using the values of the electrical properties.

The embodiment of the invention discloses a timing constraint generation method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and can effectively improve the timing convergence speed of a circuit. The method comprises the following steps: acquiring simulation waveform data of a simulation signal at a target node of a target circuit module in each working scene; according to the simulation waveform data, determining whether the overturning frequency of the simulation signal at each target node in each working scene is smaller than a preset frequency value; and in response to the situation that the overturning frequency of the simulation signal at any target node in each working scene is smaller than the preset frequency value, generating a target time sequence constraint for the target node so as to relax time sequence check on the target node according to the target time sequence constraint in static time sequence analysis. The method is suitable for chip design.

The invention provides a functional unit creating method, related equipment, a layout design method and a storage medium, and is applied to the technical field of computers.The method comprises the steps that firstly, an integrated circuit is divided into a plurality of logic areas based on a static time sequence analysis result, a target logic area is determined, and then an initial circuit architecture in the target logic area is extracted; according to the method, the initial circuit architecture is subjected to architecture recombination to obtain a target circuit architecture with the same function as the initial circuit architecture, and finally, physical design is performed based on the target circuit architecture to obtain a functional unit corresponding to a target logic area. The logic series of the target circuit architecture is smaller than that of the initial circuit architecture, so that the use amount of standard units in the target circuit architecture can be reduced, the time sequence performance of a logic region is improved, and the time sequence characteristic performance of a low-speed logic region is improved; the problem that the overall performance of an integrated circuit is limited by the time sequence performance of a low-speed logic region in related technologies is solved.

This invention discloses a static timing analysis method and a static timing analysis system. The static timing analysis method includes: obtaining a standard component library file describing multiple standard components; performing circuit structure analysis on the standard component library file to identify a target sequential component from the standard components, the target sequential component including logic gates, selection circuits, and register circuits; executing a logic test program to identify pin combinations with non-mutually controllable relationships, and treating the timing constraints related to these pin combinations in the standard component library file as redundant timing constraints to remove them from the standard component library file, thereby generating an optimized standard component library file; and performing static timing analysis on the target circuit design based on the optimized standard component library file.

Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and / or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).

The application discloses a process angle prediction method and system in static timing analysis based on ensemble learning, which combines multilayer perceptron and graph neural network for process angle prediction. Firstly, the MLP model is used for preliminary prediction, and then the prediction result of the MLP is input into the GNN model to optimize the prediction result in the form of graph structure data. The application also uses a generative adversarial network to generate synthetic data, thereby expanding the training set and improving the prediction ability of the model. The method of the application can significantly improve the prediction accuracy and is more efficient in running speed than the traditional method. The method not only reduces the calculation overhead of the traditional STA method, but also has good adaptability and high efficiency, and is particularly suitable for process angle prediction tasks of large-scale circuits. The system architecture of the application includes a data acquisition module, an MLP module, a GNN module and a GAN data generation module, and can realize efficient and accurate process angle prediction in industrial applications.

The present application relates to the technical field of microcircuit analysis, and discloses a classification method and equipment for static timing analysis report. The present application comprises the following steps: determining the type of the static timing analysis report of the target timing path; if the static timing analysis report is the setup time type, dividing the data path of the target timing path into intra-module paths and cross-module paths; dividing the violations existing in the intra-module paths to the corresponding modules to obtain a first violation division result; determining a plurality of target modules corresponding to the cross-module paths with violations; calculating the violation value contribution degree of each target module; dividing the violations existing in the cross-module paths to the corresponding target modules according to the violation value contribution degree of each target module to obtain a second violation division result; and determining the violations of the target timing path belonging to each module according to the first violation division result and the second violation division result. The present application can efficiently process the static timing analysis report, and improve the efficiency and accuracy.

The present application belongs to the field of electronic design automation and static timing analysis, and particularly relates to a parallel optimization method for FPGA static timing analysis, aiming at solving the problems of low calculation efficiency and long compilation time in the prior art. The method comprises: memory layout optimization of a timing graph and timing constraints according to a constructed FPGA-oriented STA data structure; task decomposition, and parallel execution of the calculation tasks of nodes and edges of each level by multiple parallel kernels, and sequential execution of different levels by a single CPU thread; during execution, the timing graph is traversed to mark nodes and edges to be updated; through bidirectional traversal calculation, the effective arrival time of a node and the effective requirement time of the node are obtained, the critical path in FPGA timing static analysis is determined, and a parallel optimization report for FPGA static timing analysis is generated. The present application improves the calculation efficiency in static timing analysis and shortens the compilation time.

The invention discloses an operator model processing method and device, a medium and a product, and the method comprises the steps: extracting a netlist structure of each operator model in a netlist file of a target circuit, and recognizing a complex operator model in each operator model according to the netlist structure of each operator model; performing logic relation simplification processing on each complex operator model to obtain time sequence arc information between each input bit and each output bit of each complex operator model; according to the time sequence arc information between the input bits and the output bits of the complex operator models, simplified operator models corresponding to the complex operator models respectively are generated; and storing the identity identification information of each complex operator model and the simplified operator model of each complex operator model in an optimization model library in an associated manner, so as to carry out static time sequence analysis processing on the target circuit, the technical scheme of the embodiment of the invention can effectively improve the efficiency and precision of static time sequence analysis, and at the same time, significantly reduce the consumption of computing resources.

The invention discloses a hypergraph optimization method and device, a medium and a product, and the method comprises the steps: obtaining a to-be-tested source code and a time sequence constraint file, converting the source code into a netlist file, carrying out the modeling to obtain a netlist model, and carrying out the static time sequence analysis to obtain a time sequence model; according to each time sequence parameter in the model, setting a time sequence weight value for each node and hyperedge in the netlist model; traversing the connection relationship of the net in the netlist file, counting the number of bottom unit loads driven by each net, obtaining a fan-out value of a hyperedge corresponding to the net in the netlist model, and setting a fan-out weight value for the hyperedge; classifying and merging nodes in the netlist model according to a preset resource constraint and a time sequence weight value to obtain a coarsened hypergraph model; according to the preset resource proportion, the fan-out weight value of the hyperedges and the hyperedges number of the nodes, the segmentation boundary is set, the optimized hypergraph is obtained, the reliability of hypergraph optimization is improved, and time sequence convergence of design after segmentation and back-end circuit layout and wiring are facilitated.

The invention discloses a chip subsystem gate-level simulation signal time delay debugging algorithm, which comprises the following steps of: loading a subsystem physical implementation project through a static time sequence analysis tool, reporting four key time sequence paths, and extracting key parameters from the four key time sequence paths; calculating a time delay adjustment interval based on the key parameters; judging whether the time delay adjustment interval exists or not, and if yes, adjusting the time delay difference between the VIP clock and the DUT clock to enable the time delay difference to fall in the time delay adjustment interval so as to complete gate-level simulation time sequence convergence; and if not, indicating that the IO time sequence needs to be tightened physically. According to the method, the simulation passing rate can be greatly improved, the time cost is saved, the sdf gate level simulation failure caused by the fact that the IO time sequence of a factor system is not met is avoided, the obtained time delay adjustment interval can be effective for all signals in the same direction in the same clock domain at the same time, and it is avoided that different delays are added to each signal independently.

A method includes: receiving a circuit design including circuit stages; deriving initial logic conditions for nets in a fanout cone from an input port in accordance with a primordial event; initializing a priority queue of logic transition events with the primordial event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all others in the priority queue and representing a logic transition at an input pin of a current circuit stage; simulating an arc of the circuit design from the input pin of the current circuit stage to an input pin of a fanout circuit stage to generate a propagated event; computing a propagated event timestamp based on: the trigger event timestamp; and a delay associated with the arc; enqueuing the propagated event on the priority queue; and generating a static analysis report based on the propagated event timestamp.