139results about How to "Small design area" patented technology

The invention relates to an enhanced MASK code method for resisting DES (data encryption standard) power consumption attack, comprising the steps as follows: step 1, realizing two rounds of DES (data encryption standard) calculations with a pipeline operation mode, realizing a calculating circuit by means of a first calculating circuit and a second calculating circuit which are mutually independent and isolated; step 2, realizing the DES (data encryption standard) calculation processes from the third round to the fourteenth round by means of a random positioning logical operation mode; step 3, realizing the last two rounds of DES (data encryption standard) calculations by means of a pipeline operation mode, and realizing the calculating circuit by means of a third calculating circuit and a fourth calculating circuit which are mutually independent and isolated, wherein each round of the DES (data encryption standard) calculations in step 1 to 3 is calculated with a MASK code method. The method provided by the invention not only reduces the design area of the chip, but also completely solves the problem in the prior art in which the two adjacent rounds of the MASK code solutions have a Hamming distance leakage, and keeps the sensitive information between wheels from leakage, and simultaneously keeps the Hamming distance and other sensitive information between two adjacentwheels from leakage, and effectively resists the power consumption attack.

The invention provides a NAND flash controller circuit of a multi-channel shared data cache region. The NAND flash controller circuit comprises a main controller, a shared data cache region unit and a NAND flash interface control logic unit, wherein the shared data cache region unit consists of a data cache region, a data cache region address list and a data cache region address first-in first-out (FIFO) unit which are realized by adopting a flip-flop, a latch, a static random access memory (SRAM) or an off-chip synchronous dynamic random access memory (SDRAM) and a double data rate synchronous dynamic random access memory (DDRSDRAM). By adoption of the shared data cache region, the capacity of the data cache region of a multi-channel NAND flash controller is reduced, the design area of the controller chip is reduced effectively, the data transmission time is guaranteed, and the application requirement is met.

The invention relates to a high-contrast COB packaged small-pitch LED display panel, comprising a driving circuit board, an encapsulating adhesive layer, a pixel unit and a driving IC. Each pixel unitcomprises a red, green and blue LED light emitting chip, and at least one LED light emitting chip of the primary color adopts a flip-chip LED light emitting chip. The encapsulant layer is made of epoxy resin, and its thickness is 0.4-0.65 mm, and wherein the melanin is mixed with 0.1 % to 0.6% of the total weight of the epoxy resin; At least one primary color LED light emit chip of that inventionadopts a flip-chip LED light emit chip, which not only reduces the design area of the bonding pad, reduces the bonding wire area of the light emit chip, but also improves the brightness of the display screen; At that same time, the contrast of the display screen can be effectively improve due to the addition of melanin in the encapsulation adhesive layer.

The invention discloses a time sequence repairing method, which is used for solving the problem of increase in chip design area caused by repair of a time sequence circuit during integrated circuit application by intervening with a clock channel and transferring a part of design problems of a data channel onto the clock channel. The method comprises the following steps of: analyzing the characteristic of a time sequence violating example; analyzing routes in which violating examples exists; when all routes of which start points of the violating examples serve as start points are provided with sufficient build-up time margins and all routes of which start points of the violating examples serve as end points are provided with sufficient build-up time margins, repairing and keeping a time sequence by increasing the clock delays of the start points of the routes; and when all routes of which end points of the violating examples serve as end points are provided with sufficient build-up time margins and all routes of which end points of violating examples serve as start points are provided with sufficient build-up time margins, repairing and keeping a time sequence by decreasing the clock delays of the end points of the routes. In the method disclosed by the invention, different clock delay design modes are selected, so that the circuit complexity of the integrated circuit chip design can be lowered effectively, and the chip design area is reduced.

The invention relates to an elastic buffer device which comprises a plurality of FIFO (first in first out) units used for writing in and reading the data of the data packet of corresponding data channels; a plurality of FIFO unit controllers used for controlling the reading or writing of pointers to write the data in or read the data from the corresponding FIFO units, calculating the distance of the reading and writing pointers according to the detected position of the reading and writing pointers of the corresponding data channels, adjusting the position of the reading pointer according to the preset distance scope of the reading and writing pointers, counting the data head identifiers of the received data packet of the corresponding data channels, notifying the counting result to a multi-channel deflection controller, and adjusting the position of the reading pointer of the FIFO unit of the data channel according to the feedback of the multi-channel deflection controller; the multi-channel deflection controller used for carrying out comprehensive analysis according to the counting result of data head identifiers sent by each FIFO unit controller, and transmitting feedback signals to each FIFO unit controller, thus causing the area of PCI Express to be comparatively small.

The invention discloses a DDR-based reading data synchronization method and system. The method uses a frequency divider to input a data strobe signal half-inpu-dqs-n as a DDR interface DQS signal, a sampling clock internal-clk serves as a sampling clock in a DDR controller, a transition clock is set up as a synchronous clock between the DDR interface DQS signal and the sampling clock in the DDR controller, and the synchronous clock achieves the synchronization of the sampling clock in the DDR controller and an input color outside the DDR and achieves asynchronous transmission of DDR interfaceDQS domain data and domain data of the sampling color in the DDR controller. According to the method and the system, the building time and the retention time of a DQS domain and a sampling color domain in the DDR controller can be satisfied to the maximum extent, the synchronization problem of the DDR reading data is solved with a very small delay, and the method and the system no longer rely on the FIFO technology.

The invention discloses an LDMOS which comprises a P-type substrate, an N-type epitaxial layer, a P trap, a first N-type doping region, a groove, a first metal layer and a source-electrode metal layer. The P trap is located in the N-type doping region, the first N-type doping region is arranged in the P trap, and the groove penetrates through the first N-type doping region, the P trap and the N-type epitaxial layer until the P-type substrate. A first oxidation layer is arranged on the side wall of the groove. The groove is filled with first polycrystalline silicon of P-type doping. The upper surface of the first polycrystalline silicon is located inside the P trap and is lower than the first N-type doping region. The first metal layer covers the upper surface of the first polycrystalline silicon and covers the first N-type doping region. The source-electrode metal layer is located on the back face of the P-type substrate. The invention further discloses a manufacturing method of the LDMOS. A source electrode is led out from the back face of the substrate instead of being originally led out from the front face of the substrate, the design area of the original source electrode region on the front face is effectively reduced, the design width of a channel in a gate region is increased, and the on resistance is reduced.

The invention discloses a control method and a control device for a touch sliding strip and a household electric appliance. Identifiable key regions and non-identifiable key regions of the touch sliding strip are alternately distributed on the touch sliding strip; a pressure signal output by the touch sliding strip is acquired; whether a pressure value corresponding to the pressure signal belongs to an identifiable key region or a non-identifiable key region according to a pressure value range of the pressure value can be determined; when the pressure value belongs to the identifiable key region, whether the current operation is in sliding operation or key operation can be determined by judging whether a pressure change value is larger than a preset value during pressing down of the touch sliding strip. According to the control method and the control device, the identifiable key regions are equivalent to touch keys, that is, the touch keys are embedded into the touch sliding strip, so that integration of the touch keys and the touch sliding strip is realized, and whether the current operation is in the sliding operation or the key operation can be determined by judging whether the pressure change value is larger than the preset value during pressing down of the touch sliding strip.

The invention discloses a liquid crystal display television circuit system and an interface, the liquid crystal display television circuit system comprises a TCON driving module and a machine core board, the TCON driving module integrates a TCON driving part, an upper screen interface and an FFC interface, and the machine core board comprises a machine core main control SOC chip and integrates anFFC interface; and the FFC interface is used for connecting the machine core board and the TCON driving module, the number of PINs of the FFC interface is 80, and a PIN functional area comprises a level conversion area, an interface detection area, an SPI area, an I2C area, a display data area, an LOCK area, a TBD area, a VIN area and a GND area. According to the invention, the FFC interface containing 80 PINs is arranged, so that the FFC interface can adapt to different liquid crystal display screens and can be compatible with the existing standard VBO interface to be placed on the PCB, the circuit design area is saved, and the application range is expanded.

The invention relates to a household garbage smashing, winnowing and compressing transportation car. The household garbage smashing, winnowing and compressing transportation car comprises a car chassis which is provided with a garbage collecting and compressing tank, an automatic charging device, a garbage can and a smashing and winnowing device; the garbage collecting and compressing tank is arranged on the tail portion of the car; the garbage can and the smashing and winnowing device are arranged between the head portion and the tail portion of the car; the automatic charging device used for grabbing a roadside garbage can is connected with the side edge of the car chassis below the garbage can; and the smashing and winnowing device used for smashing and classifying the garbage is connected with the garbage can and the garbage collecting and compressing tank. The household garbage smashing, winnowing and compressing transportation car has the beneficial effects that the garbage pretreatment function of garbage smashing and plastic thin film winnowing is achieved, the garbage is stored in different bins after being classified, the sealing performance is good, secondary pollution cannot be caused, the garbage smashing and compressing loading capacity is high, the automation level is high, loading and unloading are safe and reliable, and the work efficiency is high.

The invention provides a tile laying primary and secondary machine and a tile laying method. The tile laying primary and secondary machine comprises a tile conveying machine and a tile laying machine.The tile laying primary and secondary machine is characterized in that the tile conveying machine and the tile laying machine are arranged together in the mode that the tile conveying machine and thetile laying machine can be automatically connected and be automatically separated. When tiles need to be supplemented, the tile conveying machine can be automatically separated from the tile laying machine to take the tiles, and after the tile taking operation is accomplished, the tile conveying machine can automatically return to the tile laying machine and is connected with the tile laying machine again. On the basis of the tile laying primary and secondary machine and the tile laying method, the tile laying primary and secondary machine is moved to the target positions of the tiles, and therefore the process of automatically absorbing the tiles and automatically laying the tiles is achieved. By the adoption of the full-automatic tile laying primary and secondary machine, the design area is small, the space is made full use of, movement is sensitive, and the efficiency of tile laying in a room can be improved.

The invention discloses a method for improving even conduction of an ESD protection device. The method is suitable for characteristic improvement of an electrostatic discharge (ESD) protection device in an integrated circuit, wherein, an MOS transistor is provided with a plurality of finger-shaped components which are connected with each other in parallel, and each of the finger-shaped component is respectively connected with a parasitic triode in parallel, and a collector electrode (i.e., a drain electrode of the MOS transistor) of each parasitic triode is coupled with an operating potential terminal or an I/O terminal of the integrated circuit by a common drain line; an emitter electrode (i.e., a source electrode of the MOS transistor) of the parasitic triode is connected with a common ground potential terminal together with a gate electrode and a substrate of the MOS transistor. The method is characterized in that: the substrate terminal of the MOS transistor is also serially connected with a high-resistance apparatus in the ESD protection device, and the substrate terminal of the MOS transistor is further coupled to the common ground potential terminal together with the source electrode and the gate electrode, which can reduce trigger voltage of Gated_MOSFET, causes a large-sized protection device to be more evenly conducted, improves the ESD protection capability of the device, and further reduces the circuit design area and lower the development cost.

This invention discloses a shift register, it contains multi-group shift register element in series connection and is controlled by the first clock signal and second clock signal which are in opposite. Each shift register element contains: switch element receives the input signal, outputting the sample signal base on the first clock signal and second clock signal, the inverting element links the switch element, and receives the sample signal, outputs the pilot signal; as well as the signal production element, it links the inverting element, exports the output signal after receiving the pilot signal.

The invention discloses a display panel, a driving method thereof and a display device, and relates to the technical field of display; and the display panel comprises a plurality of first signal output lines, a plurality of first signal input lines, a plurality of fingerprint recognition units arranged in an array, a plurality of touch electrodes arranged in an array and a driving circuit, and onetouch electrode corresponds to at least two fingerprint recognition units; one touch electrode is electrically connected with at least one first signal input line; the fingerprint identification unitcomprises a photodiode, a first electrode and a switch module, the first electrode of the photodiode is electrically connected with the switch module, the second electrode of the photodiode is electrically connected with the corresponding touch electrode, each switch module is electrically connected with one first signal output line, and the first electrode is electrically connected with the first electrode of the photodiode. According to the invention, wiring in the display panel can be reduced, the correct rate of fingerprint identification can be improved, and the narrow bezel of the display panel can be realized.

The invention provides a mirror image inhibiting frequency mixer in a chip of an RF signal transceiver, and aims at solving the problems that a mirror image inhibition effect of a traditional mirror image inhibiting frequency mixer is not satisfied and gain loss is generated by the whole circuit. The mirror image inhibiting frequency mixer comprises a buffer unit, a frequency mixer core unit, a passive multi-phase filter, a summation circuit and a bias circuit; the buffer unit separates the frequency mixer core unit from a pre-stage frequency halving circuit; a double-balance orthogonal frequency mixing structure in the input end of the mixer core unit realizes a down-conversion function for input signals, and provides four paths of orthogonal differential signals for the post-stage passive multi-phase filter; the passive multi-phase filter realizes narrowband inhibition of mirror image interference signals; the summation circuit controls a gain compensation result of the buffer unit,the frequency mixer core unit, the passive multi-phase filter and the bias circuit via a two-bit binary digital control signal; and the bias circuit provides a variable tail current for the buffer unit, and a corresponding bias voltage for transconductance and switching levels in the frequency mixer core unit. Thus, a good mirror image inhibition effect can be realized.

The invention provides a non-volatile random access memory (100) and an operation method thereof. The non-volatile random access memory (100) comprises a memory cell array (110) composed of multiple memory cell blocks (111), and a peripheral circuit connected to the memory cell array (110). The peripheral circuit comprises an address decoding circuit (120) for selecting the corresponding memory cell block according to address input information, a block operation-mode information register (130) for storing operation mode information of all the memory cell blocks (111) and carrying out re-writing under the action of a control signal (160), a writing driving circuit (140) for outputting a writing operation mode to the memory cell array (110) according to the operation mode information stored in the block operation-mode information register (130), and a reading circuit (150) for outputting a reading operation mode to the memory cell array (110) according to the operation mode information stored in the block operation-mode information register (130). The non-volatile random access memory is compatible with two phase change memories having different operation modes, simplifies an interface design, saves a design area, reduces power consumption and improves a speed.

The invention discloses a data amount-variable radix-4 module for a fast Fourier transform (FFT)/inverse fast Fourier transform (IFFT) processor. The radix-4 module consists of registers, a radix-4 arithmetic unit, an alternative multi-path selector, a selection and control module, a multiplication module and a rotation factor module. The alternative multi-path selector comprises two multi-path selectors MUX1 and MUX2. When input, external data is divided into four data blocks, the data of the first three blocks is stored in the registers, and when arriving, the data of the last block is transmitted together with the data of the first three blocks in the registers to the radix-4 arithmetic unit for an operation. By the data amount-variable radix-4 module for the FFT/IFFT processor, a plurality of registers can be combined on the premise of not changing conventional clock frequency so as to reduce register connecting lines and a designing area, save chip resources and increase the utilization rate of resources.

The invention discloses a rainwater alarm device which comprises a water containing groove, a single chip microcomputer control circuit, a vocal apparatus and an alarm light, wherein the water containing groove consists of a metal body and a plastic body; the single chip microcomputer control circuit consists of an AT89S51 single chip microcomputer, a resistor, a capacitor and a crystal oscillator; a buzzer is adopted as the vocal apparatus; a red-light light-emitting diode is adopted as the alarm light; and the water containing groove is connected with the single chip microcomputer control circuit through a water-proof lead. The invention discloses a rainwater alarm device which has a simple structure, and can be installed movably; a 51 single chip microcomputer with the low voltage and low power consumption is adopted for realizing intelligent control, the circuit structure is simplified, the environmental suitability is strong, and the reliability is high; the water containing groove is designed uniquely, rainwater can be timely cleared, and the rainwater switching function is provided; and a charging battery is adopted for charging, so that the charging is convenient and fast.

The invention discloses a broadband monolithic integrated low noise amplifier, which comprises a first-stage amplifier, a second-stage amplifier, a third-stage amplifier, first-second stage matching and second-third stage matching, wherein the first-stage amplifier is mainly formed by one NMOS tube, one resistor, four inductors, one capacitor and two bias supplies; the second-stage amplifier is mainly formed by one NMOS tube, two resistors, two inductors, one microstrip line and two bias supplies; the third-stage amplifier is mainly formed by one NMOS tube, two resistors, two inductors, one capacitor, one microstrip line and two bias supplies; the first-second stage matching is mainly formed by one capacitor and one inductor; and the second-third stage matching is mainly formed by one capacitor and one inductor. The broadband monolithic integrated low noise amplifier has the characteristics of miniaturization, low noise, high gain, low cost and high reliability.