41 results about "Asynchronous fifo" patented technology

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an FPGA software and hardware cooperation testing platform based on a BFM. The test platform is formed by connecting a BFM with a Testbench, an AXI bus, an off-chip DDR and a DUT. The test process comprises the steps that the Testbench issues parameters through a transaction function interface, the BFM reads an excitation vector from the off-chip DDR / on-chip BRAM through an Avalon main interface, adaptive transmission of a system bus clock domain and a DUT clock domain is completed through double asynchronous FIFO (SNDfifo / RECfifo), and signal level interaction with the DUT is achieved through a pin protocol interface; the state machine dynamically switches long and short simulation modes according to the vector length, and drives the output vector to be written back and stored; the error monitoring unit monitors data flow faults in the whole process and outputs seven types of error reporting codes. The simulation equivalent frequency reaches a 10 megahertz level, and the method is suitable for efficient verification of the digital IC.

The invention discloses an efficient data flow transceiving controller applicable to a multi-core storage and calculation system, which comprises two transmitting controllers and two receiving controllers, and the transmitting controllers and the receiving controllers are arranged on the peripheries of cores and are used for performing data packaging and transmitting and data flow judgment work; wherein the sending controller comprises a configurable asynchronous FIFO (First In First Out), a data packaging unit and an error correction code generating unit; the receiving controller comprises an error correction code decoding unit, a data packet unpacking unit and a microchip detection unit; the flit detection unit is used for detecting information in a head flit to judge whether data meet the calculation requirement of the current core particle or not, and if the data do not belong to the task range of the current core particle, the data are redirected to the sending controller through a bypass transmission mechanism. According to the application, the transmission speed of the data stream among different core particles is improved, and the data stream can be dynamically planned and transmitted according to the preset rule by constructing the efficient data transceiving controller.

The invention discloses an inter-chip interconnection method and system based on an AXI bus, the method is applied to the inter-chip interconnection system based on the AXI bus, and the system comprises a first chip, a second chip and a verification module; the process that one chip sends the AXI signal to the other chip comprises the steps that the chip sends the AXI signal through each channel of the AXI bus according to a preset time sequence and caches the AXI signal into the asynchronous FIFO corresponding to each channel; reading the AXI signal of the asynchronous FIFO corresponding to each channel after the AXI signal comes out from the respective asynchronous FIFO, and encoding the preset bit width of the AXI signal of each channel; sending the coded AXI signals of each channel to an inter-chip signal line in a time-sharing manner; and the moments of occupying the inter-chip signal line by the AXI signal of each channel are different. The AXI signals are separately sent in time through the channels of one chip, the number of signal lines between the chips can be reduced, the first chip does not need too many IO pins for connection, and the pressure caused to the design and performance of a hardware circuit is reduced.

This invention proposes a superconducting single-flux quantum cross-clock domain communication method and system based on asynchronous FIFO, comprising: initializing the FIFO; an external write circuit inputting a write signal to the FIFO; the FIFO generating a write address and a write flag based on the write signal, and comparing them with the read address and read flag; if the read address and write address are equal, but the write flag and read flag are opposite, the system waits for the external read circuit to read data and generate a new read flag and read address, and then writes the data to be written to the FIFO according to the write address; otherwise, the system writes the data to be written to the FIFO according to the write address. The external read circuit inputs a read signal to the FIFO and generates a read address and read flag, comparing them with the write address and write flag; if the read address and write address are the same, and the read flag and write flag are also the same, the system waits for the external write circuit to write data and generate a new write address and write flag, and then reads the data according to the read address and returns to the external read circuit; otherwise, the system reads the data according to the read address and returns to the external read circuit.

The invention discloses a P2P equal-bandwidth output method and device for a display system and a display control chip. The objective of the invention is to solve the problem that when TCON and COMBO TX clocks cannot be divided exactly, lossless transmission can still be realized and the FIFO area can be reduced. A shallow asynchronous FIFO is configured in the COMBO TX, the TCONPLL frequency is adjusted in a closed-loop mode through a real-time water reading line, the step length is 1 / 256 times of a reference clock, and equal bandwidth output under + / -3% spread spectrum tolerance is achieved; and the horizontal blanking interval dynamically adds and deletes + / -8 packets on the P2P data packets according to rows, and keeps the bandwidth constant. Parallel simultaneous implementation is realized, and the depth of the FIFO is 1t; 256 level, and the chip area is significantly reduced. The chip integrates waterline monitoring, frequency modulation and packet increasing and decreasing modules, supports various P2P codes of 8 / 10, 9 / 10, 8 / 9, 20 / 24 and 24 / 28, and is suitable for various high-resolution display devices.

The invention provides an FFT (Fast Fourier Transform) automatic calculation structure based on DMA (Direct Memory Access), which relates to the field of communication technology signal processing, and comprises the following steps: a bus interface adaptation unit determines a space address of write-in data, a write-in data interface, a space address of output data and an output data interface of direct memory access; the FFT calculation input control unit writes write-in data into the asynchronous FIFO module through the write-in data interface according to the write request signal, and analyzes the write-in data through the data unpacking module to obtain analyzed data; the analysis data is input into the FFT calculation unit; the FFT calculation unit performs FFT calculation on the analysis data to obtain calculation data; the FFT calculation output control unit caches calculation data to an output data cache module; packaging the calculation data to obtain output data; and writing the output data into the spatial address of the output data through the output data interface. According to the invention, the calculation efficiency of FFT can be improved.

The application belongs to the technical field of electronic circuits. A high-speed data acquisition method and system of an isolation circuit based on a physical loop clock are proposed, a clock signal physical loop path is constructed, data signals and loop clock signals are transmitted through the same digital isolator channel, and then sampled through the internal loop clock domain of the FPGA and processed through the asynchronous FIFO cross-domain, realizing delay automatic offset and seamless data transfer. The application breaks through the isolation delay bottleneck, improves the acquisition rate, can automatically compensate the delay drift caused by environmental changes, avoids the metastability across the clock domain, reduces the design and calibration cost, and is suitable for high-voltage application scenarios such as industrial automation and new energy.

The application is a satellite 5G large dynamic high-speed transmission real-time receiving and time synchronization method and system based on FPGA, and belongs to the technical field of wireless communication.The system is provided with a real-time receiving module, a time synchronization module and the like at the receiving end of a satellite-ground transmission link.The method comprises the following steps: the receiving end stores data into a DDR3 in real time by using an asynchronous FIFO, and performs time synchronization once every transmission half-frame signal;the starting point of a symbol is calculated in a multi-symbol combination mode, the content of each symbol is obtained according to the starting point of the symbol, a correlation value is calculated according to a known PSS sequence, the starting point of the half-frame signal is obtained, and subsequent CP removal and demodulation operations are continuously performed;the application solves the problem of timing synchronization difficulty caused by large time delay and large frequency offset, realizes low complexity and timing synchronization error not affected by carrier frequency offset under the premise of ensuring accuracy, and can be used for the time synchronization process of a satellite mobile communication system with large dynamic frequency offset.

The present disclosure provides a method for transmitting a signal between a drive chip and a flash memory, and a drive chip. By means of an IOBUF, an APR directly transmits to a flash memory a control signal for reading / writing the flash memory. Upon receiving a read / write request, the flash memory feeds back the read / write request to the IOBUF. A feedback signal is registered for one clock cycle by means of a register inside the IOBUF to obtain a delayed signal, thereby reducing timing urgency of directly providing the feedback signal from the flash memory to the inside of the APR. The delayed signal is transmitted to an asynchronous FIFO memory of the APR for clock domain crossing processing to obtain an internal signal required by the APR. Clock domain crossing transmission of the signal output by the register of the IOBUF is performed by means of the asynchronous FIFO memory, avoiding a timing impact caused by an interactive routing delay between an APR circuit and an IOBUF circuit.

The invention relates to an asynchronous first-in first-out device and a chip. The asynchronous first-in first-out device is characterized in that a write control module obtains a current write vector in a one-hot binary format by querying a null vector data structure, generates a current write address according to the current write vector, controls a memory to write data to be written into the current write address, and transmits the current write vector to a read control module in a delayed manner; the read control module updates an occupied vector data structure according to the current write vector transmitted in a delayed manner; the read control module queries the occupied vector data structure to obtain a current sequential read vector in a one-hot binary format, generates a current sequential read address according to the current sequential read vector, and controls the memory to read read data according to the current sequential read address; the read interface module sends the read data and the current sequential read address to downstream external equipment together, and the downstream external equipment can perform backward reading subsequently by using the current sequential read address; by means of the asynchronous FIFO device, the asynchronous function and the read-back function of the FIFO device can be achieved, and the area of the asynchronous FIFO device is reduced.

The present application provides an asynchronous FIFO memory, which comprises a synchronous FIFO memory and an asynchronous buffer. Data is written into the synchronous FIFO memory if there is a write request, the synchronous FIFO memory has a FIFO mode and a continuous mode, in the FIFO mode, the oldest written data is not allowed to be overwritten by the written data, in the continuous mode, the oldest written data is allowed to be overwritten by the written data. Data is read from the asynchronous buffer if there is a read request, the asynchronous buffer buffers the data read from the synchronous FIFO memory, the asynchronous buffer is not allowed to be written into when it is full, and the capacity of the asynchronous buffer is less than that of the synchronous FIFO memory. In this way, the area of the memory is saved, and the utilization of the memory is improved.

The invention discloses a CSR-based inter-core low-delay communication method for an internal IP (Internet Protocol) of an SOC (System on Chip), which comprises the following steps: S1, a group of customized CSR registers are newly added in a CPU (Central Processing Unit) to form a CSRMASTER, the CSRMASTER 0 is used for controlling an IP and the CPU only writes data, and the CSRMASTER 1 is used for feeding back an IP state and the CPU reads the data; s2, CSRSLAVEs are integrated at the IP core end in a WRAP packaging mode, CSRSLAVE0 is used for controlling the IP, and CSRSLAVE1 is used for feeding back the state of the IP; s3, a direct connection line is led out from the CSRMASTER0 of the CPU and reaches the CSRSLAVE0 through an asynchronous FIFO across clock domains, and the control data issued by the CSRMASTER0 are analyzed by the CSRSLAVE0; and S4, a direct connection line is led out from the CSRSLAVE1 at the IP core end, the received control information reaching the CSRMASTER1 and the CSRSLAVE0 through the asynchronous FIFO crossing the clock domain comprises an instruction related to the feedback state information of the IP core, and after the instruction is received, the CSRSLAVE1 feeds back the instruction to the designated bit of the CSRMASTER1 according to the feedback requirement.

The invention provides a JESD204B-oriented non-uniform-uniform data stream conversion system and an operation method, belongs to the technical field of data conversion, and aims to solve the problem that data transmission between a PS end and a PL end of ZYNQ cannot meet a high-speed output scene, the conversion system comprises the PS end and the PL end, and the PS end is connected with the PL end through an AXIMM interface; the PS end comprises a DDR module, and the DDR module is used for storing waveform data to be transmitted; and the PL end comprises a DMA (Direct Memory Access) module, an asynchronous FIFO (First In First Out) module, a bit width conversion module and a JESD204B module which are connected in sequence. The operation method comprises the following steps: transmitting waveform data from the DDR module to the PL end through the data interface; the PL end carries out continuous reading, data stream buffering, data stream cross-clock processing and bit width conversion on the received waveform data, and finally the data is sent or received according to a JESD204B protocol specification after transmission layer framing, link layer processing and physical layer serialization are carried out by the JESD204B module.

The invention relates to the technical field of communication, in particular to an interface channel rate adaptation method and system and a computer program product, and the method comprises the steps: generating a token of a corresponding channel in a clock domain of each channel according to channel flow; synchronizing tokens of all channels to a main clock domain; and scheduling the flow of each channel in the main clock domain according to the token accumulation number of each channel to realize rate adaptation of all channels. According to the method, the token of the corresponding channel is generated in the clock domain of each channel based on the channel flow, the tokens of all the channels are synchronized to the main clock domain through the asynchronous fifo, the flow of each channel is scheduled in the main clock domain according to the accumulated number of the tokens of each channel, and rate adaptation of all the channels is achieved.

The application provides a double-to-single and single-to-double transmission method, a HDMI double-pixel transmission method and a device. The FIFO and the state machine are matched, so that when the video stream is converted from double pixels to single pixels, the phenomenon that the asynchronous FIFO reading clock is faster than the writing clock and the FIFO is easily read empty is avoided. The writing request signal of the two asynchronous FIFO writing enables controlled by the two levels opposite to the flip signal is set, so that the subsequent asynchronous FIFO processing video stream is prevented from being full and the data is covered when the writing clock is faster than the reading clock and the FIFO depth is insufficient. The pixel conversion is performed outside the transmitter IP core and the receiver IP core of the HDMI interface, so that the double-pixel transmission function is realized under the condition that the original IP core input bit width is unchanged. The bit width of the data bus is increased through the double-pixel transmission, the working clock frequency of the physical layer IP core of the serial deserializer is significantly reduced, and the data throughput is improved.

The invention discloses a storage and processing method and system of an integrated broadband Fourier transform microwave spectrometer based on an FPGA (Field Programmable Gate Array), and a storage medium. According to the method, time domain signals collected by an ADC are combined and written into a DDR3 through an asynchronous FIFO, and are split and output during reading; a radix-4 FFT algorithm is adopted, a ping-pong storage structure and an assembly line butterfly operation unit are combined, and conflict-free parallel FFT calculation is completed through six-stage extraction through cooperation of an RAM module, a twiddle factor module and a storage management unit; solving a frequency domain complex signal module value through pure shift addition operation by using a CORDIC algorithm, and correcting amplitude attenuation by using a compensation factor; data are stored through a dual-port RAM, four states are controlled by a finite-state machine to be switched, and an average result is output after corresponding points are accumulated. The system comprises a data storage module, a Fourier transform processing module, an amplitude calculation module and an accumulation averaging module. According to the invention, the data throughput efficiency and the real-time processing capability of the broadband microwave spectrometer are obviously improved.

The invention discloses a time delay calculation method and device and a related product, belongs to the technical field of communication, and solves the problem of poor synchronization performance of a network. The method comprises the following steps: providing a first working clock for a media access control (MAC) layer, a physical layer and an FIFO module of the synchronization equipment through a first synchronous clock, and providing a second working clock for the physical layer and an asynchronous FIFO module of the synchronization equipment; the first working clock is used for triggering the MAC layer to send a synchronous message to the asynchronous FIFO module, and the second working clock is used for triggering the asynchronous FIFO module to send the synchronous message to the physical layer; determining a first target period according to a common multiple of the frequency or period of the first work clock and the frequency or period of the second work clock; controlling the MAC layer to send the synchronization message in the first target period; and determining the physical path time delay of the synchronization message transmitted from the MAC layer to the timestamp reference point of the physical layer. The embodiment of the invention is used in a scene of clock synchronization.

The application discloses an AHB bus cross-clock domain data synchronization method based on a self-defined handshake protocol and particularly relates to the AHB technical field, which comprises the following steps: designing a self-defined handshake protocol, setting an AHB bus conversion bridge, setting an asynchronous FIFO synchronization circuit, setting a handshake protocol conversion bridge, and completing the cross-clock domain synchronization of a request path and a response path. Through the request and response full-handshake mechanism, the application can realize data synchronization between any clock domains in any frequency combination of a source clock domain and a target clock domain, avoid the timing conflict caused by the superposition of multiple requests, fix the READY signal of the response channel as a high level, and completely solve the deadlock problem of the existing pulse synchronization scheme. In addition, the application optimizes the depth required by the asynchronous FIFO circuit and the information between different clock domains by utilizing the characteristic that the in-transit request of the handshake protocol is less than or equal to 1, optimizes the timing of the AHB bus conversion bridge through scene conversion logic, realizes the request of any burst transmission type, and improves the synchronization and transmission efficiency.

An asynchronous FIFO system (300) for transferring data from a transmit power region (302) to a receive power region (304) on a chip comprises a plurality of memory elements (308) and a plurality of cyclic multiplexers (310, 312) in the transmit power region, a data toggling multiplexer (318) and a plurality of pointer generators (314, 316) in the receive power region, and a plurality of level shifters (322a~d) positioned between the cyclic multiplexer in the transmit power region (302) and other elements in the receive power region, each The pointer generator is configured to provide each circular multiplexer with a pointer value so that each circular multiplexer can transfer discontinuous data (1, 3, 5, 7 or 0, 2, 4, 6) from multiple memory elements (308), and the data toggling multiplexer (318) is configured to periodically read the data (0, 1, 2, 3, 4, 5, 6, 7, 8) from multiple circular multiplexers (310, 312) in order to reconstruct the data from the multiple memory elements in the received power domain.

The invention discloses an AHB (Advanced High-performance Bus) cross-clock domain data synchronization method based on a user-defined handshake protocol, and particularly relates to the technical field of AHBs, which comprises the steps of designing the user-defined handshake protocol, setting an AHB conversion bridge, setting an asynchronous FIFO (First In First Out) synchronous circuit, setting a handshake protocol conversion bridge and finishing cross-clock domain synchronization of a request path and a response path. Through a request and response full handshake mechanism, any frequency combination of a source clock domain and a target clock domain, data synchronization is carried out between any clock domains, time sequence conflicts caused by superposition of multiple requests are avoided, a response channel READY signal is fixed to be high level, no response blocking scene exists, the deadlock problem of an existing pulse synchronization scheme is thoroughly solved, and the time sequence conflicts caused by superposition of multiple requests are avoided. The characteristic that the in-transit request of a handshake protocol is smaller than or equal to 1 is utilized, the depth needed by the asynchronous FIFO circuit and information between different clock domains are optimized, the AHB bus conversion bridge optimizes the time sequence through scene-based conversion logic, requests of any burst transmission type are achieved, and the synchronization and transmission efficiency is improved.

The invention discloses a high-speed low-light image enhancement method based on an FPGA, and the method comprises the steps: carrying out the asynchronous FIFO data caching of data stored in a DDR, forming an output array, and carrying out the edge extraction and illumination mapping solving through a denoised pixel value result outputted after Gaussian filtering; based on the edge data, the solved illumination mapping coefficient and the de-noised pixel value, performing inverse color coefficient solving on the output array to obtain an inverse color coefficient; based on the inverse color coefficient denoising pixel value, solving the inverse color image to obtain an inverse color image; obtaining a positive color image based on inverse color image transformation, and solving a correction coefficient based on the positive color image; and performing Gamma color correction on the inverse color image through the correction coefficient, and outputting a low-light-level enhanced image. The method can be applied to various scenes in real time with balanced effects, high-speed image enhancement is better realized, and the image enhancement effect is improved.

This invention provides an input processing method and circuit for an image data interface, applied to an input processing circuit for an image data interface. The method includes: determining the memory size of an asynchronous FIFO and the threshold conditions for the occurrence of pre-full and pre-empty signals of the asynchronous FIFO; at the input end of the asynchronous FIFO, determining whether the pre-full signal is true; if the determination result is yes, then further determining whether the currently input data is valid image data; if yes, then continuing to write data to the asynchronous FIFO; if no, then pausing one data writing operation to the asynchronous FIFO; at the output end of the asynchronous FIFO, determining whether the pre-empty signal is true; if the determination result is yes, then further determining whether the data output in the last clock cycle before the pre-empty signal appeared is valid image data; if it is valid data, then outputting real-time data; if not, then copying the data from the previous clock cycle and outputting it. This invention can ensure the integrity of valid image data.

The invention particularly relates to a simulation system and method with an accurate period based on an FPGA (Field Programmable Gate Array). According to the FPGA-based simulation system with the accurate period, a virtual platform processing system module performs data interaction with a universal interface shell module, so that software side simulation, management and monitoring are realized; the DUT module is responsible for receiving external interaction data of the virtual platform processing system module, and sending a request and receiving a response to the outside through a data interface; and the universal interface shell module injects a request or a sample of the DUT module into the asynchronous FIFO cluster in a non-intrusive manner, and notifies the virtual platform processing system module to perform software processing. According to the FPGA-based simulation system and method with the accurate period, a large-scale system can be effectively decomposed into a plurality of small-scale subsystems, prototyping is carried out on the FPGA, non-interference and accurate-period co-simulation is realized on the low-cost FPGA by adopting a transaction period hybrid modeling technology, the verification efficiency is improved, and the total ownership cost is reduced.

A Gray code counter is enabled to increment by greater than one and still obey a rule of only one bit of change. The Gray code counter has applicability, for example, with use with an arbiter to control a multi-input asynchronous FIFO usable to synchronize data transfers between asynchronous source and destination clock domains.

The present disclosure relates to an operation core circuit and a computing chip. An operation core circuit includes: an input module configured to receive a data block; an operation module configured to perform a hash operation on the data block, including a plurality of operation stages arranged in a pipeline structure, such that a data signal based on the data block is sequentially transmitted along the plurality of operation stages; an asynchronous FIFO module arranged between adjacent first and second operation stages, configured to receive the data signal output from the first operation stage using a first clock signal and output the data signal to the second operation stage using a second clock signal, the first operation stage preceding the second operation stage; a first clock module configured to provide the asynchronous FIFO module and the first operation stage and its preceding operation stages with the first clock signal; and a second clock module configured to provide the asynchronous FIFO module and the second operation stage and its subsequent operation stages with the second clock signal, wherein the first clock signal and the second clock signal have the same frequency.

An arbitrary depth asynchronous FIFO memory is provided. The asynchronous FIFO memory includes a dual port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit, and a write pointer synchronization unit. The write pointer decoder, the full detection unit, and the read pointer synchronization unit are located in a first clock domain. The read pointer decoder, the empty detection unit, and the write pointer synchronization unit are located in a second clock domain. The write pointer decoder is coupled to a write port of the dual port memory and provides a write pointer to the write port of the dual port memory. The read pointer decoder is coupled to a read port of the dual port memory and provides a read pointer to the write port of the dual port memory.

The invention discloses a UART-SPI conversion system and method based on an FPGA, and belongs to the technical field of data communication. The system comprises an upper computer, an FPGA board and a chip to be tested; a UART-SPI communication protocol conversion circuit is integrated in the FPGA board, and the UART-SPI communication protocol conversion circuit comprises a UART interface module, a system control module, a register configuration module, an SPI interface module, a clock and reset management module, a peripheral signal generation module, an asynchronous FIFO module and a clock domain crossing synchronization module. And the system control module analyzes the configuration data packet from the upper computer and executes various configuration instructions. The UART data frame structure and the SPI data frame structure are dynamically configured through the instruction, flexible configuration of an SPI mode, a clock, UART parameters and various peripheral signals is supported, the reconfigurability of an FPGA is fully utilized, the adaptability to diversified communication protocols in scenes such as chip testing is remarkably improved, and the method has the advantages of being short in development period and wide in applicability.

The invention discloses a method and a device for synchronizing multiple multichannel ADC (Analog to Digital Converter) chips, and belongs to the technical field of wireless communication and signal processing. According to the method, homologous and in-phase reference clock signals are provided for a plurality of ADC chips and an FPGA through a multi-path output clock PLL chip; establishing an independent data processing path for each ADC in the FPGA, and sequentially performing LVDS (Low Voltage Differential Signaling) serial-to-parallel conversion and data sampling point splicing processing; asynchronous FIFO is adopted to uniformly convert asynchronous data of each ADC chip to the same system clock domain, and all the asynchronous FIFOs are read at the same time through synchronous control logic to achieve data synchronous output. The device adopts a star topology hardware architecture, and comprises a reference clock source, a multi-channel clock PLL chip, a plurality of ADC chips and an FPGA main control chip integrating all processing modules. The problems of clock phase deviation and data sampling asynchronization among multiple ADCs are solved, high-precision synchronization with the phase difference smaller than 0.3 ns among channels is achieved, and the method has the advantages of being low in implementation cost, high in system expansibility and good in real-time performance.

The invention discloses a data transmission method and device based on a QSPI interface. The method comprises the following steps: receiving serial communication data; analyzing the serial communication data to obtain a command word and an address; after the serial communication data is received, determining a transmission bit of data transmission according to the command word; transmitting a command word and an address to a system clock domain through asynchronous fifo; in a system clock domain, determining a transmission channel according to the command word and the address; when the transmission channel is a write channel, acquiring serial communication data through a system clock domain, and sending the serial communication data in the transmission channel according to the transmission bit; and when the transmission channel is the read channel, receiving data in the transmission channel according to the transmission bit. Accurate control of data is realized by transmitting command words and addresses to a system clock domain and distinguishing read-write channels. Data are sent and received through a system clock domain, the efficiency and reliability of data transmission are improved, and the requirement of a modern system for high-speed data interaction is met.

The invention discloses an SPI (Serial Peripheral Interface) slave controller and a working method thereof, the SPI slave controller comprises an SPI interface, an SPI sending shift register, an SPI receiving shift register and a system bus interface, the SPI slave controller is integrated on a chip, and the SPI slave controller further comprises a core control module, a sending asynchronous FIFO (First In First Out), a first DMA (Direct Memory Access) controller, a receiving asynchronous FIFO, a second DMA controller and a register module; according to the technical scheme provided by the invention, the SPI slave controller adopts a double-asynchronous FIFO (First In First Out) controller architecture matched with double DMA (Data Memory Access) controller architecture, the communication frequency is greatly improved in the flow, the fixed multiple relationship which must be met between a system clock and a serial communication clock in the traditional SPI design is broken, the higher communication rate is allowed to be supported under the lower system clock frequency, and the communication efficiency is improved. And the overall data transmission efficiency and the system throughput capacity are improved.