21 results about "Asynchronous fifo" patented technology

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an FPGA software and hardware cooperation testing platform based on a BFM. The test platform is formed by connecting a BFM with a Testbench, an AXI bus, an off-chip DDR and a DUT. The test process comprises the steps that the Testbench issues parameters through a transaction function interface, the BFM reads an excitation vector from the off-chip DDR / on-chip BRAM through an Avalon main interface, adaptive transmission of a system bus clock domain and a DUT clock domain is completed through double asynchronous FIFO (SNDfifo / RECfifo), and signal level interaction with the DUT is achieved through a pin protocol interface; the state machine dynamically switches long and short simulation modes according to the vector length, and drives the output vector to be written back and stored; the error monitoring unit monitors data flow faults in the whole process and outputs seven types of error reporting codes. The simulation equivalent frequency reaches a 10 megahertz level, and the method is suitable for efficient verification of the digital IC.

This invention proposes a superconducting single-flux quantum cross-clock domain communication method and system based on asynchronous FIFO, comprising: initializing the FIFO; an external write circuit inputting a write signal to the FIFO; the FIFO generating a write address and a write flag based on the write signal, and comparing them with the read address and read flag; if the read address and write address are equal, but the write flag and read flag are opposite, the system waits for the external read circuit to read data and generate a new read flag and read address, and then writes the data to be written to the FIFO according to the write address; otherwise, the system writes the data to be written to the FIFO according to the write address. The external read circuit inputs a read signal to the FIFO and generates a read address and read flag, comparing them with the write address and write flag; if the read address and write address are the same, and the read flag and write flag are also the same, the system waits for the external write circuit to write data and generate a new write address and write flag, and then reads the data according to the read address and returns to the external read circuit; otherwise, the system reads the data according to the read address and returns to the external read circuit.

The invention provides an FFT (Fast Fourier Transform) automatic calculation structure based on DMA (Direct Memory Access), which relates to the field of communication technology signal processing, and comprises the following steps: a bus interface adaptation unit determines a space address of write-in data, a write-in data interface, a space address of output data and an output data interface of direct memory access; the FFT calculation input control unit writes write-in data into the asynchronous FIFO module through the write-in data interface according to the write request signal, and analyzes the write-in data through the data unpacking module to obtain analyzed data; the analysis data is input into the FFT calculation unit; the FFT calculation unit performs FFT calculation on the analysis data to obtain calculation data; the FFT calculation output control unit caches calculation data to an output data cache module; packaging the calculation data to obtain output data; and writing the output data into the spatial address of the output data through the output data interface. According to the invention, the calculation efficiency of FFT can be improved.

The application belongs to the technical field of electronic circuits. A high-speed data acquisition method and system of an isolation circuit based on a physical loop clock are proposed, a clock signal physical loop path is constructed, data signals and loop clock signals are transmitted through the same digital isolator channel, and then sampled through the internal loop clock domain of the FPGA and processed through the asynchronous FIFO cross-domain, realizing delay automatic offset and seamless data transfer. The application breaks through the isolation delay bottleneck, improves the acquisition rate, can automatically compensate the delay drift caused by environmental changes, avoids the metastability across the clock domain, reduces the design and calibration cost, and is suitable for high-voltage application scenarios such as industrial automation and new energy.

The application is a satellite 5G large dynamic high-speed transmission real-time receiving and time synchronization method and system based on FPGA, and belongs to the technical field of wireless communication.The system is provided with a real-time receiving module, a time synchronization module and the like at the receiving end of a satellite-ground transmission link.The method comprises the following steps: the receiving end stores data into a DDR3 in real time by using an asynchronous FIFO, and performs time synchronization once every transmission half-frame signal;the starting point of a symbol is calculated in a multi-symbol combination mode, the content of each symbol is obtained according to the starting point of the symbol, a correlation value is calculated according to a known PSS sequence, the starting point of the half-frame signal is obtained, and subsequent CP removal and demodulation operations are continuously performed;the application solves the problem of timing synchronization difficulty caused by large time delay and large frequency offset, realizes low complexity and timing synchronization error not affected by carrier frequency offset under the premise of ensuring accuracy, and can be used for the time synchronization process of a satellite mobile communication system with large dynamic frequency offset.

The invention discloses a storage and processing method and system of an integrated broadband Fourier transform microwave spectrometer based on an FPGA (Field Programmable Gate Array), and a storage medium. According to the method, time domain signals collected by an ADC are combined and written into a DDR3 through an asynchronous FIFO, and are split and output during reading; a radix-4 FFT algorithm is adopted, a ping-pong storage structure and an assembly line butterfly operation unit are combined, and conflict-free parallel FFT calculation is completed through six-stage extraction through cooperation of an RAM module, a twiddle factor module and a storage management unit; solving a frequency domain complex signal module value through pure shift addition operation by using a CORDIC algorithm, and correcting amplitude attenuation by using a compensation factor; data are stored through a dual-port RAM, four states are controlled by a finite-state machine to be switched, and an average result is output after corresponding points are accumulated. The system comprises a data storage module, a Fourier transform processing module, an amplitude calculation module and an accumulation averaging module. According to the invention, the data throughput efficiency and the real-time processing capability of the broadband microwave spectrometer are obviously improved.

The application discloses an AHB bus cross-clock domain data synchronization method based on a self-defined handshake protocol and particularly relates to the AHB technical field, which comprises the following steps: designing a self-defined handshake protocol, setting an AHB bus conversion bridge, setting an asynchronous FIFO synchronization circuit, setting a handshake protocol conversion bridge, and completing the cross-clock domain synchronization of a request path and a response path. Through the request and response full-handshake mechanism, the application can realize data synchronization between any clock domains in any frequency combination of a source clock domain and a target clock domain, avoid the timing conflict caused by the superposition of multiple requests, fix the READY signal of the response channel as a high level, and completely solve the deadlock problem of the existing pulse synchronization scheme. In addition, the application optimizes the depth required by the asynchronous FIFO circuit and the information between different clock domains by utilizing the characteristic that the in-transit request of the handshake protocol is less than or equal to 1, optimizes the timing of the AHB bus conversion bridge through scene conversion logic, realizes the request of any burst transmission type, and improves the synchronization and transmission efficiency.

An asynchronous FIFO system (300) for transferring data from a transmit power region (302) to a receive power region (304) on a chip comprises a plurality of memory elements (308) and a plurality of cyclic multiplexers (310, 312) in the transmit power region, a data toggling multiplexer (318) and a plurality of pointer generators (314, 316) in the receive power region, and a plurality of level shifters (322a~d) positioned between the cyclic multiplexer in the transmit power region (302) and other elements in the receive power region, each The pointer generator is configured to provide each circular multiplexer with a pointer value so that each circular multiplexer can transfer discontinuous data (1, 3, 5, 7 or 0, 2, 4, 6) from multiple memory elements (308), and the data toggling multiplexer (318) is configured to periodically read the data (0, 1, 2, 3, 4, 5, 6, 7, 8) from multiple circular multiplexers (310, 312) in order to reconstruct the data from the multiple memory elements in the received power domain.

This invention provides an input processing method and circuit for an image data interface, applied to an input processing circuit for an image data interface. The method includes: determining the memory size of an asynchronous FIFO and the threshold conditions for the occurrence of pre-full and pre-empty signals of the asynchronous FIFO; at the input end of the asynchronous FIFO, determining whether the pre-full signal is true; if the determination result is yes, then further determining whether the currently input data is valid image data; if yes, then continuing to write data to the asynchronous FIFO; if no, then pausing one data writing operation to the asynchronous FIFO; at the output end of the asynchronous FIFO, determining whether the pre-empty signal is true; if the determination result is yes, then further determining whether the data output in the last clock cycle before the pre-empty signal appeared is valid image data; if it is valid data, then outputting real-time data; if not, then copying the data from the previous clock cycle and outputting it. This invention can ensure the integrity of valid image data.

The invention particularly relates to a simulation system and method with an accurate period based on an FPGA (Field Programmable Gate Array). According to the FPGA-based simulation system with the accurate period, a virtual platform processing system module performs data interaction with a universal interface shell module, so that software side simulation, management and monitoring are realized; the DUT module is responsible for receiving external interaction data of the virtual platform processing system module, and sending a request and receiving a response to the outside through a data interface; and the universal interface shell module injects a request or a sample of the DUT module into the asynchronous FIFO cluster in a non-intrusive manner, and notifies the virtual platform processing system module to perform software processing. According to the FPGA-based simulation system and method with the accurate period, a large-scale system can be effectively decomposed into a plurality of small-scale subsystems, prototyping is carried out on the FPGA, non-interference and accurate-period co-simulation is realized on the low-cost FPGA by adopting a transaction period hybrid modeling technology, the verification efficiency is improved, and the total ownership cost is reduced.

The invention discloses a UART-SPI conversion system and method based on an FPGA, and belongs to the technical field of data communication. The system comprises an upper computer, an FPGA board and a chip to be tested; a UART-SPI communication protocol conversion circuit is integrated in the FPGA board, and the UART-SPI communication protocol conversion circuit comprises a UART interface module, a system control module, a register configuration module, an SPI interface module, a clock and reset management module, a peripheral signal generation module, an asynchronous FIFO module and a clock domain crossing synchronization module. And the system control module analyzes the configuration data packet from the upper computer and executes various configuration instructions. The UART data frame structure and the SPI data frame structure are dynamically configured through the instruction, flexible configuration of an SPI mode, a clock, UART parameters and various peripheral signals is supported, the reconfigurability of an FPGA is fully utilized, the adaptability to diversified communication protocols in scenes such as chip testing is remarkably improved, and the method has the advantages of being short in development period and wide in applicability.

The invention discloses a method and a device for synchronizing multiple multichannel ADC (Analog to Digital Converter) chips, and belongs to the technical field of wireless communication and signal processing. According to the method, homologous and in-phase reference clock signals are provided for a plurality of ADC chips and an FPGA through a multi-path output clock PLL chip; establishing an independent data processing path for each ADC in the FPGA, and sequentially performing LVDS (Low Voltage Differential Signaling) serial-to-parallel conversion and data sampling point splicing processing; asynchronous FIFO is adopted to uniformly convert asynchronous data of each ADC chip to the same system clock domain, and all the asynchronous FIFOs are read at the same time through synchronous control logic to achieve data synchronous output. The device adopts a star topology hardware architecture, and comprises a reference clock source, a multi-channel clock PLL chip, a plurality of ADC chips and an FPGA main control chip integrating all processing modules. The problems of clock phase deviation and data sampling asynchronization among multiple ADCs are solved, high-precision synchronization with the phase difference smaller than 0.3 ns among channels is achieved, and the method has the advantages of being low in implementation cost, high in system expansibility and good in real-time performance.

The invention discloses a data transmission method and device based on a QSPI interface. The method comprises the following steps: receiving serial communication data; analyzing the serial communication data to obtain a command word and an address; after the serial communication data is received, determining a transmission bit of data transmission according to the command word; transmitting a command word and an address to a system clock domain through asynchronous fifo; in a system clock domain, determining a transmission channel according to the command word and the address; when the transmission channel is a write channel, acquiring serial communication data through a system clock domain, and sending the serial communication data in the transmission channel according to the transmission bit; and when the transmission channel is the read channel, receiving data in the transmission channel according to the transmission bit. Accurate control of data is realized by transmitting command words and addresses to a system clock domain and distinguishing read-write channels. Data are sent and received through a system clock domain, the efficiency and reliability of data transmission are improved, and the requirement of a modern system for high-speed data interaction is met.

The invention discloses an SPI (Serial Peripheral Interface) slave controller and a working method thereof, the SPI slave controller comprises an SPI interface, an SPI sending shift register, an SPI receiving shift register and a system bus interface, the SPI slave controller is integrated on a chip, and the SPI slave controller further comprises a core control module, a sending asynchronous FIFO (First In First Out), a first DMA (Direct Memory Access) controller, a receiving asynchronous FIFO, a second DMA controller and a register module; according to the technical scheme provided by the invention, the SPI slave controller adopts a double-asynchronous FIFO (First In First Out) controller architecture matched with double DMA (Data Memory Access) controller architecture, the communication frequency is greatly improved in the flow, the fixed multiple relationship which must be met between a system clock and a serial communication clock in the traditional SPI design is broken, the higher communication rate is allowed to be supported under the lower system clock frequency, and the communication efficiency is improved. And the overall data transmission efficiency and the system throughput capacity are improved.

The application discloses a network-on-chip conversion interface for a DDR3 controller and belongs to the field of integrated circuit communication, and comprises an input end asynchronous bridge, an output end asynchronous bridge and a protocol conversion processing module; the input end asynchronous bridge receives a request packet from an input port of a network-on-chip, carries out data buffering and cross-clock domain processing based on an asynchronous FIFO, and outputs the request packet to the protocol conversion processing module; the output end asynchronous bridge receives a response packet and an acknowledgement packet output by the protocol conversion processing module, also carries out data buffering and cross-clock domain processing based on an asynchronous FIFO, and finally outputs to the network-on-chip through an output port; and the protocol conversion processing module as a whole realizes conversion of a data packet and an AXI bus signal. The application has a very important role in fast integration and expansion of storage devices such as DDR3, greatly shortens a development cycle and reduces development cost.

The application provides a DRAM read data timing calibration method and device, the method comprising: in a DRAM initialization stage, a DRAM controller writes specific data to a fixed address and issues a read instruction, receives a feedback data strobe signal and a data signal; delaying the data strobe signal, delaying the data strobe signal into a plurality of data strobe signals with different delay values and selecting output using a multiplexer; receiving the data signal using an asynchronous FIFO module, the multiplexer selecting output of the data strobe signal as a write clock signal of the asynchronous FIFO module; after receiving the data signal, the asynchronous FIFO module uses a DARM system clock signal as a read clock signal of the FIFO module, and outputs FIFO read data; comparing the FIFO read data with target data, and when the comparison result is inconsistent, adjusting a control signal of the multiplexer until the FIFO read data and the specific data are consistent in the comparison result.

The invention relates to a pseudo code clock synchronization method and system based on asynchronous FIFO (First In First Out) water level adaptive control, and belongs to the technical field of communication and satellite navigation digital receiving. In order to solve the problems that in the prior art, due to frequency deviation of a local clock and an external clock, overflow or null reading occurs during long-term operation of an asynchronous FIFO, and zero-static-error tracking cannot be achieved through open-loop control, the water level error of the asynchronous FIFO is monitored in real time, closed-loop negative feedback is formed by adopting a high-precision integer operation second-order loop filter in combination with deep smoothing post-processing, and therefore the water level error of the asynchronous FIFO is monitored in real time. And dynamically adjusting frequency control words of the in-controlled oscillator to enable the average rate of the pseudo code clock to accurately track the external data rate. Long-term stable synchronization with zero steady-state error is realized, the control process is smooth, the anti-interference capability is strong, all integer operations are easy to realize by hardware, and the system reliability and the engineering practicability are obviously improved.

The present application relates to a kind of digital phased array optical fiber data transmission methods in the field of phased array digital processing.The method frames data group in optical fiber transmission, digitalizes the problem of data deframing as geometric progression, realizes data group framing, data deframing with asynchronous FIFO, the FIFO depth needed is far less than data frame length, compared with ping-pong operation, can effectively reduce the demand of program to resource, it is favorable to the low-power design of digital receiving component, while it can improve the digital processing capacity of beam forming board card, improves the ability of digital multi-beam forming.

A command processing device includes an asynchronous first-in first-out (FIFO) unit, a mode configuration unit and a post processing unit. The asynchronous FIFO unit receives a plurality of commands from an external device, and stores the plurality of commands. The mode configuration unit sets a command processing scheme for each of the plurality of commands to one of a first processing scheme or a second processing scheme different from the first processing scheme and stores the command processing scheme for each of the plurality of commands. The post processing unit determines the command processing scheme for each of the plurality of commands based on the mode configuration unit, and generates a plurality of control signals by processing the plurality of commands based on an input sequence of the plurality of commands and the determined command processing scheme.

The invention provides a controller based on a PSRAM and a control method, the controller is applied to data interaction between an AHB bus and PSRAM particles, the controller comprises a data receiving unit, a first asynchronous FIFO unit, a PSRAM writing unit, a PSRAM reading unit and a second asynchronous FIFO unit; the data receiving unit is used for acquiring data from an external RAM (Random Access Memory) through an AHB (Advanced High-performance Bus) and storing the data into the first asynchronous FIFO unit; the first asynchronous FIFO unit is used for caching the data received by the data receiving unit; the PSRAM writing unit is used for timely taking out data of the first asynchronous FIFO unit according to the acquired signal and then storing the data into PSRAM particles in a parallel-to-serial mode; the PSRAM reading unit is used for timely taking out data in PSRAM particles according to the acquired signals and then storing the data in the second asynchronous FIFO unit in a serial-to-parallel mode; and the second asynchronous FIFO unit is used for caching data read from the PSRAM particles for external use. According to the controller, the occupation time of the AHB bus can be reduced, and the execution efficiency of the system is improved.

The invention provides an ADC / DAC interface data cross-clock domain processing system and method, and the system comprises an asynchronous FIFO which is used for transmitting data between a write clock domain and a read clock domain; and the control module is connected with the asynchronous FIFO and is used for controlling the write operation of the asynchronous FIFO when the system is started and starting the read operation of the asynchronous FIFO after detecting that the data volume stored in the asynchronous FIFO reaches a preset threshold value so as to realize cross-clock domain transmission of data. According to the system provided by the invention, through cooperation of the asynchronous FIFO and the control module, cross-clock-domain transmission is realized, data delay is controllable, and loss or repetition is avoided.