Rebuilt-up device for digital asynchronous clock

Abstract

This invention discloses a digital asynchronous clock reconstructing device composed of a digital signal input interface, digital signal output interface, an asynchronous FIFO storage, a non-volatile storage, a general processor, a first clock distributor, a second clock distributor, a first bandpass filter, a second bandpass filter, a digital frequency synthesizer and a high speed crystal oscillator, in which, the clock inputting digit signals is independent of the clock outputting digital signals, and an asynchronous buffer system is used to lag the output data behind the input data, so that, when short period of frequency or phase differences exists, the DDS is used to re-generate output clock to distribute chips to further improve qualities of the output clocks, a general processor is used to tune the output frequency of the DDS to eliminate long time of frequency difference between input and output digital signal clocks to avoid overflow of the asynchronous buffer or empty.

Description

technical field [0001] The present invention relates to an asynchronous clock reconstruction device, more particularly, to an asynchronous clock reconstruction device for eliminating digital signal clock jitter. Background technique [0002] During the processing and transmission of digital signals, additional clock jitter is often added. Although these clock jitters will not affect the correctness of data content, they can reduce the accuracy of digital-to-analog conversion. If the clock jitter is too serious, it may also cause the loss or dislocation of digital information in the communication process. Contents of the invention [0003] The object of the present invention is to provide a digital asynchronous clock rebuilding device, the device makes the clock of the input digital signal and the clock of the output digital signal independent of each other, and rebuilds a low-jitter asynchronous clock according to the digital signal and clock input externally, thereby real...

AI Technical Summary

Problems solved by technology

[0002] During the processing and transmission of digital signals, additional clock jitter is often added. Although these clock jitters will not affect the correctness of data content, they can reduce the accuracy of digital-to-analog conversion.

If the clock jitter is too serious, it may also cause the loss or dislocation of digital information in the communication process

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