This invention discloses a digital asynchronous clock reconstructing device composed of a digital signal input interface, digital signal output interface, an asynchronous FIFO storage, a non-volatile storage, a general processor, a first clock distributor, a second clock distributor, a first bandpass filter, a second bandpass filter, a digital frequency synthesizer and a high speed crystal oscillator, in which, the clock inputting digit signals is independent of the clock outputting digital signals, and an asynchronous buffer system is used to lag the output data behind the input data, so that, when short period of frequency or phase differences exists, the DDS is used to re-generate output clock to distribute chips to further improve qualities of the output clocks, a general processor is used to tune the output frequency of the DDS to eliminate long time of frequency difference between input and output digital signal clocks to avoid overflow of the asynchronous buffer or empty.