A video display system, such as useful in video surveillance applications, is disclosed. The system includes a video decoder (20) having a common output data port (27) at which it presents interleaved data streams (DSA, DSB). The interleaved data streams (DSA, DSB) may correspond to multiple scalings of a processed video input signal, for example as received from a surveillance camera (C1, C2, C3, C4). The video decoder (20) also outputs multiple clock signals (CLKA, CLKB), each of which are synchronous with a corresponding one of the interleaved data streams (DSA, DSB). This enables a common data port (27) to output multiple data streams (DSA, DSB), while individual destinations (30A, 30B) of the data streams (DSA, DSB) can continue to operate at legacy clock rates.