Universal calibration method for transmission path delay errors of parallel ADC sampling system

Abstract

The invention provides a universal calibration method for transmission path delay errors of a parallel ADC sampling system, and aims to provide a universal method capable of adapting to sampling frequency changes and correcting multichannel data input delay. According to the technical scheme, a clock and a signal are configured into multi-channel output through an AD chip integrated with M channels, and an AD is connected with an FPGA through a serial peripheral interface to form a high-speed variable sampling rate system. The AD performs multi-channel parallel sampling on high-speed signals to realize first-stage speed reduction, and the FPGA performs serial-parallel conversion by adopting serial-parallel conversion primitives or serial-parallel conversion IP cores to realize second-stagespeed reduction. After the FPGA configures an AD to send a test sequence, a calibration instruction and a state machine are started, a time delay parameter calibration algorithm is operated, time delay parameters are dynamically placed into an FPGA input time delay control primitive, all data lines in channels and among the channels are aligned, the AD exits from the test sequence to output actual signals, and system input time delay calibration is completed.

Description

technical field [0001] The invention relates to an alignment calibration method for multi-channel parallel data input delay of a high-speed variable sampling system composed of an ADC device with a high-speed parallel interface and an FPGA. [0002] technical background [0003] At present, modern electronic signals are characterized by complexity and diversity, especially the rapid growth of broadband and non-stationary characteristics. seam testing requirements. High-precision sampling has become the bottleneck of modern time-domain test instruments. The higher the sampling rate and sampling accuracy, the stronger the ability to restore the signal. In recent years, the ADC sampling rate has been greatly improved, but it is still difficult to balance high speed and high precision. This is limited by the current analog device manufacturing process. of. With the promotion of digital technology, higher and higher requirements are put forward for the sampling rate and samplin...

AI Technical Summary

Problems solved by technology

The disadvantages of this method are: first, the delay parameter cannot adapt to the change of sampling frequency. When the sampling frequency changes, the delay parameter will change accordingly and needs to be recalibrated; A set of parallel ADC sampling systems is not universal. Due to the differences in the ADC chips themselves due to process reasons, each set of sampling systems needs to be calibrated separately; third, as the ambient temperature changes, the delay parameters of the ADC chip need to be fine-tuned; fourth, every The inconsistency of delay parameters in a sampling system leads to difficulties in program version management, especially for high-speed parallel ADC sampling systems with variable frequencies. The larger the frequency range, the more delay parameter files need to be saved, and the corresponding hardware program versions are also more complex. Lots of work

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