56 results about "Test sequence" patented technology

This application relates to the field of power distribution system technology, and in particular to a testing method and system for substation measurement and control devices based on neural networks. The method includes: constructing a full-link signal topology map of the substation; extracting the correlation features of each signal node from various types of configuration files; inputting the full-link signal topology map and correlation features into a pre-trained graph neural network, which matches signal node pairs to obtain matching point pairs, and generating a test sequence consisting of simulated excitation signals and expected response information based on the matching point pairs; triggering the corresponding simulated excitation signal according to the test sequence, acquiring feedback signals in real time, comparing the feedback signals with the expected response information, and determining the test results. This application effectively reduces the manual burden of testing substation measurement and control devices and improves test accuracy.

This invention discloses a composite sequence forced and logical association control method, system, and electronic device for die-casting machines, relating to the field of die-casting machine testing technology. The invention collects multi-source operating data from the die-casting machine and, based on this data and pre-set process rules, determines the process state of the die-casting machine. It acquires a pre-stored forced test sequence and generates corresponding test instructions. The forced test sequence includes trigger conditions and forced steps arranged in a logical order. During the operation of the die-casting machine, it monitors in real time whether the trigger conditions are met. If met, the test instructions are executed according to the timing logic of the forced steps. Simultaneously, it continuously monitors the process state and die-casting machine safety parameters, and controls the interruption and reset of the test instructions based on the monitoring results. This method supports repeatable and safe simulation and verification of complex operating conditions or occasional faults, improving the testing efficiency of the die-casting machine control system.

The present application relates to the technical field of wafer testing. Provided are a wafer test data processing method and apparatus, and an electronic device and a medium. The method comprises: acquiring a test sequence consisting of test data of a plurality of dies on a target wafer; dividing the plurality of pieces of test data in the test sequence, so as to obtain a plurality of sub-sequences; converting the test data in the sub-sequences, so as to obtain target sub-sequences; and for the target sub-sequences that meet a deletion condition, deleting same in corresponding processing threads. In the present application, the problem of memory overflow in a conventional CS architecture when processing large-scale wafer test data is effectively solved by means of a BS architecture and a memory optimization technique; the processing efficiency and response speed of a system are improved by means of techniques such as data chunking, stream processing and asynchronous generation; and the stability and reliability of a system are enhanced by means of optimizing memory usage and data processing flows.

The present application relates to the technical field of equipment life cycle management, and specifically includes an aviation equipment full life cycle management method and system based on digital threads, the method comprising: acquiring process parameters of each stage, determining first digital thread master data and a first layer of associated test sequences, second digital thread master data and a second layer of associated test sequences, mapping the deviation of the physical equipment state and the virtual simulation state, and identifying the performance difference point under the cross-stage data correlation link; setting a management strategy for collaborative optimization. The technical problem of being unable to identify the cross-stage performance difference point equipment performance fluctuation root cause positioning in real time, causing the reliability of aviation equipment to be limited is solved, the first and second digital thread master data and the associated test sequences are constructed, the deviation of the physical equipment and the virtual simulation state is accurately mapped, the management strategy is set in combination with the double thread data and the performance difference point, and full life cycle collaborative optimization is performed, and the technical effect of effectively improving the equipment reliability is achieved.

An electronic circuit includes a target circuit, a CPU, a memory system, a test application system and a measurement system. The target circuit includes a plurality of debug access ports and N scan paths of components, each path passing through at least a part of the ports. The test application system is configured to generate a clock signal to implement an overclocking test sequence. The CPU is configured to apply at least one input vector to the paths, under a nominal and the overclocking test sequences delivering a nominal and a test output vectors. The measurement system is configured to perform a comparison operation between the test output vector and the nominal output vector stored in the memory system, and to deliver at least one comparative vector being a fault detecting signature of the electronic circuit.

An optical fiber link testing method and apparatus, and an optical fiber communication system, belonging to the technical field of communications. An optical transmitting device transmits a first optical signal to an optical receiving device by means of an optical fiber link, the first optical signal carrying a test sequence, the test sequence comprising a plurality of sub-test sequences, and the plurality of sub-test sequences being carried in the first optical signal in a multiplexed manner. The optical receiving device receives a second optical signal by means of the optical fiber link, the second optical signal comprising the first optical signal and a reflected optical signal. The optical receiving device demodulates the second optical signal to obtain the test sequence. The optical receiving device determines transmission performance of the optical fiber link on the basis of the test sequence obtained from the demodulation. In the present application, the existing optical transmitting devices and optical receiving devices in optical fiber communication systems are used to test the transmission performance of optical fiber links, such that the optical fiber links can be tested without deploying additional devices in the optical fiber links, achieving simple hardware implementation for testing optical fiber links and lower test costs.

This invention discloses a comprehensive testing system for an electric bicycle controller, belonging to the fields of power electronics and motor control technology. The system includes the following steps: performing an electrical self-test to verify the validity of the basic operating state; after passing the self-test, acquiring a preset automated test sequence to control and simulate various test conditions for the controller under test; while running the automated test sequence, constructing a virtual motor operating environment on the rotorless stator coils, and performing virtual reconstruction and dynamic compensation algorithms; wherein, the dynamic compensation algorithm includes the generation and injection of virtual back EMF, real-time compensation of nonlinear inductance, and electromechanical coupling dynamic reconstruction; this system integrates virtual back EMF injection technology in the test board, by calculating and compensating the instantaneous value of the back EMF corresponding to the simulated rotational speed in real time in the digital domain, embedding key speed and position information into the feedback loop of the controller under test.

This application relates to the field of integrated circuit technology and provides a physical IP verification device, verification method, computer equipment, and medium. The physical IP verification device includes: a first reusable multi-mode test sequence generator, a verification component physical interface, a second reusable multi-mode test sequence generator, and a verification component serial interface. This allows for the consideration of different simulation needs and scenarios, such as accelerating simulation efficiency and integrating verification. It supports protocol consistency verification, physical layer subsystem-level functional verification completeness, and standardized protocol verification. It provides a rich set of test vectors to meet the interfacing test scenarios and completeness verification needs of different layers, including the transaction layer, data link layer, and physical layer. It supports richly layered debugging interfaces and debugging methods, different physical interface versions and interface data bus widths, and also supports hierarchical and fine-grained low-power management.

This invention discloses an automatic testing device for air conditioners and an air conditioner. The former includes a communication module and a control processing module. The control processing module can communicate with the air conditioner through the communication module. Multiple first communication messages are preset, each including a data flag and data. The parsing capability of the data flag is determined by setting the bit value corresponding to the data. Each first communication message can control the air conditioner to operate in different modes or functions. The control processing module is configured to send each first communication message to the air conditioner in a test sequence. The air conditioner parses or discards the corresponding data based on the bit value of the data flag. This invention automates air conditioner testing by sequentially setting multiple first communication messages and controls data parsing and discarding by setting data flags in each first communication message with the same protocol format, thereby reducing testing difficulty and improving testing efficiency.

An electronic circuit (10) is proposed, comprising a target circuit (100), a CPU (200), a memory system (400), a test application system (300) and a measurement system (500). The target circuit comprises a plurality of debug access ports and N scan paths of components, each path passing through at least a portion of the ports. The test application system is configured to generate a clock signal (CLK) to implement an overclocking test sequence. The CPU is configured to apply at least one input vector (V in ) to the paths under a nominal test sequence and the overclocking test sequence, the nominal test sequence and the overclocking test sequence delivering a nominal output vector and a test output vector. The measurement system is configured to perform a comparison operation between the test output vector (V out ) and the nominal output vector (V out‑i ) stored in the memory system, and to deliver at least one comparison vector (V comp ) as a fault detection feature of the electronic circuit.

This invention relates to an air conditioner and its control method, belonging to the field of air conditioner technology. It includes an outdoor unit, an indoor unit, and a controller. The controller is configured to receive a test sequence generated based on test priority logic and control the air conditioner under test to sequentially execute multiple test items. The test priority logic includes acquiring test condition parameters, test energy consumption data, and risk correlation data; calculating the switching time when switching from the previous test item to the current test item to obtain an efficiency score; calculating the energy consumption score based on the test energy consumption data and the switching time; determining the risk score based on the risk correlation data; weighting the efficiency score, energy consumption score, and risk score, and combining them with a preset business value coefficient and a preset rectification correction coefficient to obtain a priority score; and sorting each test item according to the priority score to generate a test sequence. This achieves optimal sorting under multi-factor coupling, balancing failure cost and energy consumption cost.

The present application relates to the technical field of radio frequency automation test, and more particularly to a signal source test system and method based on a radio frequency switch matrix, comprising a calibration module, an analysis module, a correction module, a sending module, an acquisition module, a closed-loop calibration module and a determination module. The calibration module obtains matrix switching time consumption, signal source parameter adjustment time consumption and temperature aging coefficient and calculates a reference time delay difference; the analysis module generates path switching instructions and waveform characteristic adjustment parameters according to a test sequence; the correction module corrects the reference time delay difference using the current temperature and the cumulative number of actions to obtain a current time delay difference value; the sending module determines the instruction sending sequence and interval according to the time delay difference sign and sends in sequence; the acquisition module controls the signal analysis unit to perform data acquisition after the instruction sending is completed; the closed-loop calibration module corrects the waveform characteristic adjustment parameters according to the reflection coefficient deviation; and the determination module compares the test data with a preset index threshold and outputs a test conclusion.

This application discloses a testing method and apparatus for a vehicle high-voltage system. The method involves acquiring initial vehicle state information; determining whether the vehicle's high-voltage system meets preset test conditions based on the initial state information; if the high-voltage system meets the test conditions, performing step-by-step testing operations and generating corresponding test results; the step-by-step testing operations are used to sequentially test the control functions of key components of the vehicle's high-voltage system according to a preset test sequence. This application automates the high-precision control function testing of key components of the vehicle's high-voltage system, significantly reducing the risk of traction failure or shutdown due to high-voltage system malfunctions during vehicle operation, thereby comprehensively improving the reliability and safety of the entire vehicle.

The application provides an m sequence optimization method for a satellite-ground integrated sensing system test, comprising the following steps: step 1, reference sequence performance evaluation: the reference performance comprises a reference peak-to-average power ratio, a reference peak-to-side lobe ratio, a reference integrated side lobe ratio and a reference Doppler tolerance; step 2, comprehensive multi-dimensional cost function construction and mixed optimization strategy: step 201, constructing a comprehensive multi-dimensional cost function capable of weighted adjustment: step 202, defining a normalization function based on the reference performance: step 203, configuring the performance on demand based on the weight coefficient: step 204, minimizing the cost function by using a mixed optimization algorithm; and step 3, generating a final integrated sensing test sequence. The application realizes the collaborative optimization of multiple key performances of communication and sensing for the first time, and can generate a special sequence with excellent comprehensive performance, which can meet the stringent integrated satellite-ground sensing system test requirements.

This invention discloses a method, apparatus, device, and storage medium for implementing automated software testing, relating to the field of software testing technology. The method includes acquiring test tasks and sending them to a corresponding test management platform; parsing the test tasks and associating them with basic test cases in a test case library to form an automated test sequence for the corresponding test tasks; distributing the automated test sequence to automated test execution devices managed by the test management platform; executing test plans, performing test operations, obtaining test results, and generating test reports. This application employs distributed technology to construct an automated software test factory, building a data management system and multiple test management platforms to replace the central platform system, significantly improving the shortcomings of centralized solutions such as long construction cycles, high costs, poor scalability, and poor stability.

The application discloses a dynamic-priority-based relay protection automatic test sequence optimization method and system, and belongs to the technical field of power relay protection. n S1, test task modeling and parameterization; the test case to be executed is modeled into a task set, n the total number of tasks, and multi-dimensional feature parameters are defined for each task; S2, real-time monitoring of system resource state; in the test execution process, the resource state vector of the test platform is continuously acquired; S3, dynamic priority calculation and task selection; according to the current resource state and task parameters, the dynamic priority scores of the executable candidate set and each ready task are calculated, and the task with the highest score is selected for execution; S4, task execution and state updating; S5, loop iteration, steps S2 to S4 are repeated until all tasks are executed. By introducing the dynamic priority scheduling mechanism, the contradiction between the static preset of the test sequence and the dynamic change of the test resources is solved.

This invention provides an automated testing and interpretation system and method for the downlink radio frequency performance of regenerative processing payloads on communication satellites, including a hardware platform and a control unit. The hardware platform is used to construct a satellite-to-ground radio frequency link and supports remote control. The control unit carries main control software to control the hardware platform to perform the following functions: loading and executing predefined test sequences to initiate the test process; sending remote control commands to set the satellite payload status via power supply control equipment or requesting command permissions from the satellite platform; receiving and parsing satellite telemetry to confirm whether the status meets the requirements; remotely controlling general-purpose test instruments to perform automatic testing, acquiring test data, and automatically interpreting and recording it based on predefined templates; and automatically storing remote control commands, telemetry data, and test data in a time sequence to a database. Thus, this invention achieves one-click automated testing and interpretation of the downlink radio frequency performance of satellite processing payloads, improving efficiency, reducing cost and error rate, and possessing versatility and scalability.

The application relates to the technical field of semiconductor testing, and discloses a memory chip FT test method based on probe contact. The method comprises the following steps: acquiring wafer-level process parameters, layout and wiring topology and historical yield data of a chip; dividing a logic test block; calculating defect probability scores of each block and sorting to generate a test sequence; performing full-function testing in sequence, collecting response signal features in real time and comparing the response signal features with a health benchmark model, and dynamically triggering adjacent expansion testing or failure determination; and feeding back test results to update yield data. The application shortens the test time and reduces the test cost while guaranteeing the defect coverage rate through a risk-oriented adaptive test strategy.

A kind of satellite power quality automatic test system and method, first build including total control computer, test computer, oscilloscope, network switch automatic test system, utilize test computer to receive the instruction issued by total control, to oscilloscope relevant parameter configuration and test data reading, in total control, can arrange test sequence according to test demand, and carry out interpretation, and automatically generate test report, can complete satellite power quality automation test, improve test efficiency, reduce the uncertainty caused by manual operation, all operations are automatically completed by system, improve the accuracy of test.

The utility model relates to vehicle control ware test technical field, concretely is a kind of vehicle control ware FCT automation test device, contain automation test platform and multifunctional test system, automation test platform is realized controller automatic feeding and discharging by linear slide module group drive pneumatic fixture, adjustable test needle bed is compatible with different size controller interface, multifunctional test system integrates programmable power array analog storage battery fluctuation, high-precision acquisition module synchronous acquisition multichannel signal, multi-protocol communication unit resolves CAN FD / SENT data, load simulation and fault injection unit test driving ability and abnormal working condition. Host system executes test sequence by industrial computer, and scanning code gun is associated serial number and test data, realizes whole-process automation test. The equipment supports dynamic power test, signal synergy analysis and communication reliability verification, single-piece test time is not more than forty-five seconds, significantly improves test efficiency and quality consistency.

This application discloses a method, apparatus, electronic device, and storage medium for evaluating the performance of quantum operation gates. The method includes: inserting a delay of a target duration between adjacent Clifford gates in a quantum benchmark test sequence to obtain a first benchmark test sequence; determining a first incoherent error based on the quantum benchmark test sequence and the first benchmark test sequence; the target duration is n times the duration of a pulse operation gate rotating 90° around a target axis; inserting n pulse operation gates rotating 90° around a target axis between adjacent Clifford gates in a purity random benchmark test sequence to obtain a second benchmark test sequence; determining a second incoherent error based on the purity random benchmark test sequence and the second benchmark test sequence; using the difference between the second incoherent error and the first incoherent error as the target incoherent error; and evaluating the performance of the quantum operation gate based on the target incoherent error, thereby realizing the performance evaluation of microwave generating devices and microwave transmission links.

This application discloses an automated production scheduling method and apparatus for harmonic reducers, relating to the field of industrial control technology. The automated production scheduling method for harmonic reducers includes: acquiring a basic dataset for multi-station testing of the harmonic reducer; optimizing the test item set corresponding to the test samples to determine the target test sequence of the test samples and the target test time corresponding to the target test sequence; constructing an initial test scheduling scheme for multi-station testing based on the target test sequence and target test time; and solving the initial test scheduling scheme to obtain the target test scheduling scheme for the harmonic reducer. Because the test sequence of the test item set corresponding to the test samples is optimized, unnecessary station state switching waiting time is reduced; and by further solving the initial test scheduling scheme, the global optimality of the obtained solution is ensured, improving production efficiency and equipment utilization.

The application provides a CBTC automatic self-test method and device, the method comprising: obtaining a first test sequence based on an event graph, wherein the first test sequence comprises a correct complete event sequence and a fault complete event sequence; optimizing the first test sequence based on an event tree optimized test sequence optimization algorithm to obtain a second test sequence with lower redundancy; and testing the second test sequence based on a CBTC automatic test platform of an event-driven model to obtain a test result.

This invention provides an efficiency optimization method for the RUL prediction framework based on DDPG fusion AM, relating to the field of mechanical equipment life prediction. The method includes: generating continuous functional signal data using the FAR method; calculating the similarity between the current test sequence and historical data using an attention-weighted dynamic time warping algorithm, dynamically selecting the M most relevant historical data segments to construct a degradation training dataset; constructing an attention-enhanced CNN and LSTM parallel hybrid model, inputting the degradation training dataset into the model to extract equipment degradation features, and outputting initial RUL prediction values; using the performance evaluation index of the initial prediction values ​​and the current RUL prediction framework parameters as state inputs to the DDPG agent, outputting actions to adjust the RUL prediction framework parameters, and dynamically optimizing the size of the degradation training dataset and the length of the input time window of the parallel hybrid model. This invention achieves global optimization of RUL prediction accuracy and operational efficiency.

The application discloses an interface test method and device, a processor and electronic equipment. The method comprises the following steps: receiving an interface test request of a to-be-tested business process, determining a plurality of logical interfaces that need to be tested in the to-be-tested business process, and obtaining a parameter calling file; judging whether each logical interface has a parameter that needs to be called in the parameter calling file according to a test sequence of the to-be-tested business process; in the case that the parameter calling file has a parameter that needs to be called by the current logical interface, obtaining the parameter names of a plurality of parameters that need to be called by the current logical interface; reading a target parameter value in an associated file of the to-be-tested business process according to the parameter name, replacing the parameter value corresponding to the parameter name in the interface test request with the target parameter value; and performing interface test of the current logical interface according to the interface test request after the parameter value is updated. Through the application, the problem that a large number of parameters need to be defined as variables during interface test in the related art, resulting in low test efficiency, is solved.

The present application relates to the technical field of power equipment detection, and particularly relates to a flexible configuration signal protection substation automatic point-to-point test method and system, which constructs a digital twin closed loop simulation system and a standard information dictionary library; according to a signal mapping relationship in the standard information dictionary library, a standardized signal point defined in a minimum test item in a general test template library is associated with an actual equipment address in a mapping table, a standard signal point parameter in the general test template library is replaced with a specific communication address and an access path, the minimum test item after the parameter replacement is combined into an executable test sequence, and an executable test scheme for a specific project is output; actual response is compared with expected results, automatic point-to-point test is completed, and therefore rapid adaptation and full-automatic closed loop test of various signal protection substations are realized, debugging efficiency and data accuracy are significantly improved, and human intervention risk is reduced.

The present application relates to a kind of chip voltage drop detection method, system, equipment and storage medium, method includes: oscilloscope is initially configured, to make oscilloscope enter standby state;Voltage drop unit is sent to control instruction containing drop time parameter, to control switch module to carry out corresponding switch-off and conduction operation, to form voltage drop event in the chip to be measured in turn;Voltage waveform data recorded based on voltage drop event by oscilloscope is received;The voltage drop detection result of the chip to be measured is obtained according to voltage waveform data analysis;Based on the test sequence of pre-set, drop time parameter is updated, and returns to execute and sends control instruction containing drop time parameter to voltage drop unit.The present application constructs a low-cost, high-automated chip voltage drop detection solution, not only significantly reduces the cost of test equipment, but also improves the accuracy, consistency and efficiency of test by automation.

The application relates to a vehicle-mounted system test method, device, equipment, storage medium and program product. The method comprises the following steps: constructing at least two initial test cases for testing a vehicle-mounted system according to train operation data of the vehicle-mounted system configured by a heavy-haul train; selecting at least two target test cases from the initial test cases according to a dependency relationship between the initial test cases, and determining an initial test order between the target test cases; adjusting the initial test order according to a test case execution time required for executing the target test cases, so as to obtain a target test order between the target test cases; and sequentially calling the target test cases according to the target test order between the target test cases, so as to test the vehicle-mounted system of the heavy-haul train. The method can improve the efficiency and reliability of testing the vehicle-mounted system.

The application provides a short message service logic fuzzy testing and vulnerability mining method and system, relating to the technical field of software testing, wherein the method comprises: firstly, obtaining historical vulnerability information and first network interaction data to construct vulnerability knowledge graph and user session state data; then inputting the state data and the knowledge graph into a large language model, and guiding the generation of a test sequence through a reinforcement learning strategy; subsequently, executing the sequence in a test environment, synchronously collecting business responses and second network interaction data, updating the state data according to the second network interaction data and obtaining corresponding signaling state data; finally, comparing the first operation state in the response of the application to be tested with the second operation state in the signaling state data by using a differential testing algorithm, and determining that there is a logic vulnerability when the two are inconsistent. The application improves the mining capability of deep logic vulnerabilities of short message services.