151 results about "Test status" patented technology

The invention relates to a train wake-up test method and an implementation system, and the method comprises the steps: enabling DWUs at the head end and the tail end to achieve the power-on of a train through a double-end alternate wake-up mechanism according to a preset sequence after the DWUs at the head end and the tail end receive a wake-up command from an ATS and the state of the train meets a remote wake-up condition in a dormant state of the train; after the train is awakened and powered on, the vehicle-mounted controllers VOBCs at the head end and the tail end execute self-inspection, and the self-inspection state of the train is obtained through the TCMS; entering a static test stage after the self-inspection is passed, sequentially activating the vehicle-mounted controllers VOBCs at the head end and the tail end to be upgraded to a master system, enabling the vehicle-mounted controller VOBCs at the opposite end of the master system to be a slave system, and performing static test on the vehicle-mounted controller VOBCs of the master system; and when the VOBCs at the head end and the tail end serve as main systems to complete the static test and the test is passed, it is confirmed that awakening succeeds. Compared with the prior art, the reliability of the main-standby switching mechanism and the effectiveness of the whole redundancy architecture can be fully verified at the initial stage of starting of the vehicle-mounted operation control system.

The invention discloses a power line carrier communication chip test system and test method, and belongs to the technical field of electronics. The test system comprises a test platform configured to provide a test instruction used for indicating a test item; the accompanying test module comprises a processing unit and a first interface unit, a second interface unit and a third interface unit which are connected with the processing unit, the first interface unit is connected with the test platform, and the second interface unit and the third interface unit are connected with the chip to be tested; the third interface unit comprises a wireless test interface unit and / or a power line carrier test interface unit; wherein the processing unit is configured to receive a test instruction or feed back a test result through the first interface unit, control the to-be-tested chip to enter a target test state corresponding to the test item through the second interface unit according to the test instruction, and perform a data communication test through the third interface unit to obtain the test result. The configuration requirement for the test platform is reduced, the cost is reduced, and implementation is easy.

A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.

The invention discloses a mainboard function automatic detection method and device, and relates to the technical field of computer hardware detection. The method comprises: receiving a user instruction through a graphical interface to generate a test queue; distributing an independent thread for each test item to execute hardware detection, and dynamically mapping the position of a physical port; analyzing a test state in real time and updating interface feedback; comparing the actual hardware parameters with preset parameters; and hot update of the test script is supported. The device comprises a graphical interface module, a multi-thread execution engine, a scripted hardware detection module and the like. The mainboard function detection device can perform efficient, automatic and visual detection on the mainboard function, and is suitable for quality control of mainboard production, maintenance and research and development links.

The invention relates to an automatic test method and device for network card performance, a storage medium and electronic equipment, and relates to the technical field of automatic test.The method comprises the steps that a to-be-tested network card obtains a PXE bootstrap file from a PXE server based on the IP address of the PXE server, and executes the PXE bootstrap file to obtain a PXE bootstrap program so as to transfer the control right to the PXE bootstrap program; the PXE bootstrap program downloads the PXE configuration file; the PXE bootstrap program executes the operating system kernel file to obtain an operating kernel execution program, and transfers the control right to the operating kernel execution program to obtain test state information of the network card to be tested; and operating the kernel execution program to call an initialization script in the initialization memory file, and executing the initialization script to update test state identification information in a test state file in the PXE server according to the test state information, so that the PXE server determines the test state of the to-be-tested network card according to the updated test state identification information. The test efficiency is improved.

The invention provides an aircraft full-process collaborative design and assembly test system and method, which support rapid realization of collaborative design and assembly test control and analysis of an aircraft in each stage of a full life cycle, and establish an efficient and normative full-process collaborative design and assembly test system and method. Information integration of the whole life cycle is achieved through an information technology means, multi-user collaborative design and dynamic assembly test records of cross-specialty, cross-information-system and cross-regional systems in the development process are achieved, the development efficiency is improved, and design and assembly test state carding according to model requirements is supported. The method supports the selection of comparison data columns according to needs, obtains a more targeted result, and promotes the standardization and collaboration of the test process, improves the data reuse capability, enhances the interaction friendliness, and improves the efficiency through the classified display, the mastering of the data change trend, and the comprehensive and effective control of the assembly test data of each stage. Real-time operation and later-period management are based, and records are reserved according to the basis.

The invention relates to the technical field of chip function testing, and particularly discloses a multi-site testing method for TOF sensor chip function testing, which comprises the following steps: completing hardware self-inspection and software loading; the host receives a'ready 'signal fed back by the sorting machine / probe station through GPIB communication, and confirms that each slave and the corresponding peripheral are in a'to-be-tested' state through TCP communication or Pipe interaction; the host issues an independent test instruction to each slave; after each slave receives the instruction, the corresponding test resource board card is controlled to provide a test condition for the chip to be tested, and the chip output data is collected at the same time; after completing the single-station test, each slave uploads a test result to the host; the host captures the test data from the corresponding network disk and counts the yield; and the host sends the final result of the multi-station test to the sorting machine / probe station through the communication driver and automatically grabs the next batch of chips to be tested. According to the method, the overall test time is greatly shortened through the multi-site parallel test.

The invention belongs to the field of cross-application function automatic testing in mobile applications, and relates to a large model driven cross-application function testing method and system based on memory implantation. The method comprises the following steps: constructing a cross-application function knowledge base for storing and organizing complete information of historical cross-App tasks; searching a historical path most similar to the current test task from the cross-application function knowledge base, reconstructing the historical path into a dialogue memory format conforming to the natural interaction habit of the large language model, and implanting the large language model; and dynamically generating a test path matched with task semantics by utilizing a large language model according to an implanted dialogue memory format, and realizing test state monitoring and feedback correction in the whole process in combination with a local state sensing mechanism. According to the method, a cross-application function knowledge base is constructed, and a global + local memory implantation mechanism is designed, so that the model has a long-term memory ability and a real-time state sensing ability, and therefore, the model can stably run in a complex scene, and a test task can be efficiently completed.

The invention provides a plastic pipe service life test method and device, and the method comprises the steps: filling a low-level water tank and a circulation test pipeline communicated with the low-level water tank with a test solution, injecting the test solution into a high-level water tank communicated with the low-level water tank, and enabling the interior of the high-level water tank to have a preset test solution initial volume; wherein the high-level water tank is higher than the low-level water tank by a preset height, and a gas phase space is formed at the top of the high-level water tank; charging compressed gas into the gas-phase space to enable the gas-phase space of the high-level water tank to have preset pressure so as to apply back pressure to the test solution in the low-level water tank; under the back pressure condition, heating the test solution in the low-level water tank to a target test temperature; the backpressure condition and the target test temperature are maintained, and the service life of the plastic pipe sample in the circulation test pipeline is tested. Through the integrated structure and process design, the system is in a stable high-temperature and high-pressure test state, the energy utilization efficiency is improved, the operation cost is reduced, and the test efficiency is improved.

The application discloses a sample additional testing method, an additional system, a scheduling system and an analysis system. The method comprises the following steps: selecting a sample to be tested in an additional project and confirming the sample as an additional sample; judging a position state and a testing state of the additional sample; judging and obtaining a scheduling result according to the testing state and the position state of the additional sample; scheduling a sample rack where the additional sample is located to a corresponding track sample suction position according to the scheduling result; and testing the additional sample in the additional project. The application can effectively complete the operation of the additional project test according to different position states and testing states of the additional sample, and the user does not need to worry about invalid additional test caused by improper additional time, so that the user operation is more convenient.

The invention provides chip testing equipment and a testing method, and relates to the technical field of chip testing. At least one tested chip is placed on a first test platform deck, and the first test platform deck is set to be controlled to move in the front-back direction of the chip test equipment. The second test platform deck is arranged on the side, away from the first test platform deck, of the test machine, at least one tested chip is placed on the second test platform deck, and the second test platform deck is arranged to move in the front-back direction in a controlled mode. The first test platform deck and the second test platform deck are arranged to alternately move into the test machine, so that the test machine alternately performs functional test on the tested chips on the first test platform deck and the second test platform deck. According to the technical scheme, the first test platform deck and the second test platform deck alternately enter the test machine, so that the loading waiting time is shortened, the test machine alternately tests the tested chips on the first test platform deck and the second test platform deck and is always in a test state, and the test efficiency of the chips is improved.

The embodiment of the invention provides a chip test system and method and electronic equipment, and the system can comprise a test state judgment circuit which is connected with a plurality of cores and is used for obtaining test results outputted by the plurality of cores based on test data; based on a preset arrangement sequence of the plurality of kernels, comparing the test results of the two adjacent kernels to obtain a plurality of comparison results; the plurality of comparison results are used for determining abnormal conditions of the plurality of kernels; the abnormal condition can be judged by using the comparison results, the abnormal range can be quickly narrowed and the abnormal kernel can be positioned by combining the distribution of all the comparison results, and the whole process is completed by an internal circuit closed loop, is efficient and does not occupy extra port resources, so that the diagnosis efficiency is improved.

The invention belongs to the technical field of impeller detection, and provides an air floating type clamping tool and impeller dynamic balance testing device.The air floating type clamping tool comprises an outer fixing sleeve, a first air inlet connecting hole, a second air inlet connecting hole and a third air inlet connecting hole are formed in the outer fixing sleeve, and an inner mounting cylinder is fixedly mounted in the outer fixing sleeve; a wheel shaft sleeve is mounted in the inner mounting cylinder through an end cover and a locking pressing ring; an outer end face groove is formed in the side, away from the wheel shaft sleeve, of the end cover. The first air inlet connecting hole communicates with the outer end face groove through a first airflow channel. In a test state, the wheel shaft sleeve and the middle part of the wheel shaft of the impeller are encircled to form a middle cavity, and the second air inlet connecting hole is communicated with the middle cavity through a second airflow channel; a plurality of blowing holes are formed in the inner walls of the top and the bottom of the wheel shaft sleeve. The third air inlet connecting hole communicates with the blowing holes through a third airflow channel. According to the invention, the dynamic balance test precision of the impeller is higher, secondary damage possibly caused to the impeller in the test process is avoided, and the test efficiency of the impeller is greatly improved.

The invention relates to a four-point bending test method which comprises the following test steps: I, preparing a spare part, namely manufacturing a test sample piece which must be made of the same material as a composite material part on an airplane; iI, state inspection before testing: (1) vibration requirements, (2) electromagnetic requirements, (3) temperature and humidity requirements, and (4) setting of an upper clamp and a lower clamp of a testing machine; iII, loading a test sample; iV, testing the test sample piece, and driving the upper clamp to move downwards for loading, namely (1) preloading setting, (2) sample piece measurement and (3) loading setting in sequence; and V, comparing test results, and correcting the load and the deformation in consideration of the deviation between the actual size and the nominal size. The four-point bending test method has different test standards for aircraft shell parts of different types and specifications, data is corrected based on tested data set deviation, the data precision is improved, and then safe flight of an aircraft is guaranteed.

Insert (40) for a test contactor (1) for testing an electrically conductive test element (10), - wherein the insert (40) comprises several contact elements (8) which are designed to electrically contact the electrically conductive test element (10) in the test state of the test contactor (1), - wherein the insert (40) comprises a plurality of openings (67), wherein the openings (66) are arranged on an upper side of the insert (40) facing the test element (10) in the test state, - wherein in the test state at least one pin (68) is arranged in at least one opening (67) of the plurality of openings (67) such that the insert has a coding for a test element (10) corresponding to the coding.

The application discloses a passenger car four-channel chassis component durability test device and relates to the field of durability tests, which comprises a test frame main body, a tractor one installed at the bottom of the test frame main body, a tractor two installed at the left side of the test frame main body, a tractor three installed at the right side of the test frame main body and a control module installed on the front of the test frame main body, wherein the tractor one, the tractor two and the tractor three are used for fixing the tested components and conducting horizontal, vertical and torsional fatigue tests; a prediction model is constructed, the test state of a future period is predicted and obtained based on the test data of the current test project, the mapping relationship between the initial period damage state of the test component and the future period fission and deformation state is analyzed, and then the long-term test performance of the tested object can be quickly obtained through short-term actual tests.

The application discloses a memory test method and a test system. The memory test method is used for controlling the test state and test flow of each to-be-tested memory through at least two layers of loop control and read-write sequence operation. The at least two layers of loop control include: algorithm loop, each algorithm loop controls the execution of all algorithm steps of one to-be-tested memory, and the test flow of the corresponding to-be-tested memory is ended after the execution of all algorithm steps; address loop, the test address is traversed in the execution process of each algorithm step, each traversed address is executed the read-write sequence operation, and the address loop is ended after the traversal of the test address is completed. The application realizes algorithm atomization, so that the MBIST memory built-in self-test architecture can realize a more flexible test process.

The invention relates to a feed shaft precision retentivity test system and a test method thereof.The feed shaft precision retentivity test system comprises a test block, a loading device and a control device, the test block is used for being connected with a workbench of a feed shaft, the loading device comprises at least three loading pieces, and the control device is connected with the test block; the control device is used for controlling the three loading pieces to apply test force to the test block along a first direction, a second direction and a third direction which are perpendicular to one another, and controlling the workbench and the loading device to move along the first direction at the same speed. Wherein the first direction is the extension direction of the feeding shaft. The loading device can simulate the multi-axis vector load of the feed shaft under different working conditions by applying constant loading force in different directions of the workbench. Moreover, the control device ensures the synchronous follow-up of the loading module and the feed shaft to be tested, and the dynamic follow-up condition of the loading force of the feed shaft in the actual working condition is restored, so that the test state of the feed shaft better fits the actual working condition.

The invention relates to the technical field of diesel engine testing, and discloses a bench test diagnosis method, system and equipment for data acquisition, and the method comprises the steps: recognizing whether engine test equipment is available or not based on a flag bit of the selected equipment; if yes, judging whether the engine test equipment, the test environment and the test state meet validity diagnosis conditions or not; if yes, based on a preset data acquisition strategy, data acquisition work of the engine is controlled according to diagnosis signals of different engine bench tests; otherwise, displaying test interruption according to the instrument, and sending an alarm signal which does not meet the required factors to the user side. According to the scheme, data validity automatic diagnosis can be realized, data acquisition results are evaluated in real time, the validity of data acquisition is improved, and the effective utilization rate of resources and time is improved.

The invention discloses a method and a system for testing synchronous digital quantity injection of a regional stability control system based on network time synchronization, and the method is characterized in that the method comprises the following steps: S1, determining a test case needed by each control strategy function test of the stability control system according to the architecture and functions of the regional stability control system; s2, based on the test state sequence and the test input quantity determined by the test case, automatically generating a stability control system digital quantity injection test script matched with the test state sequence and the test input quantity; s3, through a network time synchronization mechanism, it is ensured that clock references of the test computer systems of all the sites are consistent, triggering time marks of test cases are set in a unified mode, and generated test case scripts are distributed to stability control devices of all the sites; and S4, analyzing the received test case script by the stability control device of each station, and extracting a test state sequence and characteristic parameters related to the station device.

The invention relates to the technical field of automobile safety, in particular to an intelligent chassis automatic testing method and system based on an NI platform. The method comprises the following steps: a test preparation step: importing an intelligent chassis VeriStand project, and obtaining a project identifier; configuring a test case, wherein the test case comprises a signal input parameter and a verification rule; the method comprises the following steps: a sequence automatic generation step, a step of reading test case data, a step of converting signal input into TestStand, a test step of converting a verification rule into TestStand and a test step of assembling and generating a test sequence; a test execution step: starting a test sequence through TestStand, calling VeriStand to load the chassis model and executing a test, and obtaining a test state in real time for monitoring; and a result processing step: generating and filing a test data file after the test is completed. According to the technical scheme, the compatibility and efficiency of chassis testing can be improved.

The utility model discloses a combined sealing gasket service life testing device which comprises a testing device body, an opening and closing door is arranged on the testing device body through an opening and closing opening, observation glass is arranged on the opening and closing door, a transverse screw is arranged on the back face of the opening and closing door through two installation blocks and a driving motor, and the transverse screw is connected with the testing device body. A horizontal screw rod is arranged on the base, a scraping plate is arranged on the horizontal screw rod in a threaded and sleeving manner, a spraying plate and a functional box are arranged on the scraping plate, a rotating chamber and a movable chamber are arranged in the functional box, a vertical screw rod extending to the outside of the functional box is rotationally arranged in the rotating chamber, and the vertical screw rod is connected with an opening and closing door through a rotating mechanism. According to the utility model, the cleaning assembly is arranged, so that when the glass is blocked by sundries and the sight is influenced, the device can automatically clean the glass, the continuity and definition of observation are ensured, and an operator can timely master the test state of the sealing gasket.

1. The name of the design product: factory quality test area data dashboard graphical user interface for electronic equipment. 2. The use of the design product: an electronic device. 3. The design points of the design product: the graphical user interface content in the screen. 4. The picture or photo that best indicates the design points: front view. 5. The use of the graphical user interface: to display the dashboard of the digital smart factory quality test area data, and to view the quality test status in real time. 6. The human-computer interaction mode of the graphical user interface: the front view is the initial interface of the operating system, the left side of the front view displays the options of different shelves, the right side of the front view displays the charging pile related information on the currently selected shelf, and the above data is updated in real time; clicking on any charging pile option in the right front view will enter the interface change state diagram.

The invention relates to the technical field of ATC testing, in particular to an ATC parallel testing method and system based on use case driving and a medium, and the method comprises the steps that on the basis of a preset to-be-distributed sequence, use cases corresponding to the number of testing environments are distributed to the testing environments, ATC testing is started to be executed, and the preset to-be-distributed sequence is determined on the basis of association attributes of the use cases; monitoring the test states of the plurality of test environments, and when monitoring that a single test environment ends the test, releasing the test environment which ends the test as an idle state; when the to-be-executed use cases exist, the to-be-executed use cases are distributed to the test environment in the idle state based on the preset to-be-distributed sequence, and the ATC test is continuously executed; and when the to-be-executed use case does not exist, completing the ATC test. Through an automatic distribution mechanism of the test cases, parallel test of the cases in different test environments at the same time is realized, and the overall test efficiency is effectively improved.

The invention discloses a state switching test method, device and system, electronic equipment and a storage medium, and relates to the technical field of software test.The main technical scheme includes the steps that when it is determined that the software state of a test execution end is switched to a to-be-tested state, a first target test case is sent to the test execution end; when it is determined that the first target test case completes the test, a first control instruction for switching the software state to the to-be-tested state is sent to a test execution end, so that the test execution end switches the software state to the to-be-tested state based on the first control instruction; when it is determined that the software state is switched to the to-be-tested state, sending a second target test case to the test execution end until each test case in the test case set is tested; the second target test case is any test case except the first target test case in the test case set. Compared with the prior art, the embodiment of the invention realizes the comprehensive coverage of the switching scene of the software state.

The invention provides a comprehensive testing method and device for an agricultural machine microcontroller and a storage medium, and relates to the technical field of microcontroller testing. The method comprises the steps of firstly building a bidirectional data transmission link with a microcontroller to be tested, then converting a user test demand into a corresponding test instruction, issuing the test instruction, collecting original test data after a test is executed, carrying out standardization processing on the original data, evaluating a test state, if a result is abnormal, creating a correction response flow according to an abnormal type, and if the result is abnormal, completing the test. Re-establishing a link or evaluating to obtain a new result; according to the invention, automation and integration of the whole testing process are realized through a closed-loop process, a splitting link is not needed, manual equipment switching is not needed, comprehensive testing is completed in a one-stop manner, operation is greatly simplified, and efficiency is improved; the abnormality correction mechanism can optimize the process automatically, avoids test interruption, guarantees test continuity and reliability, and provides an efficient and stable solution for factory detection and regular maintenance of the agricultural machine microcontroller.

A set of software criteria including a condition that a software test be successfully performed prior to deploying a software package to a user device and location information indicating a storage location for status information of the software test is obtained. A testing status of the software package is analyzed using the status information at the storage location and software package is deployed to the user device as a result of the testing status confirming that the condition has been met in response to a request to deploy the software package to the user device.

The application discloses a kind of test system and method for analog switch, it is related to electrical performance test technical field, including test control unit, coordinate each module work, parse instruction generation control signal, monitor test state and output result;Analog switch unit, adapt to multiple types of switch, can set on-off frequency and other key parameters restore working characteristic;Signal generation unit, generate a variety of adjustable electrical signal to meet different test requirements;Data acquisition unit, collect on-off response time and other electrical parameters;Fault injection unit, simulate a variety of common fault scenarios;Data analysis unit, process raw data to evaluate switch performance;Communication interaction unit, interact with external equipment data reception configuration instruction.The application adapts to multiple types of switch, test precision is high and anti-interference ability is strong, supports multi-environment test;Improve test efficiency and data reliability, adapt to electronic manufacturing, power operation and other multi-field applications.

The invention provides a multi-power domain chip timing sequence adaptive test system and test method, the system comprises a plurality of timing sequence test devices, each timing sequence test device is connected with a GPU chip, the models of all GPU chips are the same, and each timing sequence test device comprises a timing sequence control module, a timing sequence detection module and a result analysis module. A test scheme of the time sequence test device is formulated according to the test states of the time sequence test device and other simultaneous test time sequence test devices, and a plurality of time sequence test devices are adopted to test the GPU chip at the same time, so that the time sequence test efficiency of the multi-power-domain GPU chip is improved; during testing, the power-on sequence and the rising time delay of the time sequence of the multi-power-domain GPU chip are evaluated, and time sequence parameters of the GPU chip are analyzed more comprehensively; and testing is carried out in a normal working state of the GPU chip, so that the time sequence parameters of the chip in an actual application scene are reflected more accurately.

The present invention is applicable to the field of chip fault recovery technology and provides a dual-core lockstep processor fault recovery device and method. Before recovering from a processor fault, the present invention performs a self-test on the relevant system components required for processor operation. The specific self-test content is configurable and includes chip component self-test, processor self-test, software self-test, etc. Based on the self-test status, abnormal parameters or states are selectively restored to ensure that the current software and hardware states allow system rollback operations. This eliminates the need for multiple recovery points or a full reset to ensure recovery, thereby ensuring the reliability of fault recovery.