100 results about "Test status" patented technology

A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.

The invention discloses a mainboard function automatic detection method and device, and relates to the technical field of computer hardware detection. The method comprises: receiving a user instruction through a graphical interface to generate a test queue; distributing an independent thread for each test item to execute hardware detection, and dynamically mapping the position of a physical port; analyzing a test state in real time and updating interface feedback; comparing the actual hardware parameters with preset parameters; and hot update of the test script is supported. The device comprises a graphical interface module, a multi-thread execution engine, a scripted hardware detection module and the like. The mainboard function detection device can perform efficient, automatic and visual detection on the mainboard function, and is suitable for quality control of mainboard production, maintenance and research and development links.

The invention relates to an automatic test method and device for network card performance, a storage medium and electronic equipment, and relates to the technical field of automatic test.The method comprises the steps that a to-be-tested network card obtains a PXE bootstrap file from a PXE server based on the IP address of the PXE server, and executes the PXE bootstrap file to obtain a PXE bootstrap program so as to transfer the control right to the PXE bootstrap program; the PXE bootstrap program downloads the PXE configuration file; the PXE bootstrap program executes the operating system kernel file to obtain an operating kernel execution program, and transfers the control right to the operating kernel execution program to obtain test state information of the network card to be tested; and operating the kernel execution program to call an initialization script in the initialization memory file, and executing the initialization script to update test state identification information in a test state file in the PXE server according to the test state information, so that the PXE server determines the test state of the to-be-tested network card according to the updated test state identification information. The test efficiency is improved.

The invention relates to the technical field of chip function testing, and particularly discloses a multi-site testing method for TOF sensor chip function testing, which comprises the following steps: completing hardware self-inspection and software loading; the host receives a'ready 'signal fed back by the sorting machine / probe station through GPIB communication, and confirms that each slave and the corresponding peripheral are in a'to-be-tested' state through TCP communication or Pipe interaction; the host issues an independent test instruction to each slave; after each slave receives the instruction, the corresponding test resource board card is controlled to provide a test condition for the chip to be tested, and the chip output data is collected at the same time; after completing the single-station test, each slave uploads a test result to the host; the host captures the test data from the corresponding network disk and counts the yield; and the host sends the final result of the multi-station test to the sorting machine / probe station through the communication driver and automatically grabs the next batch of chips to be tested. According to the method, the overall test time is greatly shortened through the multi-site parallel test.

The invention provides a plastic pipe service life test method and device, and the method comprises the steps: filling a low-level water tank and a circulation test pipeline communicated with the low-level water tank with a test solution, injecting the test solution into a high-level water tank communicated with the low-level water tank, and enabling the interior of the high-level water tank to have a preset test solution initial volume; wherein the high-level water tank is higher than the low-level water tank by a preset height, and a gas phase space is formed at the top of the high-level water tank; charging compressed gas into the gas-phase space to enable the gas-phase space of the high-level water tank to have preset pressure so as to apply back pressure to the test solution in the low-level water tank; under the back pressure condition, heating the test solution in the low-level water tank to a target test temperature; the backpressure condition and the target test temperature are maintained, and the service life of the plastic pipe sample in the circulation test pipeline is tested. Through the integrated structure and process design, the system is in a stable high-temperature and high-pressure test state, the energy utilization efficiency is improved, the operation cost is reduced, and the test efficiency is improved.

The application discloses a sample additional testing method, an additional system, a scheduling system and an analysis system. The method comprises the following steps: selecting a sample to be tested in an additional project and confirming the sample as an additional sample; judging a position state and a testing state of the additional sample; judging and obtaining a scheduling result according to the testing state and the position state of the additional sample; scheduling a sample rack where the additional sample is located to a corresponding track sample suction position according to the scheduling result; and testing the additional sample in the additional project. The application can effectively complete the operation of the additional project test according to different position states and testing states of the additional sample, and the user does not need to worry about invalid additional test caused by improper additional time, so that the user operation is more convenient.

The invention provides chip testing equipment and a testing method, and relates to the technical field of chip testing. At least one tested chip is placed on a first test platform deck, and the first test platform deck is set to be controlled to move in the front-back direction of the chip test equipment. The second test platform deck is arranged on the side, away from the first test platform deck, of the test machine, at least one tested chip is placed on the second test platform deck, and the second test platform deck is arranged to move in the front-back direction in a controlled mode. The first test platform deck and the second test platform deck are arranged to alternately move into the test machine, so that the test machine alternately performs functional test on the tested chips on the first test platform deck and the second test platform deck. According to the technical scheme, the first test platform deck and the second test platform deck alternately enter the test machine, so that the loading waiting time is shortened, the test machine alternately tests the tested chips on the first test platform deck and the second test platform deck and is always in a test state, and the test efficiency of the chips is improved.

The embodiment of the invention provides a chip test system and method and electronic equipment, and the system can comprise a test state judgment circuit which is connected with a plurality of cores and is used for obtaining test results outputted by the plurality of cores based on test data; based on a preset arrangement sequence of the plurality of kernels, comparing the test results of the two adjacent kernels to obtain a plurality of comparison results; the plurality of comparison results are used for determining abnormal conditions of the plurality of kernels; the abnormal condition can be judged by using the comparison results, the abnormal range can be quickly narrowed and the abnormal kernel can be positioned by combining the distribution of all the comparison results, and the whole process is completed by an internal circuit closed loop, is efficient and does not occupy extra port resources, so that the diagnosis efficiency is improved.

The invention belongs to the technical field of impeller detection, and provides an air floating type clamping tool and impeller dynamic balance testing device.The air floating type clamping tool comprises an outer fixing sleeve, a first air inlet connecting hole, a second air inlet connecting hole and a third air inlet connecting hole are formed in the outer fixing sleeve, and an inner mounting cylinder is fixedly mounted in the outer fixing sleeve; a wheel shaft sleeve is mounted in the inner mounting cylinder through an end cover and a locking pressing ring; an outer end face groove is formed in the side, away from the wheel shaft sleeve, of the end cover. The first air inlet connecting hole communicates with the outer end face groove through a first airflow channel. In a test state, the wheel shaft sleeve and the middle part of the wheel shaft of the impeller are encircled to form a middle cavity, and the second air inlet connecting hole is communicated with the middle cavity through a second airflow channel; a plurality of blowing holes are formed in the inner walls of the top and the bottom of the wheel shaft sleeve. The third air inlet connecting hole communicates with the blowing holes through a third airflow channel. According to the invention, the dynamic balance test precision of the impeller is higher, secondary damage possibly caused to the impeller in the test process is avoided, and the test efficiency of the impeller is greatly improved.

Insert (40) for a test contactor (1) for testing an electrically conductive test element (10), - wherein the insert (40) comprises several contact elements (8) which are designed to electrically contact the electrically conductive test element (10) in the test state of the test contactor (1), - wherein the insert (40) comprises a plurality of openings (67), wherein the openings (66) are arranged on an upper side of the insert (40) facing the test element (10) in the test state, - wherein in the test state at least one pin (68) is arranged in at least one opening (67) of the plurality of openings (67) such that the insert has a coding for a test element (10) corresponding to the coding.

The invention relates to a feed shaft precision retentivity test system and a test method thereof.The feed shaft precision retentivity test system comprises a test block, a loading device and a control device, the test block is used for being connected with a workbench of a feed shaft, the loading device comprises at least three loading pieces, and the control device is connected with the test block; the control device is used for controlling the three loading pieces to apply test force to the test block along a first direction, a second direction and a third direction which are perpendicular to one another, and controlling the workbench and the loading device to move along the first direction at the same speed. Wherein the first direction is the extension direction of the feeding shaft. The loading device can simulate the multi-axis vector load of the feed shaft under different working conditions by applying constant loading force in different directions of the workbench. Moreover, the control device ensures the synchronous follow-up of the loading module and the feed shaft to be tested, and the dynamic follow-up condition of the loading force of the feed shaft in the actual working condition is restored, so that the test state of the feed shaft better fits the actual working condition.

The invention relates to the technical field of automobile safety, in particular to an intelligent chassis automatic testing method and system based on an NI platform. The method comprises the following steps: a test preparation step: importing an intelligent chassis VeriStand project, and obtaining a project identifier; configuring a test case, wherein the test case comprises a signal input parameter and a verification rule; the method comprises the following steps: a sequence automatic generation step, a step of reading test case data, a step of converting signal input into TestStand, a test step of converting a verification rule into TestStand and a test step of assembling and generating a test sequence; a test execution step: starting a test sequence through TestStand, calling VeriStand to load the chassis model and executing a test, and obtaining a test state in real time for monitoring; and a result processing step: generating and filing a test data file after the test is completed. According to the technical scheme, the compatibility and efficiency of chassis testing can be improved.

The utility model discloses a combined sealing gasket service life testing device which comprises a testing device body, an opening and closing door is arranged on the testing device body through an opening and closing opening, observation glass is arranged on the opening and closing door, a transverse screw is arranged on the back face of the opening and closing door through two installation blocks and a driving motor, and the transverse screw is connected with the testing device body. A horizontal screw rod is arranged on the base, a scraping plate is arranged on the horizontal screw rod in a threaded and sleeving manner, a spraying plate and a functional box are arranged on the scraping plate, a rotating chamber and a movable chamber are arranged in the functional box, a vertical screw rod extending to the outside of the functional box is rotationally arranged in the rotating chamber, and the vertical screw rod is connected with an opening and closing door through a rotating mechanism. According to the utility model, the cleaning assembly is arranged, so that when the glass is blocked by sundries and the sight is influenced, the device can automatically clean the glass, the continuity and definition of observation are ensured, and an operator can timely master the test state of the sealing gasket.

1. The name of the design product: factory quality test area data dashboard graphical user interface for electronic equipment. 2. The use of the design product: an electronic device. 3. The design points of the design product: the graphical user interface content in the screen. 4. The picture or photo that best indicates the design points: front view. 5. The use of the graphical user interface: to display the dashboard of the digital smart factory quality test area data, and to view the quality test status in real time. 6. The human-computer interaction mode of the graphical user interface: the front view is the initial interface of the operating system, the left side of the front view displays the options of different shelves, the right side of the front view displays the charging pile related information on the currently selected shelf, and the above data is updated in real time; clicking on any charging pile option in the right front view will enter the interface change state diagram.

The invention relates to the technical field of ATC testing, in particular to an ATC parallel testing method and system based on use case driving and a medium, and the method comprises the steps that on the basis of a preset to-be-distributed sequence, use cases corresponding to the number of testing environments are distributed to the testing environments, ATC testing is started to be executed, and the preset to-be-distributed sequence is determined on the basis of association attributes of the use cases; monitoring the test states of the plurality of test environments, and when monitoring that a single test environment ends the test, releasing the test environment which ends the test as an idle state; when the to-be-executed use cases exist, the to-be-executed use cases are distributed to the test environment in the idle state based on the preset to-be-distributed sequence, and the ATC test is continuously executed; and when the to-be-executed use case does not exist, completing the ATC test. Through an automatic distribution mechanism of the test cases, parallel test of the cases in different test environments at the same time is realized, and the overall test efficiency is effectively improved.

The invention provides a comprehensive testing method and device for an agricultural machine microcontroller and a storage medium, and relates to the technical field of microcontroller testing. The method comprises the steps of firstly building a bidirectional data transmission link with a microcontroller to be tested, then converting a user test demand into a corresponding test instruction, issuing the test instruction, collecting original test data after a test is executed, carrying out standardization processing on the original data, evaluating a test state, if a result is abnormal, creating a correction response flow according to an abnormal type, and if the result is abnormal, completing the test. Re-establishing a link or evaluating to obtain a new result; according to the invention, automation and integration of the whole testing process are realized through a closed-loop process, a splitting link is not needed, manual equipment switching is not needed, comprehensive testing is completed in a one-stop manner, operation is greatly simplified, and efficiency is improved; the abnormality correction mechanism can optimize the process automatically, avoids test interruption, guarantees test continuity and reliability, and provides an efficient and stable solution for factory detection and regular maintenance of the agricultural machine microcontroller.

A set of software criteria including a condition that a software test be successfully performed prior to deploying a software package to a user device and location information indicating a storage location for status information of the software test is obtained. A testing status of the software package is analyzed using the status information at the storage location and software package is deployed to the user device as a result of the testing status confirming that the condition has been met in response to a request to deploy the software package to the user device.

The application discloses a kind of test system and method for analog switch, it is related to electrical performance test technical field, including test control unit, coordinate each module work, parse instruction generation control signal, monitor test state and output result;Analog switch unit, adapt to multiple types of switch, can set on-off frequency and other key parameters restore working characteristic;Signal generation unit, generate a variety of adjustable electrical signal to meet different test requirements;Data acquisition unit, collect on-off response time and other electrical parameters;Fault injection unit, simulate a variety of common fault scenarios;Data analysis unit, process raw data to evaluate switch performance;Communication interaction unit, interact with external equipment data reception configuration instruction.The application adapts to multiple types of switch, test precision is high and anti-interference ability is strong, supports multi-environment test;Improve test efficiency and data reliability, adapt to electronic manufacturing, power operation and other multi-field applications.

The invention provides a multi-power domain chip timing sequence adaptive test system and test method, the system comprises a plurality of timing sequence test devices, each timing sequence test device is connected with a GPU chip, the models of all GPU chips are the same, and each timing sequence test device comprises a timing sequence control module, a timing sequence detection module and a result analysis module. A test scheme of the time sequence test device is formulated according to the test states of the time sequence test device and other simultaneous test time sequence test devices, and a plurality of time sequence test devices are adopted to test the GPU chip at the same time, so that the time sequence test efficiency of the multi-power-domain GPU chip is improved; during testing, the power-on sequence and the rising time delay of the time sequence of the multi-power-domain GPU chip are evaluated, and time sequence parameters of the GPU chip are analyzed more comprehensively; and testing is carried out in a normal working state of the GPU chip, so that the time sequence parameters of the chip in an actual application scene are reflected more accurately.

A system of digitally representing equipment failure comprising: a testing assembly for testing a component of a manufacturing equipment wherein the component includes a defect in a critical area included in the component; a sensor in communications with the testing assembly for sensing a failure state of the component, a set of computer readable instructions adapted for: receiving a critical failure mode associated with the component, receiving a testing dataset from the sensor representing testing results produced by the testing assembly wherein the testing dataset includes initial data representing an undamaged component and a failure dataset representing a failed component, isolating a set of failure data representing a testing status of the component from initial testing to failure of the component determined by the critical failure mode, creating a usable lifetime model of the component according to the set of failure data.

This utility model belongs to the technical field of solid-state drive (SSD) test benches and discloses an adjustable SSD test bench, including a support frame. A fixed shell is connected to the surface of the support frame, and a drive source is connected to the inner bottom of the fixed shell. A transmission component and a support component are respectively arranged on the fixed shell. This utility model uses the shape characteristics of a half-gear to drive the adapter rod and the test circuit board body to rotate in a half-turn trajectory, which facilitates the sequential rotation of test slots in different positions to the operator. This eliminates the need for the operator to move around to insert SSDs or to stretch out their arms and body for a long time to insert SSDs. Furthermore, the multiple test slots allow for simultaneous testing of multiple SSDs, improving the efficiency of SSD testing. The test status display screen, which is electrically connected to the test circuit board body, facilitates the display of SSD insertion results. If a failure occurs, its location can be displayed in time, improving the accuracy of SSD testing.

The application provides a hardware test method, device, equipment and storage medium. The method comprises the following steps: dividing a test graph into at least two sub test graphs, wherein each sub test graph comprises a×b regions, a and b are both integers equal to or greater than 2; generating a sub graph state array, wherein the sub graph state array is used for recording the test state of the regions in the sub test graph; performing the following processing on one or more sub test graphs in the at least two sub test graphs respectively to obtain a test result graph corresponding to the hardware to be tested: determining a target region from the sub test graph according to the sub graph state array; testing the hardware to be tested according to the test parameters corresponding to the target region, obtaining a test result, and updating the sub graph state array; performing filling processing on the target region of the test graph according to the test result; and initializing the sub graph state array after completing the test on each target region in the sub test graph. The method reduces the memory requirement during the test by reusing the sub graph state array.

The invention provides a vehicle registration method, system, equipment and product in a research and development test stage, and relates to the technical field of vehicle registration, and the method avoids the tedious and error of manual input by automatically reading a test state code and hardware information in a vehicle engineering mode; by verifying the integrity and legality of the registration information, it is ensured that only compliant research and development test vehicles can complete registration, and the safety and reliability of the system are enhanced; meanwhile, registration result information comprises registration records, vehicle information tables and associated test case numbers, automatic generation and structured storage can be achieved, centralized management and traceability of data are achieved, finally, results are pushed to users in real time through the front end, the response time is greatly shortened, and the user experience is improved. The problems that a traditional manual registration mode is low in efficiency, prone to making mistakes and difficult in collaboration are effectively solved, and efficient and intelligent technical support is provided for the research and development test process.

The invention discloses a chip test method and device and a storage medium, and the method comprises the steps: controlling a target port to enter a test state when a test for the target port is started; after the target port enters the test state, waiting for a first preset time, and not processing data from the target port within the time; after the first preset time, starting to analyze the data from the target port to detect a preset effective state character; and when the effective state character is detected, sending a chip test instruction to a corresponding lower computer through the target port, and receiving test data fed back by the lower computer. According to the method, invalid data at the initial stage of power-on are effectively filtered by introducing a waiting mechanism, the problems of test false triggering and low efficiency caused by immediate data analysis in the prior art are solved, and the test reliability and the system resource utilization rate are remarkably improved.

This application discloses a chip batch testing method, system, electronic device, and storage medium, relating to the field of chip testing technology. The method includes: generating a test list comprising multi-level test tasks; responding to a test start command, performing continuity testing on the chips under test to obtain the continuity testing results for each chip; identifying the chips under test with successful continuity testing results as the first test object; performing parallel, step-by-step testing on the first test object based on execution priority and each level of test task to obtain the task test status corresponding to each level of test task; and generating a color chart of the test status for each obtained task test status. This method enables efficient and comprehensive chip testing of batches of chips under test, and provides visualized monitoring and management during the chip testing process.

The invention provides a nuclear power DCS picture automatic testing method and device based on a communication protocol, and relates to the field of nuclear power DCS testing. The method comprises the following steps: loading a test case; various template XML files used for nuclear power DCS picture automatic testing are loaded; starting a nuclear power DCS picture test through the first specified instruction; in the test state of the nuclear power DCS picture, executing the test case, and calling a pre-established picture test interface to obtain state data of the dynamic object; wherein the state data of the dynamic object of the picture test interface is packaged through a preset communication protocol; and analyzing the obtained state data of the dynamic object according to a preset communication protocol, comparing an analysis result with a required state of the test case, and generating a test report. It can be seen that automatic testing is achieved on the basis of the two-layer picture testing interface, manual testing or testing based on image recognition is replaced, and the problems that manual operation is complex and the image recognition rate is low are solved.

The embodiment of the invention provides a board card test system, a test method and computing equipment. Comprising a to-be-tested board card which comprises a first programmable logic controller, and the first programmable logic controller is provided with a first pin; the first programmable logic controller comprises a plurality of second pins, and after the first programmable logic controller enters a test state, the plurality of second pins are used for sending a test code stream; the test code stream is used for determining a to-be-tested signal path after entering a test state; the test card is connected with the to-be-tested board card and comprises a second programmable logic controller, and the second programmable logic controller is used for receiving the test code stream, determining a to-be-tested signal channel based on the test code stream, executing test operation on the to-be-tested signal channel, collecting signal level changes on the to-be-tested signal channel and sending the signal level changes to the to-be-tested board card. Therefore, whether the to-be-detected signal channel is normal is determined. In the unified test state, the to-be-tested signal path is detected, so that the test efficiency can be effectively improved.

The invention relates to the technical field of vehicle-mounted electronic testing, in particular to a test control method and device for a vehicle-mounted chip and a storage medium, and the method comprises the following steps: S1, obtaining a group of dynamic environment parameters synchronously changing along with time from a preset vehicle-mounted environment database; s2, generating a composite test instruction; s3, sending the composite test instruction to an environmental parameter simulator and a power supply module, and enabling the to-be-tested vehicle-mounted chip to enter a composite stress test state; s4, comparing the output response signal with a pre-stored expected response signal, and judging whether the output response signal is abnormal or not; s5, calling all abnormal records to identify dominant parameters causing test abnormity and an abnormal threshold range of the dominant parameters; and S6, generating a final test analysis report. According to the invention, by constructing a multi-stress test control mechanism based on time synchronization, accurate test and abnormal traceability analysis of the vehicle-mounted chip under complex working conditions are realized, and the authenticity and traceability of the test are improved.

This invention belongs to the field of relay board testing, and in particular, a relay board testing fixture and method, comprising: a base and a lifting assembly disposed on the top of the base; a mounting plate connected to the lifting assembly, the lifting assembly being used to drive the mounting plate to move vertically, and multiple test probes mounted on the bottom of the mounting plate; two protective covers movably mounted on the bottom of the mounting plate, the two protective covers being used to protect the multiple test probes; a dust cleaning mechanism disposed on the two protective covers, used to clean dust adhering to the multiple test probes; and a moving mechanism connected to the two protective covers, the moving mechanism being used to drive the two protective covers to move towards each other. This invention, through two protective covers that can move towards each other, can completely enclose the test probes in the non-testing state, preventing the probes from being exposed to the outside and absorbing dust and impurities, preventing poor contact and probe damage. Simultaneously, after the test is completed, the protection can be quickly reset, further improving the protection effect.

Various embodiments described herein relate to a test chamber device an associated methods and non-transitory machine-readable media including a test chamber, a system builder that is configured to build and apply an equipment load to the test chamber; a load maker that is configured to build and apply a predefined load to the test chamber; and a tester which measures action of the equipment load and the predefined load within the test chamber, producing a test state.