608 results about "Test program" patented technology

The invention relates to the technical field of chip test engineering control, in particular to an active temperature control method and system for a chip aging tester, and the method comprises the steps: analyzing a test process according to test task parameters, and evaluating the expected thermal load change rate of a test chip, so as to dynamically generate a chip target junction temperature control curve; based on the chip target junction temperature control curve, the actual chip junction temperature and the current actual furnace temperature, the theoretical furnace temperature is obtained through a junction temperature closed-loop control algorithm, the furnace temperature compensation amount is calculated through a feedforward compensation algorithm in combination with the test state parameters, and the ideal furnace temperature is obtained according to the theoretical furnace temperature and the furnace temperature compensation amount; the actual temperature control quantity is obtained according to the basic temperature adjusting quantity and the temperature control compensation quantity, a preset chip target junction temperature control curve can be tracked more accurately, transient and steady state errors caused by test program switching and environment fluctuation can be more effectively restrained, and control over the chip junction temperature with higher precision and faster response is achieved.

The invention discloses a computer board card testing method and system, and relates to the technical field of computer board card testing, the system comprises a central server and at least one intelligent test fixture, the model of a to-be-tested board card is identified through the intelligent test fixture to obtain test information, and the test information is sent to the central server; and the central server determines a parallel test program corresponding to each to-be-tested board card according to the test information, and performs a synchronous test on each to-be-tested board card by running the parallel test program to obtain a test result corresponding to each to-be-tested board card. In the process, the model of the to-be-tested board card is automatically identified through the intelligent test fixture, the test program is automatically determined through the central server, automation of the test process is achieved, the problem of low efficiency caused by manual operation is avoided, and meanwhile, the test efficiency of the computer board card is improved by synchronously testing multiple to-be-tested board cards.

The invention relates to the technical field of computers, and discloses a method for generating a test program for testing a Solidiity smart contract compiler, which comprises the following steps of: defect directional triggering: inserting a Solidiity variable through an inline assembly block to expose an optimizer defect, and limiting a dynamic array / character string to be expanded to at most one element at a time; semantic consistency control: eliminating intermediate representation behavior differences by adopting a placeholder counter, and preventing border crossing through an array length check instruction; and resource conflict arbitration: managing EVM stack variables by using a block scope, and nesting hierarchies based on a depth threshold truncation function. Through triple innovative design of defect directional triggering, semantic consistency control and resource conflict arbitration, the fundamental contradiction among semantic ambiguity, low defect detection rate and resource constraint in the Solidity compiler test is systematically solved.

The invention provides a real-time stability test platform and method for data acquisition of a power distribution control chip. The real-time stability test platform comprises a test power grid, an acquisition system, a to-be-tested control chip, a high-low temperature alternating box, an upper computer and a clock module, the upper computer is used for storing a plurality of test programs, controlling the high and low temperature alternating box and the test power grid to obtain different working conditions, calling the corresponding test programs according to the different working conditions, sending out corresponding control instructions, and performing stability analysis on the control chip to be tested according to the first test data and the second test data; and obtaining a stability test result. The problem that in the prior art, a single parameter testing method is difficult to comprehensively evaluate the stability of a control chip in an actual complex environment in real time is solved; according to the invention, the stability of the control chip is efficiently tested in real time, and the problems of difficult simulation of complex working conditions and multi-parameter coupling influence can be solved.

The invention discloses a controller automatic test tool based on feature recognition and a test method thereof, and relates to the technical field of automatic test. The controller automation test tool comprises an image acquisition unit used for capturing display content of a controller screen; the electromechanical execution unit comprises a base positioning mechanism, a top pressing mechanism, a rear side butt joint mechanism, a key triggering mechanism set and a vibration mechanism. The control unit is respectively in communication connection with the image acquisition unit and the electromechanical execution unit, and is used for controlling the action of the electromechanical execution unit and receiving and analyzing the image information captured by the image acquisition unit; and the double-starting switch is connected with the control unit and needs to be synchronously triggered to start a test program. By integrating image acquisition and an electromechanical execution system, automatic identification of the display state of the controller screen and automatic execution of function operation are realized, and the consistency of the test efficiency and the test result is improved.

The invention provides a test system for prototype verification of a PCIE Switch switch chip. The system comprises an FPGA assembly, RC simulation equipment, EP simulation equipment and monitoring analysis equipment. In the application, the FPGA component integrates the tested component PCIE Switch and the test auxiliary component, supports hardware-level reconfiguration, can simulate topology and abnormal scenes of any RC device or EP device on the same platform, and does not need to replace physical hardware. Compared with an existing test system which depends on serial port log output faults, the method has the advantages that the error state is captured through FPGA hard logic, nanosecond fault tracing is achieved, and the test efficiency can be effectively improved. Besides, RC simulation equipment defines a test program through software, dynamically generates flow (such as normal / abnormal messages), and can replace physical RC equipment; the EP simulation device can respond to the test flow in real time, and can support multi-protocol version compatibility verification. Automatic testing of prototype verification of the PCIE Switch chip can be achieved through the monitoring and analyzing device, manual intervention is not needed, and input of testing manpower can be reduced.

The invention provides a chip testing method based on an ATE platform, and relates to the technical field of chip manufacturing and testing. According to the method, multiple advanced test technologies and intelligent algorithms are creatively integrated, test environment parameters are accurately controlled through an intelligent environment regulation and control system, radio frequency and digital signals are efficiently processed in cooperation with a test engine, a test execution stream optimizes a high-speed interface test by using a chip built-in Loopback function and an adaptive algorithm, and the test efficiency is improved. The intelligent control and analysis system dynamically adjusts a test process and accurately predicts chip defects based on a federal learning framework, and realizes Chiplet interconnection verification and closed-loop data analysis feedback optimization of a test program at the same time. The chip testing efficiency and precision are effectively improved, the testing cost is reduced, dependence on expensive equipment is reduced, the method can be widely applied to various chip testing scenes, and remarkable economic benefits and technical advantages are brought to chip manufacturing enterprises.

The invention provides a refrigerator factory performance automatic detection method and system, and the method comprises the steps: transmitting operation state data to a production test server in real time during the operation of a factory detection program through a built-in wireless communication module of a refrigerator; the production test server collects running state data of the multiple refrigerators which are judged to be qualified manually in a factory detection program, extracts a preset range of key parameters based on the running state data, and generates a test parameter set; and comparing the real-time operation state data of the refrigerator to be detected with the test parameter set, and if any key parameter exceeds a preset range, determining that the refrigerator is unqualified. The refrigerator is automatically connected with the production test server at the production line detection station, detection at the freezing stage, the refrigeration stage and the defrosting stage is executed in sequence, efficiency is high, maintenance cost is low, the requirement for variety diversification of refrigerators is met, test efficiency is improved, the problems that a traditional method is high in cost and low in efficiency are solved, the requirement for variety diversification of refrigerators is met, and product quality is improved. And the product quality stability is ensured.

The invention discloses a method for testing the comprehensive performance of an electrically-controlled silicone oil clutch water pump assembly. The method comprises the following steps: (1) installing the electrically-controlled silicone oil clutch water pump assembly to be tested on a test bench; (2) installing a test program in the control and data acquisition system, and inputting test parameters in the test program; (3) driving the tested fan of the electrically controlled silicone oil clutch water pump assembly by adopting controllable load equipment, and simulating the air resistance torque characteristics of the fan at different rotating speeds; and (4) starting the driving unit, controlling the load of the electrically-controlled silicone oil clutch and the working signal of the clutch according to the program, and testing various working conditions of the electrically-controlled silicone oil clutch. According to the method for testing the comprehensive performance of the electric control silicone oil clutch water pump assembly, comprehensive, efficient and accurate performance detection can be carried out on the electric control silicone oil clutch water pump assembly, product problems can be solved at an early stage, the product design is optimized, and the product quality is guaranteed.

The embodiment of the invention provides a fuzzy test method and device for an underwater control system communication protocol, and the method comprises the steps: defining each protocol field and an invariant segment according to a protocol description file, and generating input data meeting the protocol requirements; modeling a protocol interaction process based on the state diagram, and performing multi-path traversal in the state diagram based on input data; monitoring abnormity of network communication and a target process in operation of the fuzzy test program, obtaining feedback information, and adjusting the test case based on the feedback information; and according to the anomaly detection information in the test process, generating a standardized test report and a test case script capable of collapsing and reproducing.

The invention provides a test program generation method, electronic equipment and a storage medium, relates to the field of chips, and is mainly technically characterized by comprising the following steps: generating a plurality of subprograms corresponding to each module in at least two modules according to instruction characteristics of the at least two modules in a target processor; wherein each subprogram comprises dependency information with other subprograms, each subprogram comprises a plurality of instruction fragments, each instruction fragment comprises at least one instruction, and the dependency information of the subprogram is used for indicating whether the instruction fragment in the subprogram conflicts with the instruction fragments in other subprograms or not; the to-be-used instruction fragments are continuously selected until a preset ending condition is met, and the next to-be-used instruction fragment in every two adjacent to-be-used instruction fragments is the to-be-used instruction fragment which is sequentially selected from any subprogram of any module and does not conflict with the previous to-be-used instruction fragment; and obtaining a target test program according to a selection result of the to-be-used instruction fragment.

Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells connected to a plurality of word lines, respectively, a peripheral circuit configured to perform a test program operation and a pass bit detection operation of measuring a program speed of memory cells connected to a selected word line among the plurality of word lines during a test operation, and control logic configured to control the peripheral circuit to perform the test operation, and set a potential of a pass voltage to be used in a program operation, or a time point at which the pass voltage is to be applied, based on a number of times the test program operation is performed.

The invention provides an automatic testing method, device and platform for equipment load function performance, and relates to the technical field of software testing. According to the invention, through setting the plurality of subprogram packages in the process of testing the load function performance of the equipment, automatic programming is carried out according to the equipment type, the load type and the function type, the modularized combination generation of the test item, the test program and the subprogram is realized, the professional threshold is reduced, and the generation speed of the test program is improved. Furthermore, in combination with the task queue of the test accompanying instrument, path optimization is carried out on the test process, the test sequence of a plurality of test items is optimized, and the waiting time is shortened. Finally, based on the testing process and the testing program, automatic testing is achieved, the problem that the testing efficiency is low in the equipment load function performance testing process is solved, and the testing efficiency of the equipment load function performance testing is improved.

The invention relates to a method for producing a product, said method having the steps of: providing specification data of the product, said specification data containing reference values for product features of the product; processing the product in a plurality of processing steps in accordance with the specification data; creating a test program which comprises a plurality of test criteria, each of which is assigned at least one of the product features; testing the product in accordance with the test criteria of the test program by testing the product features assigned to the test criteria, each reference value assigned to the product features being compared with corresponding actual values actually determined during the test, and collecting test data which indicates the result of the test and / or the actual values of the product features.

The invention relates to a chip testing system, device and method. The chip test system comprises a server and an embedded test device which are in communication connection. The server is configured to store a test program and load the stored test program to the embedded test device; the embedded test device is configured to run a test program so as to test one or more chips to be tested connected with the embedded test device, and the test program simultaneously tests the computing power load and the memory pressure of the chips to be tested in parallel when running. According to the chip testing system, device and method, the testing efficiency can be remarkably improved, and the real performance of the chip in an actual service scene can be accurately reflected.

The invention discloses a DRAM (dynamic random access memory) repairing method, an upper computer, a storage medium and a computer program product, and relates to the technical field of DRAM repairing, the DRAM repairing method comprises the following steps: inputting a test program to a main control chip to enable the main control chip to test DRAM particles based on the test program, and determining fault information of the DRAM particles according to a test result; wherein the test program runs in an SRAM (Static Random Access Memory) in the main control chip; generating a corresponding repair program according to the fault information, and verifying the validity of the repair program; and under the condition that the repair program is verified to be valid, repairing the DRAM particles according to the repair program. According to the method and the device, the DRAM can be repaired on the premise of not depending on normal work of the DRAM.

The invention discloses a test and evaluation method for a virtualization system in multiple scenes, which comprises the following steps: deploying an executable file compiled by a test script at a virtualization client, and testing the performance of a client operating system to judge the performance loss of the virtualization system to computer resources. The method comprises the following steps: step 1, creating a project, and configuring system parameters; 2, integrating a test program into a project, and generating a mirror image file; step 3, packaging a complete virtualization system mirror image; 4, transmitting the mirror image to a development board through a network protocol; 5, executing a command to start a system, and logging in a system console through a serial port; and 6, calling and executing the function test script, the performance test script and the security test script.

The invention discloses a self-checking method and device for a storage module, a chip, a medium and a product, and the method comprises the steps: obtaining a pre-established first interrupt vector table from a target storage module when a self-checking program is executed on an error-injected storage module and if a trigger instruction error correction error of the error-injected storage module is detected, the target storage module is not injected with errors; and executing an interrupt service program corresponding to the first interrupt vector table. Therefore, when an instruction error correction error occurs, the interrupt vector table is read from the non-error-injected storage module instead of being read from the error-injected memory, so that a CPU (Central Processing Unit) can be prevented from accessing an invalid interrupt vector table to enter a locking state, and a self-checking program can normally run.

The invention provides a test case generation method and device, electronic equipment and a readable storage medium, code change is extracted based on Git change perception, and code change information of a to-be-tested program of a target version is obtained; screening out a first test case based on the code change information and a trained test case screening model; generating a second test case based on the code change information and a trained test case generation model; extracting dependency information of each external dependency associated with the code change, and matching a Mock object and a Mock rule for the external dependencies in the first test case and the second test case; and determining the matched first test case and second test case as a target test case of the to-be-tested program of the target version. Thus, through the trained test case screening model and test case generation model, the test case matched with the code change of the to-be-tested program can be generated, and the accuracy of test case generation in automatic testing is improved.

The embodiments of the present application relate to the technical field of computers. Provided are a cache performance evaluation method and apparatus, and an electronic device and a readable storage medium. The method comprises: in response to multiple memory access operations for each memory access request in a test program, acquiring memory access statistical information of the test program, wherein the memory access statistical information at least comprises a hit count of each memory access request in a cache to be evaluated; and evaluating the performance of said cache on the basis of the memory access statistical information and a memory access mode of each memory access request.

The invention relates to a vulnerability mining method and device for an intelligent unmanned system controller program. The method comprises the following steps: acquiring a communication data packet corresponding to the intelligent unmanned system sent by a fuzzy tester through a target test program; synchronously running a test driving thread and a target data packet receiving thread of a communication data packet corresponding to the intelligent unmanned system through the target test program based on a blocked communication mode; receiving a communication data packet corresponding to the intelligent unmanned system based on a target data packet receiving thread through a target test program, analyzing the communication data packet corresponding to the intelligent unmanned system, and determining execution data; and running the synchronous sending program and the synchronous receiving program, enabling a target execution thread in the target test program and the target data packet receiving thread to run synchronously, running execution data based on the target execution thread, and obtaining a vulnerability mining result of the intelligent unmanned system controller program. According to the scheme, the execution stability of the coverage rate guide fuzzy test process can be improved.

The invention discloses a method, device and equipment for efficiently evaluating operator performance, a medium and a product. The method comprises the following steps: when a to-be-evaluated operator is a data handling and calculation operator, after obtaining a plurality of segmentation strategies of the to-be-evaluated operator, calculating data handling time consumption and calculation time consumption of each segmentation strategy according to a bandwidth model and an operator calculation kernel performance model which are adaptive to a target AI chip; preliminarily calculating the operator total time consumption of the operator to be evaluated for each segmentation strategy; afterwards, according to the preliminarily calculated operator total time consumption, screening to obtain each alternative segmentation strategy, measuring the target actual measurement data carrying time consumption and the target actual measurement calculation time consumption of each alternative segmentation strategy by operating a bandwidth test program and calculating a core test program, and calculating the target actual measurement data carrying time consumption and the target actual measurement calculation time consumption of each alternative segmentation strategy; and recalculating the operator total time consumption of the to-be-evaluated operator for each alternative segmentation strategy to perform operator performance evaluation. According to the technical scheme of the embodiment of the invention, the operator performance of the AI chip can be quickly, accurately and comprehensively evaluated.

The embodiment of the invention provides a chip testing method and device and a storage medium. The method is applied to an upper computer in a test system, and comprises the following steps: displaying a configuration information setting interface; setting values corresponding to the configuration items are obtained on the configuration information setting interface, and a test configuration file is obtained; generating a test script based on the test configuration file; and running the test script to test the chip to be tested. According to the technical scheme provided by the embodiment of the invention, when the to-be-tested chip is tested, only the configuration information related to the test process needs to be filled in the test configuration interface to form the test configuration file, the test configuration file is processed by utilizing the automatic test program, the test script is automatically generated, and the test efficiency is improved. And finally, the test script is run to test the chip to be tested, and the test script does not need to be customized by technical personnel in the process, so that the development difficulty of the test script can be reduced, the compiling efficiency of the test script is improved, and the test efficiency is improved.

The invention provides an efficient parameterization co-simulation method which comprises the following steps: S1, parameterization design: in circuit design software, performing parameterization design on a target circuit, and defining adjustable parameters in the target circuit; s2, data transmission interaction design: defining a data transmission channel and a data transmission format between the circuit design software and the graphical programming software, and then writing a test program in the graphical programming software according to the requirement of the data transmission format; and S3, co-simulation is carried out. According to the method, rapid iteration design can be achieved, potential problems can be rapidly found and solved through an automatic testing process, time and energy of designers are saved, product marketing time is shortened, design accuracy and reliability are improved, production cost is further reduced, product competitiveness is improved, and remarkable economic benefits are brought to enterprises.

The invention discloses a communication module test method, device and equipment, a medium and a computer program product, and the method comprises the steps: detecting whether a test flag bit of a communication module is set or not in response to a test instruction; if the test flag bit is not set, loading and running an application program and a test program of the communication module; wherein the test program and the application program are stored in a decoupling manner, and the test program is stored in a non-application program partition of the communication module; based on the communication connection between the interface to be tested of the application program and the shadow interface of the test program, the application program is tested, after the test is passed, the storage space occupied by the test program and the system operation resources are invalid, and the test mark position is set. According to the invention, the complexity of the communication module software test can be effectively reduced, the test coverage is enhanced, the stability of the module software is improved, and the space utilization rate of the module can be improved.

This invention relates to a service fault location system and method based on a BMC (Browser Control Center). The system includes: establishing a communication link between the BMC and the server under test (DUT) using a customized IPMI protocol; configuring test parameters and controlling the DUT to power on and start a restart test program; the BMC collecting current hardware-level data; the BMC performing temporary storage and determining whether an anomaly occurred during the current test round; when an anomaly occurs during the current test round, the BMC receives the current customized IPMI message, obtains the anomaly level information, and controls the CPLD (Content Management Logic Controller) to perform a hard restart or not perform a hard restart based on the anomaly level information, and persistently stores the on-site data. No additional test equipment or server hardware / software modifications are required, resulting in lower testing costs and broad applicability; in the event of an abnormal downtime, the BMC can directly operate the CPLD to perform a hard restart, greatly improving testing efficiency and continuity.

The application discloses a concurrent program vulnerability detection method based on fuzzy testing and static analysis, and comprises the following steps: compiling a to-be-detected program source code, obtaining a bytecode file according to the compiling, then performing static analysis to obtain a concurrent vulnerability pair; performing program insertion on the concurrent vulnerability pair to obtain a program binary file with inserted code; taking the program binary file with inserted code as a test program, adding an initial input file in an input queue, adding a concurrent vulnerability-oriented mechanism in AFL and adding a judgment mode of whether an input is interesting, and pruning unfeasible paths; performing fuzzy testing to realize vulnerability detection. The application can not only utilize the characteristics of concurrent program vulnerabilities, use an optimized redundant node static analysis technology to reduce the number of concurrent vulnerability detections, but also use a fuzzy testing technology to efficiently reproduce the occurrence process of the concurrent program vulnerabilities, so that more efficient and more intuitive concurrent vulnerability detection is realized.

The present invention discloses a BMC cold restart stress testing system, belonging to the field of computer firmware technology. The system includes two types of devices: a test host and a tested server. The test host can be connected to multiple tested servers via a network. The test host provides a writing environment for server BMC test scripts. Testers will write a test script instance for BMC cold restart. The completed script will be sent to the tested server via the test host. The test program of the tested server host operating system sends a test instruction to the BMC to execute the test script, obtain the BMC test results, and automatically generate a test report to complete the BMC cold restart test. The present invention can improve the efficiency of BMC cold restart testing, increase the coverage of BMC interaction and status judgment, and realize the flexible expansion of BMC configuration parameters.

The embodiment of the invention provides an intelligent agent system for graphics processor development and a graphics processor development method, and is applied to the technical field of graphics processor development. The intelligent agent system comprises a first intelligent agent, a second intelligent agent, a plurality of third intelligent agents and a fourth intelligent agent. The first intelligent agent is configured to receive a development task and drive the other intelligent agents to execute corresponding operations in sequence or in parallel so as to complete the development task; the second agent is configured to maintain related documents; the plurality of third agents are configured to generate function codes based on related documents; and the fourth agent is configured to perform joint test on the function codes to generate test information. The plurality of third agents includes a simulator agent, an assembler agent, and a test program agent. According to the intelligent agent system, related documents serve as a single fact source, a simulator, an assembler and a test program are automatically processed through multi-intelligent-agent cooperation, and the consistency of all components consuming the related documents is guaranteed.