489 results about "Test program" patented technology

The invention relates to the technical field of chip test engineering control, in particular to an active temperature control method and system for a chip aging tester, and the method comprises the steps: analyzing a test process according to test task parameters, and evaluating the expected thermal load change rate of a test chip, so as to dynamically generate a chip target junction temperature control curve; based on the chip target junction temperature control curve, the actual chip junction temperature and the current actual furnace temperature, the theoretical furnace temperature is obtained through a junction temperature closed-loop control algorithm, the furnace temperature compensation amount is calculated through a feedforward compensation algorithm in combination with the test state parameters, and the ideal furnace temperature is obtained according to the theoretical furnace temperature and the furnace temperature compensation amount; the actual temperature control quantity is obtained according to the basic temperature adjusting quantity and the temperature control compensation quantity, a preset chip target junction temperature control curve can be tracked more accurately, transient and steady state errors caused by test program switching and environment fluctuation can be more effectively restrained, and control over the chip junction temperature with higher precision and faster response is achieved.

The invention discloses a controller automatic test tool based on feature recognition and a test method thereof, and relates to the technical field of automatic test. The controller automation test tool comprises an image acquisition unit used for capturing display content of a controller screen; the electromechanical execution unit comprises a base positioning mechanism, a top pressing mechanism, a rear side butt joint mechanism, a key triggering mechanism set and a vibration mechanism. The control unit is respectively in communication connection with the image acquisition unit and the electromechanical execution unit, and is used for controlling the action of the electromechanical execution unit and receiving and analyzing the image information captured by the image acquisition unit; and the double-starting switch is connected with the control unit and needs to be synchronously triggered to start a test program. By integrating image acquisition and an electromechanical execution system, automatic identification of the display state of the controller screen and automatic execution of function operation are realized, and the consistency of the test efficiency and the test result is improved.

The invention provides a chip testing method based on an ATE platform, and relates to the technical field of chip manufacturing and testing. According to the method, multiple advanced test technologies and intelligent algorithms are creatively integrated, test environment parameters are accurately controlled through an intelligent environment regulation and control system, radio frequency and digital signals are efficiently processed in cooperation with a test engine, a test execution stream optimizes a high-speed interface test by using a chip built-in Loopback function and an adaptive algorithm, and the test efficiency is improved. The intelligent control and analysis system dynamically adjusts a test process and accurately predicts chip defects based on a federal learning framework, and realizes Chiplet interconnection verification and closed-loop data analysis feedback optimization of a test program at the same time. The chip testing efficiency and precision are effectively improved, the testing cost is reduced, dependence on expensive equipment is reduced, the method can be widely applied to various chip testing scenes, and remarkable economic benefits and technical advantages are brought to chip manufacturing enterprises.

The invention provides a test program generation method, electronic equipment and a storage medium, relates to the field of chips, and is mainly technically characterized by comprising the following steps: generating a plurality of subprograms corresponding to each module in at least two modules according to instruction characteristics of the at least two modules in a target processor; wherein each subprogram comprises dependency information with other subprograms, each subprogram comprises a plurality of instruction fragments, each instruction fragment comprises at least one instruction, and the dependency information of the subprogram is used for indicating whether the instruction fragment in the subprogram conflicts with the instruction fragments in other subprograms or not; the to-be-used instruction fragments are continuously selected until a preset ending condition is met, and the next to-be-used instruction fragment in every two adjacent to-be-used instruction fragments is the to-be-used instruction fragment which is sequentially selected from any subprogram of any module and does not conflict with the previous to-be-used instruction fragment; and obtaining a target test program according to a selection result of the to-be-used instruction fragment.

Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells connected to a plurality of word lines, respectively, a peripheral circuit configured to perform a test program operation and a pass bit detection operation of measuring a program speed of memory cells connected to a selected word line among the plurality of word lines during a test operation, and control logic configured to control the peripheral circuit to perform the test operation, and set a potential of a pass voltage to be used in a program operation, or a time point at which the pass voltage is to be applied, based on a number of times the test program operation is performed.

The invention provides an automatic testing method, device and platform for equipment load function performance, and relates to the technical field of software testing. According to the invention, through setting the plurality of subprogram packages in the process of testing the load function performance of the equipment, automatic programming is carried out according to the equipment type, the load type and the function type, the modularized combination generation of the test item, the test program and the subprogram is realized, the professional threshold is reduced, and the generation speed of the test program is improved. Furthermore, in combination with the task queue of the test accompanying instrument, path optimization is carried out on the test process, the test sequence of a plurality of test items is optimized, and the waiting time is shortened. Finally, based on the testing process and the testing program, automatic testing is achieved, the problem that the testing efficiency is low in the equipment load function performance testing process is solved, and the testing efficiency of the equipment load function performance testing is improved.

The invention relates to a method for producing a product, said method having the steps of: providing specification data of the product, said specification data containing reference values for product features of the product; processing the product in a plurality of processing steps in accordance with the specification data; creating a test program which comprises a plurality of test criteria, each of which is assigned at least one of the product features; testing the product in accordance with the test criteria of the test program by testing the product features assigned to the test criteria, each reference value assigned to the product features being compared with corresponding actual values actually determined during the test, and collecting test data which indicates the result of the test and / or the actual values of the product features.

The invention discloses a test and evaluation method for a virtualization system in multiple scenes, which comprises the following steps: deploying an executable file compiled by a test script at a virtualization client, and testing the performance of a client operating system to judge the performance loss of the virtualization system to computer resources. The method comprises the following steps: step 1, creating a project, and configuring system parameters; 2, integrating a test program into a project, and generating a mirror image file; step 3, packaging a complete virtualization system mirror image; 4, transmitting the mirror image to a development board through a network protocol; 5, executing a command to start a system, and logging in a system console through a serial port; and 6, calling and executing the function test script, the performance test script and the security test script.

The embodiments of the present application relate to the technical field of computers. Provided are a cache performance evaluation method and apparatus, and an electronic device and a readable storage medium. The method comprises: in response to multiple memory access operations for each memory access request in a test program, acquiring memory access statistical information of the test program, wherein the memory access statistical information at least comprises a hit count of each memory access request in a cache to be evaluated; and evaluating the performance of said cache on the basis of the memory access statistical information and a memory access mode of each memory access request.

The invention relates to a vulnerability mining method and device for an intelligent unmanned system controller program. The method comprises the following steps: acquiring a communication data packet corresponding to the intelligent unmanned system sent by a fuzzy tester through a target test program; synchronously running a test driving thread and a target data packet receiving thread of a communication data packet corresponding to the intelligent unmanned system through the target test program based on a blocked communication mode; receiving a communication data packet corresponding to the intelligent unmanned system based on a target data packet receiving thread through a target test program, analyzing the communication data packet corresponding to the intelligent unmanned system, and determining execution data; and running the synchronous sending program and the synchronous receiving program, enabling a target execution thread in the target test program and the target data packet receiving thread to run synchronously, running execution data based on the target execution thread, and obtaining a vulnerability mining result of the intelligent unmanned system controller program. According to the scheme, the execution stability of the coverage rate guide fuzzy test process can be improved.

The invention discloses a method, device and equipment for efficiently evaluating operator performance, a medium and a product. The method comprises the following steps: when a to-be-evaluated operator is a data handling and calculation operator, after obtaining a plurality of segmentation strategies of the to-be-evaluated operator, calculating data handling time consumption and calculation time consumption of each segmentation strategy according to a bandwidth model and an operator calculation kernel performance model which are adaptive to a target AI chip; preliminarily calculating the operator total time consumption of the operator to be evaluated for each segmentation strategy; afterwards, according to the preliminarily calculated operator total time consumption, screening to obtain each alternative segmentation strategy, measuring the target actual measurement data carrying time consumption and the target actual measurement calculation time consumption of each alternative segmentation strategy by operating a bandwidth test program and calculating a core test program, and calculating the target actual measurement data carrying time consumption and the target actual measurement calculation time consumption of each alternative segmentation strategy; and recalculating the operator total time consumption of the to-be-evaluated operator for each alternative segmentation strategy to perform operator performance evaluation. According to the technical scheme of the embodiment of the invention, the operator performance of the AI chip can be quickly, accurately and comprehensively evaluated.

The invention discloses a communication module test method, device and equipment, a medium and a computer program product, and the method comprises the steps: detecting whether a test flag bit of a communication module is set or not in response to a test instruction; if the test flag bit is not set, loading and running an application program and a test program of the communication module; wherein the test program and the application program are stored in a decoupling manner, and the test program is stored in a non-application program partition of the communication module; based on the communication connection between the interface to be tested of the application program and the shadow interface of the test program, the application program is tested, after the test is passed, the storage space occupied by the test program and the system operation resources are invalid, and the test mark position is set. According to the invention, the complexity of the communication module software test can be effectively reduced, the test coverage is enhanced, the stability of the module software is improved, and the space utilization rate of the module can be improved.

This invention relates to a service fault location system and method based on a BMC (Browser Control Center). The system includes: establishing a communication link between the BMC and the server under test (DUT) using a customized IPMI protocol; configuring test parameters and controlling the DUT to power on and start a restart test program; the BMC collecting current hardware-level data; the BMC performing temporary storage and determining whether an anomaly occurred during the current test round; when an anomaly occurs during the current test round, the BMC receives the current customized IPMI message, obtains the anomaly level information, and controls the CPLD (Content Management Logic Controller) to perform a hard restart or not perform a hard restart based on the anomaly level information, and persistently stores the on-site data. No additional test equipment or server hardware / software modifications are required, resulting in lower testing costs and broad applicability; in the event of an abnormal downtime, the BMC can directly operate the CPLD to perform a hard restart, greatly improving testing efficiency and continuity.

The application discloses a concurrent program vulnerability detection method based on fuzzy testing and static analysis, and comprises the following steps: compiling a to-be-detected program source code, obtaining a bytecode file according to the compiling, then performing static analysis to obtain a concurrent vulnerability pair; performing program insertion on the concurrent vulnerability pair to obtain a program binary file with inserted code; taking the program binary file with inserted code as a test program, adding an initial input file in an input queue, adding a concurrent vulnerability-oriented mechanism in AFL and adding a judgment mode of whether an input is interesting, and pruning unfeasible paths; performing fuzzy testing to realize vulnerability detection. The application can not only utilize the characteristics of concurrent program vulnerabilities, use an optimized redundant node static analysis technology to reduce the number of concurrent vulnerability detections, but also use a fuzzy testing technology to efficiently reproduce the occurrence process of the concurrent program vulnerabilities, so that more efficient and more intuitive concurrent vulnerability detection is realized.

The embodiment of the invention provides an intelligent agent system for graphics processor development and a graphics processor development method, and is applied to the technical field of graphics processor development. The intelligent agent system comprises a first intelligent agent, a second intelligent agent, a plurality of third intelligent agents and a fourth intelligent agent. The first intelligent agent is configured to receive a development task and drive the other intelligent agents to execute corresponding operations in sequence or in parallel so as to complete the development task; the second agent is configured to maintain related documents; the plurality of third agents are configured to generate function codes based on related documents; and the fourth agent is configured to perform joint test on the function codes to generate test information. The plurality of third agents includes a simulator agent, an assembler agent, and a test program agent. According to the intelligent agent system, related documents serve as a single fact source, a simulator, an assembler and a test program are automatically processed through multi-intelligent-agent cooperation, and the consistency of all components consuming the related documents is guaranteed.

The application discloses a fault diagnosis automation test method and system, an electronic device and a storage medium. The method comprises the following steps: generating a preset standardized fault code table according to a fault diagnosis specification and a preset fault parameter; generating a preset test case through a preset program development module according to the preset standardized fault code table; generating an automation test program according to the preset test case; and performing fault diagnosis test through the automation test program to obtain a fault diagnosis test result. The embodiment of the application can realize the automation test of the controller fault diagnosis, effectively improve the test efficiency, and shorten the test period. The application can be widely applied to the technical field of fault diagnosis.

To automatically test an OS incorporated in equipment or a control board.SOLUTION: An acquisition unit 51 that communicates with a repository via a network and acquires a source code of a target program from the repository, a build unit 52 that builds the target program using the acquired source code, a writing unit 53 that performs a process of writing the built target program to a storage unit of a target board, a reset unit 54 that performs a process of resetting the target board, a communication unit 55 that communicates with the target board, instructs a control unit of the target board to execute an automatic test, and receives a test result of the automatic test from the target board, and a determination unit 56 that performs a process of determining results of various tests executed on the target board based on the received test result.SELECTED DRAWING: Figure 6

The utility model discloses a programmable logic device test experiment device, which relates to the field of logic device test experiments and comprises a replaceable FPGA test circuit, a phase-locked loop test circuit, a pulse width modulation test circuit, a chip power supply circuit, a serial port test circuit, a Bank area power supply test circuit, a power supply generation circuit and a liquid crystal display control circuit. According to the experimental device for testing the programmable logic device, through a mode of combining the liquid crystal display screen and the FPGA function test board, a large-scale test machine in traditional test equipment is omitted, so that a test system is more portable, comprehensive coverage test of FPGA chip functions can be realized through compiling a plurality of self-test programs, and the test efficiency is improved. Therefore, not only can the basic logic function of the FPGA be tested, but also the advanced characteristics and boundary conditions of the FPGA can be deeply verified, so that the function correctness of the FPGA chip can be more comprehensively ensured.

The invention discloses an implementation method of a serial port tool, the serial port tool, equipment and a storage medium. The implementation method of the serial port tool comprises the steps of testing current tested equipment based on an obtained test case, and generating a test program corresponding to the test case; constructing a test data document in the server, wherein the test data document comprises a serial port instruction set, a communication protocol, a test case set and a test program corresponding to each test case; the test data document is subjected to structured analysis, so that an intelligent index model of the test data document is constructed, and the intelligent index model is used for indexing related communication protocols, test case sets and test programs corresponding to the test cases in the test data document through an AI algorithm according to the index keywords. Through the mode, the test efficiency and quality of the serial port can be improved.

The application belongs to the technical field of automatic test program, and particularly relates to a LabVIEW test method of a multi-channel programmable output clock buffer. The method comprises the following steps: initializing the clock buffer after power-on; resetting the FSWP spectrum analyzer and clearing the previous interface settings; switching the radio frequency switch to channel 1 and opening the channel 1 output; setting the signal source input frequency; setting the signal source input amplitude; starting the signal source input, and outputting the set frequency and amplitude to the input end of the clock buffer; starting the register configuration module, and transmitting the 174 24-bit register values to the SPI in sequence through the serial port, and then transmitting the SPI to the clock buffer; reading the data on the FSWP spectrum analyzer; and the method automatically measures the key indicators of the 14-channel clock buffer, saves the data and judges the advantages and disadvantages. The method reduces the burden of the test personnel, reduces the test time cost, and avoids causing data errors.

The present invention relates to a smoke detector test bench (test device) for the functional testing of a smoke detector, in particular a linear smoke detector based on the transmitted light principle, in a manner that complies with standards and / or is standardized, and to its use or application in this regard, as well as to a corresponding smoke detector test method.

The invention discloses a power panel automatic test method and system based on a drawer type jig, and belongs to the technical field of electrical testing, and the method comprises the steps: obtaining a serial number of a to-be-tested power panel to call a test program; identifying the ID code of the jig to carry out matching verification; the driving module is controlled to form preliminary contact, and a contact quality characteristic value is measured and generated; if the characteristic value does not reach the contact quality threshold value, generating a driving compensation parameter to adjust a driving module, and determining a final driving parameter; performing a comprehensive electrical test on the to-be-tested power panel to generate a test result; and associating the final driving parameter, the test result and the serial number information to generate process associated data. According to the invention, closed-loop iterative compensation is carried out on the driving module based on the contact electrical characteristics measured in real time, and the technical scheme of dual automatic verification of the serial number of the to-be-tested board and the ID of the jig is combined, so that intelligent mistake proofing of the test process and data tracing of the whole process can be realized while high reliability of test contact is guaranteed.

This invention belongs to the field of integrated circuit testing and semiconductor manufacturing quality control technology, and discloses an integrated circuit final testing method and system based on dynamic power consumption compensation. The method includes the following steps: acquiring power consumption prediction data for each test vector in the test program; querying a lookup table to obtain the expected voltage drop value corresponding to each test vector; performing feedforward pre-compensation on the supply voltage based on the expected voltage drop value before testing; monitoring the actual voltage at the power supply pin in real time during testing; comparing the actual voltage with the target voltage to generate an error signal; performing feedback fine-tuning compensation on the supply voltage based on the error signal; and collecting the actual voltage drop value under each test vector after testing, iteratively updating the expected voltage drop value of the corresponding test vector in the lookup table based on the deviation between the actual voltage drop value and the corresponding expected voltage drop value. This invention can solve the problems of test misjudgment, low yield, and insufficient test coverage caused by IR drop in traditional testing methods.

The invention discloses an automobile chip overvoltage test system and method, and belongs to the technical field of chip test.According to the automobile chip overvoltage test system, a power supply module is used for providing an adjustable direct-current power supply for a chip to be tested; the test master control module controls the output voltage of the power supply module and adjusts the output voltage according to a preset test program; testing data of the to-be-tested chip under different voltage conditions are measured by using the testing instrument module; a to-be-tested chip is installed through the test board card module; the test master control module obtains test data of the power supply module and the test instrument module, processes and analyzes the test data and generates a test report, and the output voltage range of the power supply module covers the upper and lower limits of the normal working voltage of the automobile chip and can exceed a certain range so as to simulate overvoltage and undervoltage conditions. Performance and functions of the automobile chip under different overvoltage and undervoltage conditions can be tested comprehensively and accurately.

The invention discloses a processor performance testing method and device, electronic equipment and a storage medium. When the performance test is carried out on the target processor, the test data of the target processor is firstly configured, the target core of the target processor is associated with the target thread of the test program, and it is ensured that the target thread runs on the target core. And in the process that the test program runs according to the test data, determining a test result of the target processor according to the running data. According to the embodiment of the invention, the test data is configured for the target processor, and the target core of the target processor is associated and bound with the target thread executed by the test program, so that the test environment can be flexibly configured; by monitoring the running data when the test program runs, the test result of the target processor is determined according to the running data, so that the test program can be tested under different configurations of the target processor, the test results under different test environments are obtained, and the test accuracy and reliability are improved.

The invention discloses a code compiling device and method, and belongs to the technical field of computers. The device comprises a compiling module used for compiling a test program matched with a cost model for at least one section of candidate code, and the cost model is constructed by depending on the hardware performance of a target platform; the sending module is used for sending the test program to the target platform; the receiving module is used for receiving cost data obtained after the test program runs on the target platform, and the cost data is used for describing the running cost of at least one section of candidate code on the target platform; and the compiling module is also used for determining a target code from the at least one section of candidate code according to the cost data, and compiling the target code into a target machine code matched with the target platform. Therefore, the optimal machine code for the target platform is obtained, and user requirements are met.

The invention discloses a software ecological management method of automatic test equipment and application thereof, and belongs to the technical field of integrated circuit test. The method comprises the following steps: automatically writing a version identifier containing firmware information of an upper computer and a lower computer when a test program is compiled; when the program is loaded, the system obtains the actual version of the current operating environment and compares the actual version with the version identifier; if the versions are not matched, the system interrupts program execution through consistency verification and an interlocking controller, and a version switching manager is started; and the version switching manager automatically closes the current environment according to the version identifier, searches a version information base, switches the software of the upper computer, synchronously updates the firmware of the lower computer to a target version, and restores the test after the environment verification is passed. Through binding during compiling and forced verification during loading, automatic and accurate switching of the test environment is achieved, the problems that manual switching is prone to errors and software and hardware collaboration is poor are solved, and the test risk and the maintenance cost are remarkably reduced.

This application belongs to the field of aero-engine technology, and specifically relates to a method and apparatus for simulating aircraft bleed air during sustained test of a turbofan engine, wherein the inlet temperature T1 and inlet pressure P1 of the engine are preset to a range; Step S2: Calculate the aircraft bleed air volume W fy The range, the total bleed air temperature T of the aircraft fy The range and total bleed air pressure P fy Range; Step S3: Calculate the cold diameter D of the bleed air nozzle. fy Range; Step S4: Select the cold-state diameter D of the bleed air nozzle fy An aircraft bleed air volume verification test was conducted to obtain the bleed air volume W for the test. fyr When the induced draft volume W in the experiment fyr The requirements are met, and the cold-state diameter D of the expiratory air nozzle is adopted. fy When the induced draft volume W in the experiment fyr If the requirements are not met, return to step S4; ensure that the calculation error of the aircraft bleed air volume is within the required range, and obtain the actual bleed air volume of the engine in various states to the maximum extent through test program design. This test method has the advantages of simple test method, low test cost and high replacement efficiency.

The invention discloses a test case generation method and device and a readable storage medium, and belongs to the technical field of automatic software testing. The method comprises the following steps: performing method call analysis on a to-be-tested program to generate a method call set; inputting the test case and a program code into a large language model to generate an initial test case; and evaluating the coverage rate, and if the saturation condition is not met, identifying an uncovered code line and feeding back the uncovered code line to the model to iteratively generate a new case until the coverage rate is saturated. According to the method, the high-coverage test case can be automatically and efficiently generated, and the method is particularly suitable for a scientific calculation program.