3187 results about "Test program" patented technology

For testing electrical properties of packaged IC devices, there is provided an apparatus which includes a test board which is located at a testing station and provided with a plural number of contacting sockets for connecting individual IC devices to an IC tester separately and independently of each other, a loader which is located at a loading station and adapted to feed untested IC devices toward the test board, an unloader which is located at an unloading station and adapted to discharge tested IC devices from the test board at the testing station, and a device transfer mechanism which is movable across the testing station to transfer untested IC devices from the loader to the test board and also to transfer tested IC devices from the test board to the unloader. Upon detecting completion of a test on one of IC devices in one socket of the test board, a fresh untested IC device is transferred to the testing station to replace the tested IC device. As soon as the fresh IC device is set in position in that socket, execution of a test program is started with respect to that socket on the test board.

A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model. Further, a backtracking search may be performed to find a valid ordering if such ordering exists or show that none exists and, hence, confirm whether or not the results comply with the given memory consistency model.

Methods and apparatus provide single or multi-port, flexible, cost-effective, built-in self-test capabilities for network communications equipment, such as for example switches, and programmably generate, and subsequently analyze, one or more sequences of test packets, wherein the test packets simulate at least two flows of traffic. Such test packets can have programmable headers, payloads, and duty cycle. A line card embodying the present invention may generate its own traffic pattern, which may be similar or identical, to traffic patterns observed on Internet backbones. These traffic patterns may contain a bimodal distribution of control packets interspersed with data packets wherein the control packets and data packets are relatively short and long respectively. A plurality of test packet generators / receivers can be deployed in a network communications device having a plurality of ports. In such a configuration, test generator / receiver is associated with each of the plurality of ports. Under software control, test packets can be sent from at least any one of the plurality of ports to at least any other one of the plurality of ports. In this way, an in-circuit testing procedure may be implemented without having to disconnect line cards from the switch and connect the switch to expensive external test equipment.

A method and apparatus are disclosed for testing the accuracy of digital test images generated by a computer graphics program executed on a computer graphics system. A test program is utilized to compare the test image with a reference image. The user defines regions of interest and a maximum error for each region. This allows the user to focus on a particular object or group of objects. Global image quantification verification generates one measurement of error or image difference for each region of the test image. Each region is divided into sub-regions and an average color value is calculated for each sub-region and the corresponding sub-region in the reference image. The differences between the averages for corresponding sub-regions in the test and reference images are calculated. A test image region may be unacceptably different from a reference image if a normalized sum of the absolute differences exceeds the maximum error.

A probe card of a wafer test system includes one or more programmable ICs, such as FPGAs, to provide routing from individual test signal channels to one of multiple probes. The programmable ICs can be placed on a base PCB of the probe card, or on a daughtercard attached to the probe card. With programmability, the PCB can be used to switch limited test system channels away from unused probes. Programmability further enables a single probe card to more effectively test devices having the same pad array, but having different pin-outs for different device options. Reprogrammability also allows test engineers to re-program as they are debugging a test program. Because the programmable IC typically includes buffers that introduce an unknown delay, in one embodiment measurement of the delay is accomplished by first programming the programmable IC to provide a loop back path to the test system so that buffer delay can be measured, and then reprogramming the programmable IC now with a known delay to connect to a device being tested.

A method for managing a pattern object file in a modular test system is disclosed. The method includes providing a modular test system, where the modular test system comprises a system controller for controlling at least one site controller, and where the at least one site controller controls at least one test module and its corresponding device under test (DUT). The method further includes creating an object file management framework for establishing a standard interface between vendor-supplied pattern compilers and the modular test system, receiving a pattern source file, creating a pattern object metafile based on the pattern source file using the object file management framework, and testing the device under test through the test module using the pattern object metafile.