804 results about "Test program" patented technology

The invention relates to the technical field of chip test engineering control, in particular to an active temperature control method and system for a chip aging tester, and the method comprises the steps: analyzing a test process according to test task parameters, and evaluating the expected thermal load change rate of a test chip, so as to dynamically generate a chip target junction temperature control curve; based on the chip target junction temperature control curve, the actual chip junction temperature and the current actual furnace temperature, the theoretical furnace temperature is obtained through a junction temperature closed-loop control algorithm, the furnace temperature compensation amount is calculated through a feedforward compensation algorithm in combination with the test state parameters, and the ideal furnace temperature is obtained according to the theoretical furnace temperature and the furnace temperature compensation amount; the actual temperature control quantity is obtained according to the basic temperature adjusting quantity and the temperature control compensation quantity, a preset chip target junction temperature control curve can be tracked more accurately, transient and steady state errors caused by test program switching and environment fluctuation can be more effectively restrained, and control over the chip junction temperature with higher precision and faster response is achieved.

The invention relates to the technical field of storage, in particular to a test method, device, equipment, system, medium and product, and the method comprises the steps: obtaining a test management command of an input and output management command representing error injection in a real working environment of a disk array controller chip; the command is analyzed to obtain the error injection test type and the corresponding related parameters, and the error processing mode is changed according to the error injection test type, so that the exception is only reported and not processed when encountering the exception in the test, the interference of exception processing on the test process is avoided, and the test can be smoothly carried out according to the preset error injection scene; and according to the error injection test type and the related parameters, constructing analog input and output and injecting the analog input and output into the target hardware unit to perform an execution behavior test, thereby realizing accurate test of the specific hardware unit in a specific error scene in an environment of performing input and output test based on a read-write input and output test program, so that the test is more comprehensive, and the test efficiency is improved. And the test precision is higher.

The invention discloses a computer board card testing method and system, and relates to the technical field of computer board card testing, the system comprises a central server and at least one intelligent test fixture, the model of a to-be-tested board card is identified through the intelligent test fixture to obtain test information, and the test information is sent to the central server; and the central server determines a parallel test program corresponding to each to-be-tested board card according to the test information, and performs a synchronous test on each to-be-tested board card by running the parallel test program to obtain a test result corresponding to each to-be-tested board card. In the process, the model of the to-be-tested board card is automatically identified through the intelligent test fixture, the test program is automatically determined through the central server, automation of the test process is achieved, the problem of low efficiency caused by manual operation is avoided, and meanwhile, the test efficiency of the computer board card is improved by synchronously testing multiple to-be-tested board cards.

The utility model discloses a DBC automatic test workstation, which comprises a test mechanism, a movable truss and a machine table, the test mechanism comprises a first test station, a second test station and a third test station, and the first test station, the second test station and the third test station are all installed on the machine table. The two ends of the movable truss are installed on the two sides of the machine table, the moving path of the movable truss is arranged above the first testing station, the second testing station and the third testing station, the movable truss is used for testing the bonded DBC module, the equipment can integrate various testing machines, and the testing efficiency is improved. Detection items such as safety testing, static testing and dynamic testing are automatically completed according to program setting, different testing processes can be achieved by calling testing programs, meanwhile, the equipment has the function of recording and storing testing data, the testing items are flexibly configured, and the testing efficiency is remarkably improved.

The invention relates to the technical field of computers, and discloses a method for generating a test program for testing a Solidiity smart contract compiler, which comprises the following steps of: defect directional triggering: inserting a Solidiity variable through an inline assembly block to expose an optimizer defect, and limiting a dynamic array / character string to be expanded to at most one element at a time; semantic consistency control: eliminating intermediate representation behavior differences by adopting a placeholder counter, and preventing border crossing through an array length check instruction; and resource conflict arbitration: managing EVM stack variables by using a block scope, and nesting hierarchies based on a depth threshold truncation function. Through triple innovative design of defect directional triggering, semantic consistency control and resource conflict arbitration, the fundamental contradiction among semantic ambiguity, low defect detection rate and resource constraint in the Solidity compiler test is systematically solved.

The invention provides a real-time stability test platform and method for data acquisition of a power distribution control chip. The real-time stability test platform comprises a test power grid, an acquisition system, a to-be-tested control chip, a high-low temperature alternating box, an upper computer and a clock module, the upper computer is used for storing a plurality of test programs, controlling the high and low temperature alternating box and the test power grid to obtain different working conditions, calling the corresponding test programs according to the different working conditions, sending out corresponding control instructions, and performing stability analysis on the control chip to be tested according to the first test data and the second test data; and obtaining a stability test result. The problem that in the prior art, a single parameter testing method is difficult to comprehensively evaluate the stability of a control chip in an actual complex environment in real time is solved; according to the invention, the stability of the control chip is efficiently tested in real time, and the problems of difficult simulation of complex working conditions and multi-parameter coupling influence can be solved.

The present application relates to the technical field of computers, and provides an interruption control method and apparatus, an electronic device, a computer program, and a computer-readable storage medium. The method comprises: acquiring a first execution result of a design under test for a benchmark test program and a second execution result of a software emulator for the benchmark test program; and when an interruption condition is satisfied, interrupting the operation of the design under test, wherein the interruption condition comprises at least one of the following: the first execution result does not match the second execution result; a hardware buffer zone corresponding to the design under test is full; the hardware buffer zone is used for recording operation data of the design under test; a software buffer zone corresponding to the software emulator is empty; and the software buffer zone is used for recording operation data of the software emulator. According to embodiments of the present application, in hardware verification, the execution results of the design under test and the software emulator can be automatically compared and checked, and interruption can be automatically triggered, thereby achieving a better debugging capability.

According to the automatic test error-proofing detection method and detection system disclosed by the invention, after a test instruction is received, verification requests generated by bar codes of a needle bed upper mold and a needle bed lower mold are received; sending to a selected product test program to judge whether the needle bed upper die and the needle bed lower die and whether the needle bed name is matched with the current product test program or not; if not, stopping the test, otherwise, after the to-be-tested product is placed in place, receiving a serial number of the to-be-tested product generated by the bar code of the to-be-tested product, and querying and obtaining internal card binding information of the corresponding to-be-tested product; controlling the test tool to start and electrify the to-be-tested product, acquiring identity information of an internal clamping piece actually mounted in the to-be-tested product, comparing the identity information with inquired binding information of the internal clamping piece, if the identity information is consistent with the binding information of the internal clamping piece, carrying out subsequent function test, otherwise, sending error information of the internal clamping piece, and controlling the test tool to pull open an upper die and a lower die of the needle bed; therefore, automatic error-proofing detection of each module test of the industrial control system is realized.

The invention discloses a controller automatic test tool based on feature recognition and a test method thereof, and relates to the technical field of automatic test. The controller automation test tool comprises an image acquisition unit used for capturing display content of a controller screen; the electromechanical execution unit comprises a base positioning mechanism, a top pressing mechanism, a rear side butt joint mechanism, a key triggering mechanism set and a vibration mechanism. The control unit is respectively in communication connection with the image acquisition unit and the electromechanical execution unit, and is used for controlling the action of the electromechanical execution unit and receiving and analyzing the image information captured by the image acquisition unit; and the double-starting switch is connected with the control unit and needs to be synchronously triggered to start a test program. By integrating image acquisition and an electromechanical execution system, automatic identification of the display state of the controller screen and automatic execution of function operation are realized, and the consistency of the test efficiency and the test result is improved.

The invention discloses a system and a method for testing and analyzing the single event effect of a high-capacity nonvolatile memory. The system comprises an upper computer module, an FPGA (Field Programmable Gate Array) control module and a programmable power supply module. The system is used for testing and analyzing various single event effects of a high-capacity nonvolatile memory chip in a dynamic working mode. And according to the error data read from the memory in the dynamic working mode, presetting error bitmap rules of various single-particle function interruptions in an FPGA test program, carrying out real-time analysis and identification on the various single-particle function interruptions, and discriminating single-particle upset of the memory unit. According to the system, testing and real-time analysis of various complex single event effects of the high-capacity nonvolatile memory can be achieved, then radiation hardening and evaluation can be conducted on the sensitive position of a memory chip, and high pertinence is achieved.

The invention relates to the technical field of energy storage systems, and discloses an energy storage system upgrading test method and device, computer equipment and a storage medium, and the method comprises the steps: constructing an upgrading task on an Internet of Things platform through a preset test program; an OTA upgrading command is issued to at least one target device through the upgrading task, and the OTA upgrading command is used for controlling the target device to execute upgrading operation of the energy storage system; receiving progress data reported by the target equipment, and updating the running state of the target equipment on the display component according to the progress data until the upgrading operation is executed; and obtaining a state image of the display component, and determining whether the energy storage system in the target equipment is successfully upgraded according to the state image to obtain a test result. The problems that manual operation is tedious and prone to errors, upgrading judgment is inaccurate and success rate statistics is low in the CAN communication upgrading test of the BMS of the household storage battery pack are solved.

The invention provides a test system for prototype verification of a PCIE Switch switch chip. The system comprises an FPGA assembly, RC simulation equipment, EP simulation equipment and monitoring analysis equipment. In the application, the FPGA component integrates the tested component PCIE Switch and the test auxiliary component, supports hardware-level reconfiguration, can simulate topology and abnormal scenes of any RC device or EP device on the same platform, and does not need to replace physical hardware. Compared with an existing test system which depends on serial port log output faults, the method has the advantages that the error state is captured through FPGA hard logic, nanosecond fault tracing is achieved, and the test efficiency can be effectively improved. Besides, RC simulation equipment defines a test program through software, dynamically generates flow (such as normal / abnormal messages), and can replace physical RC equipment; the EP simulation device can respond to the test flow in real time, and can support multi-protocol version compatibility verification. Automatic testing of prototype verification of the PCIE Switch chip can be achieved through the monitoring and analyzing device, manual intervention is not needed, and input of testing manpower can be reduced.

The invention provides a chip testing method based on an ATE platform, and relates to the technical field of chip manufacturing and testing. According to the method, multiple advanced test technologies and intelligent algorithms are creatively integrated, test environment parameters are accurately controlled through an intelligent environment regulation and control system, radio frequency and digital signals are efficiently processed in cooperation with a test engine, a test execution stream optimizes a high-speed interface test by using a chip built-in Loopback function and an adaptive algorithm, and the test efficiency is improved. The intelligent control and analysis system dynamically adjusts a test process and accurately predicts chip defects based on a federal learning framework, and realizes Chiplet interconnection verification and closed-loop data analysis feedback optimization of a test program at the same time. The chip testing efficiency and precision are effectively improved, the testing cost is reduced, dependence on expensive equipment is reduced, the method can be widely applied to various chip testing scenes, and remarkable economic benefits and technical advantages are brought to chip manufacturing enterprises.

The invention provides a high and low temperature test box all-in-one machine, which comprises a box body assembly, an incubator inner box assembly, a refrigeration assembly, a power supply assembly and an operation panel assembly, and is characterized in that the top of the box body assembly is provided with the power supply assembly, the upper part of the box body assembly is internally provided with the incubator inner box assembly, and the lower part of the box body assembly is internally provided with the refrigeration assembly; the beneficial effects of the invention are that the device is simple to operate, is equipped with a touch display screen and an automatic control system, is convenient to use, can rapidly switch between a high temperature and a low temperature, greatly shortens the test period, and improves the work efficiency; through the high-precision temperature sensor and the controller, the environmental test box can ensure the accuracy of temperature control; the equipment can also store multiple groups of test programs, so that a user can conveniently perform repeated tests, and the test efficiency is improved; the equipment is provided with an automatic door opening and closing system, an incubator door can be opened and closed in a remote intelligent mode, and a robot can conveniently take and place a battery.

The invention provides a refrigerator factory performance automatic detection method and system, and the method comprises the steps: transmitting operation state data to a production test server in real time during the operation of a factory detection program through a built-in wireless communication module of a refrigerator; the production test server collects running state data of the multiple refrigerators which are judged to be qualified manually in a factory detection program, extracts a preset range of key parameters based on the running state data, and generates a test parameter set; and comparing the real-time operation state data of the refrigerator to be detected with the test parameter set, and if any key parameter exceeds a preset range, determining that the refrigerator is unqualified. The refrigerator is automatically connected with the production test server at the production line detection station, detection at the freezing stage, the refrigeration stage and the defrosting stage is executed in sequence, efficiency is high, maintenance cost is low, the requirement for variety diversification of refrigerators is met, test efficiency is improved, the problems that a traditional method is high in cost and low in efficiency are solved, the requirement for variety diversification of refrigerators is met, and product quality is improved. And the product quality stability is ensured.

The invention discloses a method for testing the comprehensive performance of an electrically-controlled silicone oil clutch water pump assembly. The method comprises the following steps: (1) installing the electrically-controlled silicone oil clutch water pump assembly to be tested on a test bench; (2) installing a test program in the control and data acquisition system, and inputting test parameters in the test program; (3) driving the tested fan of the electrically controlled silicone oil clutch water pump assembly by adopting controllable load equipment, and simulating the air resistance torque characteristics of the fan at different rotating speeds; and (4) starting the driving unit, controlling the load of the electrically-controlled silicone oil clutch and the working signal of the clutch according to the program, and testing various working conditions of the electrically-controlled silicone oil clutch. According to the method for testing the comprehensive performance of the electric control silicone oil clutch water pump assembly, comprehensive, efficient and accurate performance detection can be carried out on the electric control silicone oil clutch water pump assembly, product problems can be solved at an early stage, the product design is optimized, and the product quality is guaranteed.

The embodiment of the invention provides a fuzzy test method and device for an underwater control system communication protocol, and the method comprises the steps: defining each protocol field and an invariant segment according to a protocol description file, and generating input data meeting the protocol requirements; modeling a protocol interaction process based on the state diagram, and performing multi-path traversal in the state diagram based on input data; monitoring abnormity of network communication and a target process in operation of the fuzzy test program, obtaining feedback information, and adjusting the test case based on the feedback information; and according to the anomaly detection information in the test process, generating a standardized test report and a test case script capable of collapsing and reproducing.

To provide a testing terminal device, a testing system, and a testing program which can fairly perform testing.SOLUTION: An answering terminal device 2 used by a user who takes a test comprises: a capturing unit 24 which captures a confirmation image of the user during the test, for confirming legitimacy related to the test of the user; a recording unit 27 which stores the confirmation image captured by the capturing unit 24; an adjustment unit 281 which adjusts a capturing mode by the capturing unit 24, based on free capacity as remaining capacity in which information in the recording unit 27 is storable; and a processing unit 282 which makes the capturing unit 24 capture the confirmation image, based on the capturing mode adjusted by the adjustment unit 281. The capturing unit 24 captures a moving image or a still image of the user during the test, as a confirmation image.SELECTED DRAWING: Figure 4

The invention belongs to the technical field of network security protocol vulnerability mining, and discloses a protocol fuzz testing method and system based on a potential relationship between states, the method comprises the following steps: in a state modeling stage, tracking directed edges in a tested program state machine to generate a state bitmap, the state bitmap comprising state transition information; in the state selection stage, a state selection problem is modeled as a multi-arm machine optimization problem, and the optimization problem is solved by using an Epsilone-Greedy algorithm and a Thompson sampling algorithm in combination with state transition information. According to the method, the state bitmap is designed to represent the condition of inter-state migration, basic state information is reserved, meanwhile, representation of the state machine is simplified, the mapping relation between the tested protocol state machine and the state bitmap is established, inter-state migration is abstracted into state points in the state bitmap, and therefore the process of constructing and analyzing the tested protocol state machine is simplified.

The invention provides a test program generation method, electronic equipment and a storage medium, relates to the field of chips, and is mainly technically characterized by comprising the following steps: generating a plurality of subprograms corresponding to each module in at least two modules according to instruction characteristics of the at least two modules in a target processor; wherein each subprogram comprises dependency information with other subprograms, each subprogram comprises a plurality of instruction fragments, each instruction fragment comprises at least one instruction, and the dependency information of the subprogram is used for indicating whether the instruction fragment in the subprogram conflicts with the instruction fragments in other subprograms or not; the to-be-used instruction fragments are continuously selected until a preset ending condition is met, and the next to-be-used instruction fragment in every two adjacent to-be-used instruction fragments is the to-be-used instruction fragment which is sequentially selected from any subprogram of any module and does not conflict with the previous to-be-used instruction fragment; and obtaining a target test program according to a selection result of the to-be-used instruction fragment.

The invention provides a network testing system and method and a related device, and relates to the technical field of network testing. The system comprises a tested network system, a monitoring device and a control device, the tested network system comprises node devices, the node devices are connected through an Ethernet link, the monitoring device is connected with the tested network system through the Ethernet link, and the control device is connected with the monitoring device; the node equipment comprises tested node equipment; the test program of the tested node equipment responds to a first trigger instruction sent by the control equipment, and Ethernet data streams are sent to other node equipment; the monitoring equipment counts Ethernet data flow information sent by the detected node equipment and sends the Ethernet data flow information to the control equipment; and the control equipment sends a first trigger instruction to the test program, and detects the physical layer conflict avoidance function of the tested network system according to the Ethernet data flow information counted by the monitoring equipment. According to the invention, the network system can be tested, and the security of the network system is improved.

The invention belongs to the field of semiconductor testing, and provides a probe detection method and device and a storage medium. Coordinate measurement elements are obtained through software, an initial coordinate system is established, a needle head sub-coordinate system and a needle point sub-coordinate system are further established, a first probe test program is generated, translation copying is carried out based on the step pitch between probes to obtain a multi-probe test program, the multi-probe test program is summarized to form an overall test program, and the overall test program is automatically operated. And combining data analysis to complete screening of probes which do not accord with standards. According to the method, the problems that traditional manual measurement is high in subjectivity, low in efficiency and prone to damaging the probe are solved, rapid and accurate automatic detection and probe screening are achieved, the production efficiency is remarkably improved, and the labor cost and risk are reduced.

Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells connected to a plurality of word lines, respectively, a peripheral circuit configured to perform a test program operation and a pass bit detection operation of measuring a program speed of memory cells connected to a selected word line among the plurality of word lines during a test operation, and control logic configured to control the peripheral circuit to perform the test operation, and set a potential of a pass voltage to be used in a program operation, or a time point at which the pass voltage is to be applied, based on a number of times the test program operation is performed.

The invention relates to the technical field of semiconductor testing, and provides a chip test program generation method and device, electronic equipment and a storage medium. The method comprises the following steps: firstly, determining each piece of first test item information and / or each piece of second test item information of a to-be-tested chip according to test demand information; then obtaining a first test resource based on all the first test item information and a general library, and / or obtaining a second test resource based on all the second test item information and a target special library corresponding to the chip to be tested; then generating a test source code of the chip to be tested based on the first test resource and / or the second test resource; and finally, compiling and checking the test source code according to a grammar rule corresponding to the test machine type, and obtaining an executable code corresponding to the test source code under the condition of successful compiling and checking, thereby obtaining a test program of the to-be-tested chip. Automatic generation of the test program is realized, the development efficiency of the test program is improved, and the reliability and stability of the test program are ensured.

The invention provides an automatic testing method, device and platform for equipment load function performance, and relates to the technical field of software testing. According to the invention, through setting the plurality of subprogram packages in the process of testing the load function performance of the equipment, automatic programming is carried out according to the equipment type, the load type and the function type, the modularized combination generation of the test item, the test program and the subprogram is realized, the professional threshold is reduced, and the generation speed of the test program is improved. Furthermore, in combination with the task queue of the test accompanying instrument, path optimization is carried out on the test process, the test sequence of a plurality of test items is optimized, and the waiting time is shortened. Finally, based on the testing process and the testing program, automatic testing is achieved, the problem that the testing efficiency is low in the equipment load function performance testing process is solved, and the testing efficiency of the equipment load function performance testing is improved.

The invention relates to the technical field of PLC programming language testing in the field of industrial automation control, in particular to an IEC 61131-3-based PLC programming software language function full coverage testing method, which comprises the following steps: establishing a structured test table based on functions of five PLC programming languages; based on the content of the structured test table, a plurality of different function points to be tested are determined, and a test program complete set is determined based on the function points to be tested; the test program complete set is iteratively updated according to a test standard; importing the test program complete set into to-be-tested PLC programming software, and testing grammar analysis, compiling results and runtime behaviors to obtain test data; generating a technical list based on the test data; according to the invention, the test comprehensiveness of the PLC programming language can be improved.

The invention relates to a method for producing a product, said method having the steps of: providing specification data of the product, said specification data containing reference values for product features of the product; processing the product in a plurality of processing steps in accordance with the specification data; creating a test program which comprises a plurality of test criteria, each of which is assigned at least one of the product features; testing the product in accordance with the test criteria of the test program by testing the product features assigned to the test criteria, each reference value assigned to the product features being compared with corresponding actual values actually determined during the test, and collecting test data which indicates the result of the test and / or the actual values of the product features.

The invention relates to a chip testing system, device and method. The chip test system comprises a server and an embedded test device which are in communication connection. The server is configured to store a test program and load the stored test program to the embedded test device; the embedded test device is configured to run a test program so as to test one or more chips to be tested connected with the embedded test device, and the test program simultaneously tests the computing power load and the memory pressure of the chips to be tested in parallel when running. According to the chip testing system, device and method, the testing efficiency can be remarkably improved, and the real performance of the chip in an actual service scene can be accurately reflected.

The invention discloses a DRAM (dynamic random access memory) repairing method, an upper computer, a storage medium and a computer program product, and relates to the technical field of DRAM repairing, the DRAM repairing method comprises the following steps: inputting a test program to a main control chip to enable the main control chip to test DRAM particles based on the test program, and determining fault information of the DRAM particles according to a test result; wherein the test program runs in an SRAM (Static Random Access Memory) in the main control chip; generating a corresponding repair program according to the fault information, and verifying the validity of the repair program; and under the condition that the repair program is verified to be valid, repairing the DRAM particles according to the repair program. According to the method and the device, the DRAM can be repaired on the premise of not depending on normal work of the DRAM.

The invention discloses a test and evaluation method for a virtualization system in multiple scenes, which comprises the following steps: deploying an executable file compiled by a test script at a virtualization client, and testing the performance of a client operating system to judge the performance loss of the virtualization system to computer resources. The method comprises the following steps: step 1, creating a project, and configuring system parameters; 2, integrating a test program into a project, and generating a mirror image file; step 3, packaging a complete virtualization system mirror image; 4, transmitting the mirror image to a development board through a network protocol; 5, executing a command to start a system, and logging in a system console through a serial port; and 6, calling and executing the function test script, the performance test script and the security test script.