176 results about "Ic devices" patented technology

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

A semiconductor IC device (50) includes a conductive through device connection. The connection may be located within a double diffusion break (DDB) region (51) separating the active regions (52, 53). The connection may include a dummy S / D region (24) between the front contact (30) and the back contact (32). The semiconductor IC device may further include a first (20) and / or a second diffusion interruption isolation rail (22). A connection may be between the first and second diffusion-interrupting isolation rails. The connection locations within the DDB region thus increase the packaging density of the semiconductor IC device. In addition, the connection may reduce wiring complexity and resistance through the semiconductor IC device, which may improve semiconductor IC device performance. Furthermore, the connections may utilize structural instances (e.g., front contacts, back contacts, dummy S / D regions, etc.) mirrored with structural instances used by micro devices (e.g., transistors, etc.) within the active region, which may reduce manufacturing complexity.

Isolation structures between transistors in integrated circuit (IC) devices. An IC device includes transistors coupled to an interconnect network, and between the transistors a dielectric structure with a wider width away from the interconnect network and a narrower width nearer the interconnect network. Dielectric structures with wider back-side widths may separate gate electrodes and / or source and drain contacts of the transistors. The dielectric structures may be formed by etching an opening between metallization structures of the transistors from a back side of the device substrate and by depositing liner and fill dielectrics over the back-side opening.

An integrated circuit (IC) device includes a plurality of chiplets including a first device and a second device. A die-to-die (D2D) interconnect link connects between the first device and the second device. A link training and status state machine (LTSSM) of the IC device is configured to operate the degraded D2D interconnect link in a resilient link mode to provide a plurality of enabled lanes and a plurality of disabled lanes. The LTSSM detects a faulty lane among the plurality of enabled lanes, and replaces the faulty lane using a functional lane from the plurality of disabled lanes to maintain the degraded D2D interconnect link.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.

IC devices implementing 2T memory cells with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. 2T memory cells with read and write transistors provided in different planes of an IC device, stacked substantially over one another, and having either the read transistors or the write transistors being angled transistors provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

A method for provisioning a plurality of IC devices, the method including: providing, by a first entity, the plurality of IC devices; storing, by the first entity, in one of the plurality of IC devices used as a provisioning device, one or more keys, and a public key, wherein the one or more keys include a reprovisioning key for reprovisioning the remaining IC devices; installing, by the first entity, provisioning software in the provisioning device; signing, by the first entity, provisioning software using a private key, the private key corresponding to the public key; provisioning the remaining IC devices by the provisioning device including providing cryptographic assets to the remaining IC devices, wherein the cryptographic assets include cryptographic code and keys; and reserving space in the remaining IC devices for reprovisioning the remaining IC devices with updated cryptographic assets.

An apparatus and method for low page overhead recompression. In one embodiment a memory buffer integrated circuit (IC) device is disclosed that includes a first circuit configured to independently compress equally sized portions of a page of data, and a second circuit configured to store the compressed data portions at respective addresses in memory. The memory buffer IC device also includes a third circuit configured to store a page table comprising an entry with information related to the respective memory addresses.

An IC device includes a static random access memory device (SRAM device) positioned in a substrate, wherein the SRAM device comprises a first complementary field-effect transistor (CFET) having a first pass-gate transistor positioned at a first height, a second CFET having a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height, a third CFET having a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height, and a fourth CFET having a second pass-gate transistor positioned at the first height.Each of the first and second pull-down transistors has a gate extending in a gate direction and having a first output working configuration, and each of the first and second pass-gate transistors has a gate extending in the gate direction and having a second output working configuration that differs from the first output working configuration.

Integrated circuit (IC) devices having shared, dual-metal gates for complementary transistors. An IC device includes a shared gate structure over first and second stacks of nanoribbons with complementary conductivities and a substrate, and the gate structure includes first, second, and third gate metals with the first gate metal over and around the nanoribbons in the first stack, the second gate metal over and around the nanoribbons in the second stack, and the third gate metal around and between the nanoribbons in the first stack, between the first and second stacks, in contact with both the first and second gate metals, and extending beyond the first metal over the substrate. The first gate metal may act as a temple for selective deposition of the third gate metal. The second gate metal may be conformally deposited over the nanoribbons in the second stack and on the third gate metal.

Disclosed herein are IC devices with 3D interlocked corrugated capacitor structures. An example IC device includes a support structure (e.g., a substrate, a die, a wafer, or a chip), an insulator material over the support structure, and a first and a second corrugated capacitor structures extending into the insulator material, where a projection of at least one of the protrusions of the first corrugated capacitor structure onto a plane parallel to the support structure overlaps with a projection of at least one of the protrusions of the second corrugated capacitor structure onto the plane.

A stacked integrated circuit (IC) device (100) includes a first die (110) having a first face (112), a first active region (116) adjacent the first face, and a first die interconnect contact (122) disposed on the first face and connected to a first circuit. The stacked IC device includes a second die (130) having a second face (132), a second active region (136) adjacent the second face, and a second die interconnect contact (142) disposed on the second face and connected to a second circuit. The first face is oriented toward the second face, and the first die interconnect contact is connected to the second die interconnect contact. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face (124), the second face (144), or both. The stacked IC device also includes an interconnect conductor connected to the redistribution layer to provide a signal path from the first die (122), the second die (142), or both to a set of external contacts (162).

Methods for forming via openings by using a lamellar triblock copolymer, a polymer nanocomposite, and a mixed epitaxy approach are disclosed. An example method includes forming a guiding pattern (e.g., a topographical guiding pattern, chemical guiding pattern, or mixed guiding pattern) on a surface of a layer of an IC device, forming lamellar structures based on the guiding pattern by using the lamellar triblock copolymer or forming cylindrical structures based on the guiding pattern by using the polymer nanocomposite, and forming via openings by removing a lamella from each of at least some of the lamellar structures or removing a nanoparticle from each of at least some of the cylindrical structures.

An integrated sensor array device and method. The method includes providing a partially completed semiconductor substrate having a material stack used to form a sensor array device with a plurality of device regions. One or more isolation trench regions separating the device regions can be formed in a front-end isolation process during the formation of the device regions or in a back-end isolation process following a bonding process to integrate the sensor array device to an integrated circuit (IC) device. Prior to the front-end or back-end processing, metal interconnect materials within a passivation material can be formed via a planarization process to provide connection to n-type and p-type contact regions of the sensor array device. The resulting planarized sensor array device can then be bonded to the IC device, and a plurality of surface relief structures can be formed overlying a backside surface region of the planarized sensor array device.

Isolation structures between transistors in integrated circuit (IC) devices. An IC device includes transistors coupled to an interconnect network, and between the transistors a dielectric structure with a wider width away from the interconnect network and a narrower width nearer the interconnect network. Dielectric structures with wider back-side widths may separate gate electrodes and / or source and drain contacts of the transistors. The dielectric structures may be formed by etching an opening between metallization structures of the transistors from a back side of the device substrate and by depositing liner and fill dielectrics over the back-side opening.

IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.

In an aspect there is provided a 3D IC device comprising: a package wiring plane comprising a global VDD voltage node and a global VSS voltage node; a die stack arranged over the package wiring plane and comprising a number of stacked dies stacked on top of each other; a metal interconnect layer arranged on top of a top stacked die of the die stack; and a pass-through interconnect extending vertically through each stacked die of the die stack and connecting the metal interconnect layer to the global VDD voltage node; wherein each stacked die of the die stack has a bottom side and a top side, a local VDD voltage contact on its top side and a local VSS voltage contact on its bottom side.

An integrated circuit (IC) device may implement a deep neural network (DNN). The IC device may include an activator unit that implements a nonlinear activation function in the DNN. The nonlinear activation function may be decomposed into a rectified linear unit (ReLU) function and a symmetric function. After receiving an input value, the activator unit may apply the ReLU function on the input value to compute a first value. The input range of the nonlinear activation function may be partitioned into segments. The activator unit may determine which segment the input value falls into. The activator unit may apply a linear function, which approximates the symmetric function within the segment, on the input value to compute a second value. The activator unit may correct an error in the second value and compute an output of the nonlinear activation function based on the first value and the second value.

An IC device includes a first complementary field-effect transistor (CFET) static random-access memory (SRAM) cell in a semiconductor wafer, the first CFET SRAM cell including a first internal node and a first pass gate including a first source / drain (S / D) region and a second S / D region electrically connected to the first internal node, and a second CFET SRAM cell in the semiconductor wafer, the second CFET SRAM cell including a second internal node and a second pass gate including a third S / D region and a fourth S / D region electrically connected to the second internal node, wherein the first S / D region is aligned with the third S / D region in a direction perpendicular to a frontside of the semiconductor wafer and a backside of the semiconductor wafer

An IC device includes isolation structures extending between two locations along a first direction in a front side of a semiconductor substrate, transistors including gates and MD segments extending between the two locations and being entireties of gates and MD segments positioned between the two locations and between the isolation structures in a second direction perpendicular to the first direction, frontside gate vias being an entirety of frontside gate vias electrically connected to the gates, and frontside S / D vias being an entirety of frontside S / D vias electrically connected to the MD segments. All of the frontside gate vias are positioned at locations of first and / or second tracks of first through third layer tracks extending in the second direction and being an entirety of lowermost frontside metal layer tracks positioned between the two locations, and all of the frontside S / D vias are positioned at locations of the second and / or third tracks.

Integrated circuit (IC) devices having gate-all-around (GAA) transistors. An IC device may include adjacent GAA transistors with gate electrodes having different gate dielectric stacks separated by a dielectric wall. The gate dielectric stacks may include inner gate dielectric layers on nanoribbon channels and outer gate dielectric layers on the inner gate dielectric layers. The inner gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The outer gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The dielectric wall between gate electrodes and gate dielectric stacks may enable independent processing of the transistors gates by dividing the nanoribbon channels into separate gate tubs.

Integrated circuit (IC) devices having shared, dual-metal gates for complementary transistors. An IC device includes a shared gate structure over first and second stacks of nanoribbons with complementary conductivities and a substrate, and the gate structure includes first, second, and third gate metals with the first gate metal over and around the nanoribbons in the first stack, the second gate metal over and around the nanoribbons in the second stack, and the third gate metal around and between the nanoribbons in the first stack, between the first and second stacks, in contact with both the first and second gate metals, and extending beyond the first metal over the substrate. The first gate metal may act as a temple for selective deposition of the third gate metal. The second gate metal may be conformally deposited over the nanoribbons in the second stack and on the third gate metal.

An integrated circuit (IC) device includes a die (102) including a silicon region (104) having a coefficient of thermal expansion (CTE silicon), and a conductive contact (106) on a first side of a first die. An encapsulant (120) laterally adjacent to the silicon region of the first die has a coefficient of thermal expansion (CTE encapsulant), wherein a mismatch between the CTE silicon and the CTE encapsulant defines a thermal stress interface (124) between the silicon region and the encapsulant. The IC device includes a dielectric layer (130) formed on the first die and the encapsulant, and includes a dielectric spacer region (134) over and extending laterally across the thermal stress interface. The IC device includes a redistribution layer (RDL) (140) including an RDL element (142) formed on the dielectric spacer region and electrically connected to the conductive contact through an opening (132) in the dielectric layer, where the RDL element is physically spaced from the thermal stress interface by the dielectric spacer region.

An integrated circuit (IC) device may implement a contextual embedding model. The IC device may include a tokenizer unit, embedder unit, layer normalizer unit, dot unit, activator units, and flow control unit. The tokenizer unit may implement a tokenizer in the model and convert text to tokens using the vocabulary of the model. The embedder unit may implement embedders in the model and generate embeddings from the tokens. The layer normalizer unit may implement one or more layer normalizers in the model and compute embedding vectors. The dot unit may implement matrix multiplication and add operations in the encoders and pooler of the model. The activator units may implement activation functions, including tanh function, in the model. The flow control unit may orchestrate the other components of the IC device based on a timing sequence of neural network operations in the model.

Having an IC device: a semiconductor substrate (137); a photodiode (143) formed in the semiconductor substrate (137); a metal compound structure (155) formed on the semiconductor substrate (137); and a reflector (153) formed in the metal compound structure (155) above the photodiode (143), where the reflector (153) is grounded, wherein the reflector (153) is grounded to the semiconductor substrate (137), where the reflector (153) is attached to a P + -doped area (149) of the semiconductor substrate (137) is grounded, where the P + -doped area (149) of the semiconductor substrate (137) is part of the photodiode (143).

Some embodiments relate to an integrated circuit (IC) device that includes a substrate including a P-well region and a dielectric structure. The dielectric structure is disposed at a surface of the substrate, extends downward into the substrate, and is located at a lateral perimeter of the P-well region. The IC device further includes a dielectric layer disposed over the P-well region and extends laterally over the dielectric structure. The IC device also includes an N+ gate structure disposed over the dielectric layer and includes at least one P+ region located over the P-well region of the substrate and the dielectric structure.

IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. Similarly, a routing track is referred to as an “angled routing track” if the routing track is neither perpendicular nor parallel to any edges of front or back faces of the support structure. Angled transistors and angled routing tracks provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and / or decreasing adverse effects associated with continuous scaling of IC components.

Integrated circuits (ICs) with gate-all-around field-effect transistors (GFEs) featuring nanoband channels through the gate electrodes. An IC device has a stack of nanoband channels through a gate electrode, and the gate electrode has uniform gate thicknesses of gate metal and dielectric layers between, above, and below each of the nanobands. The nanobands extend between pairs of gate spacers to couple the source and drain bodies, with matching gate spacers positioned above and below each of the nanobands. A second pair of gate spacers is located on top of and above a topmost pair of the first gate spacers. A sacrificial cap layer is applied over one of the topmost channel layers during processing, and the end portions of the cap layer are retained as second gate spacers.

This utility model discloses a multi-layer potting structure for a high-voltage sensor, relating to the technical field of voltage sensor potting structures. It aims to solve the problem of electro-corrosion of IC devices caused by the aging of internal filling materials in existing sensors, ultimately leading to severe and unstable zero-point drift in the voltage sensor. The key technical solution includes a circuit board with components fixedly connected to its upper end. The components are coated with a conformal coating, and a silicone protective layer is fixedly connected to the outside of the conformal coating. A polytetrachloroethylene (PTFE) shell for protection is fixedly connected to the outside of the silicone protective layer, and a high-pressure epoxy adhesive layer is fixedly connected to the outside of the PTFE shell, achieving sufficient and multi-level protection.