308 results about "Ic devices" patented technology

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

A semiconductor IC structure includes a stacked transistor that has a top transistor stacked upon a bottom transistor. The bottom transistor includes at least a bottom source / drain region. The semiconductor IC structure further includes a replacement bottom source / drain region contact that includes a deep via region through at least the top semiconductor IC device and a monolithic region within the bottom semiconductor IC device directly coupled against a top surface of the bottom source / drain region. There is no interfacial impedance between the deep via region and the monolithic region. For example, there is no liner (e.g., such as a diffusion barrier, adhesion liner, or the like) between the deep via region and the monolithic region.

An IC device includes an active area extending in a first direction in a front side of a semiconductor substrate, a first gate electrode overlying the active area and extending in a second direction perpendicular to the first direction, a metal-like defined (MD) segment extending in the second direction adjacent to the first gate electrode and overlying the active area, and a first feed-through via (FTV) directly contacting one of the first gate electrode or the MD segment and extending in a third direction perpendicular to the first and second directions to a back side of the semiconductor substrate.

Described herein are transistors with front-side and back-side routing, and IC devices including such transistors. The transistor includes a channel material having a longitudinal structure and formed in a dielectric material. A source region encloses a first portion of the channel material, a gate electrode encloses a second portion of the channel material, and a drain region encloses a third portion of the channel material. Each of the source region, gate electrode, and drain region have a first face and a second face opposite the first face, the first and second faces co-planar with the faces of the dielectric material. A first contact is coupled to the first face of the source region, and a second contact is coupled to the second face of the source region.

Voltage droop is mitigated within an integrated circuit (IC) device including a first processing device and scheduler circuitry. The first processing device executes operations of a first workload. The first processing device is associated with a first processing device voltage droop characteristic. The scheduler circuitry receives the first workload. The first workload is associated with a first workload voltage droop characteristic. Further, the scheduler circuitry assigns the first workload to the first processing device of the IC device based on the first workload voltage droop characteristic and the first processing device voltage droop characteristic.

A semiconductor IC device (50) includes a conductive through device connection. The connection may be located within a double diffusion break (DDB) region (51) separating the active regions (52, 53). The connection may include a dummy S / D region (24) between the front contact (30) and the back contact (32). The semiconductor IC device may further include a first (20) and / or a second diffusion interruption isolation rail (22). A connection may be between the first and second diffusion-interrupting isolation rails. The connection locations within the DDB region thus increase the packaging density of the semiconductor IC device. In addition, the connection may reduce wiring complexity and resistance through the semiconductor IC device, which may improve semiconductor IC device performance. Furthermore, the connections may utilize structural instances (e.g., front contacts, back contacts, dummy S / D regions, etc.) mirrored with structural instances used by micro devices (e.g., transistors, etc.) within the active region, which may reduce manufacturing complexity.

Liquid metal (LM) interconnects have angled features to reduce reflection loss and / or insertion loss of signals sent across the interconnects. The LM interconnects may be used to couple two electronic components, e.g., to physically and electrically couple an IC device and a circuit board together. One component has an array of LM wells, and the second component has a corresponding array of pins. The LM wells have tapered shapes, e.g., tapered sidewalls with LM within the sidewalls. A cap layer along seals the wells to hold the LM inside the wells. The pins on the second component have a flared portion that widens in the direction of the second component and tapers in the direction of the tip. When a pin is inserted into a corresponding LM well, the tip and straight (e.g., cylindrical) sections may be within the LM well, while the flared portion remains within the cap layer.

Isolation structures between transistors in integrated circuit (IC) devices. An IC device includes transistors coupled to an interconnect network, and between the transistors a dielectric structure with a wider width away from the interconnect network and a narrower width nearer the interconnect network. Dielectric structures with wider back-side widths may separate gate electrodes and / or source and drain contacts of the transistors. The dielectric structures may be formed by etching an opening between metallization structures of the transistors from a back side of the device substrate and by depositing liner and fill dielectrics over the back-side opening.

An integrated circuit (IC) device includes a plurality of chiplets including a first device and a second device. A die-to-die (D2D) interconnect link connects between the first device and the second device. A link training and status state machine (LTSSM) of the IC device is configured to operate the degraded D2D interconnect link in a resilient link mode to provide a plurality of enabled lanes and a plurality of disabled lanes. The LTSSM detects a faulty lane among the plurality of enabled lanes, and replaces the faulty lane using a functional lane from the plurality of disabled lanes to maintain the degraded D2D interconnect link.

A integrated circuit (IC) package device includes a first substrate, an IC device mounted to a first surface of the first substrate, a second substrate, and first power delivery circuitry. The second substrate is mounted to a second surface of the first substrate. The first surface is opposite the second surface. The second substrate includes a decoupling capacitor. The first power delivery circuitry is mounted to the second substrate and coupled to the IC device through the second substrate and the first substrate.

Integrated circuit (IC) devices implementing bilayer memory stacking with compute logic circuits shared between bottom and top memory layers are disclosed. An example IC device includes a first IC structure that includes one or more memory layers but not necessarily compute logic circuits, the first IC structure being bonded with a second IC structure that includes at least one layer of compute logic circuits and further includes one or more memory layers stacked above the compute logic circuits. The first and second IC structures may be bonded so that the compute logic circuits of the second IC structure may be communicatively coupled to memory layers of both the first and second IC structures.

An integrated circuit (IC) device may implement a speech recognition model with a transformer-based architecture. The IC device may include an embedder unit, etched mind unit(s), a layer normalizer unit, a sampler unit, and a flow control unit. The embedder unit may be a hardware implementation of an embedder in the model. The etched mind unit(s) may be a hardware implementation of matrix multiplications and additions in the model. The layer normalizer unit may implement a layer normalizer in the model. The sampler unit may implement a sampler in the model. The sampler unit may use comparators to find the largest value of a vector received from the etched mind unit(s). The sampler unit may determine the index of the largest value and output a predicted token. The flow contour unit may orchestrate the other components of the IC device based on a timing sequence of the model.

An example IC device includes a plurality of vertical transistors which may be part of memory cells, thus realizing vertical-transistor based memory. The IC device further includes a wordline, electrically continuous along a first longitudinal axis and electrically coupled to gates of a first subset of the transistors, and a control line that may be either a bitline or a plateline, electrically continuous along a second longitudinal axis and wrapping around at least portions of channel materials of a second subset of the transistors, where the first subset and the second subset have one transistor in common. At least one of the first longitudinal axis and the second longitudinal axis is not parallel to any edges or borders of the support structure, and, as a result, such a memory is referred to as “diagonal memory.” The transistors may be hysteretic transistors and / or may be further coupled to hysteretic capacitors.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.

A method can include receiving a first power supply voltage at a first terminal substantially at a first side of an IC device; providing first and second rows of insulated gate field effect transistors (IGFETs) substantially at a second side of the IC device, each IGFET including first and second source / drains (S / Ds), channels, and a control gate that substantially surrounds the channels. A first power supply voltage can be coupled from the first terminal to an S / D of an IGFET in the first row via a first conductive via disposed between the first side and the second side and a first conductive line buried in and proximate the second side. IGFETs of the first row can have a first conductivity type. IGFETs of the second row can have a second conductivity type. Corresponding devices and systems are also disclosed.

An IC device design system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs, the storage medium and the code being configured to, with the processor, cause the system to receive an IC device layout diagram including a gate region having a width extending at least from a first edge of an active region to a second edge of the active region and a gate via at a location within the active region and along the width, receive a first gate resistance value corresponding to the gate region, retrieve a second gate resistance value from a resistance value reference based on the location and the width, and based on the second gate resistance value being greater than the first gate resistance value, add a gate terminal node and a resistor to a netlist corresponding to the gate region.

IC devices implementing 2T memory cells with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. 2T memory cells with read and write transistors provided in different planes of an IC device, stacked substantially over one another, and having either the read transistors or the write transistors being angled transistors provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

A method for provisioning a plurality of IC devices, the method including: providing, by a first entity, the plurality of IC devices; storing, by the first entity, in one of the plurality of IC devices used as a provisioning device, one or more keys, and a public key, wherein the one or more keys include a reprovisioning key for reprovisioning the remaining IC devices; installing, by the first entity, provisioning software in the provisioning device; signing, by the first entity, provisioning software using a private key, the private key corresponding to the public key; provisioning the remaining IC devices by the provisioning device including providing cryptographic assets to the remaining IC devices, wherein the cryptographic assets include cryptographic code and keys; and reserving space in the remaining IC devices for reprovisioning the remaining IC devices with updated cryptographic assets.

Methods of forming a back-end-of-line (BEOL) region of an integrated circuit (IC) device are provided. A method of forming a BEOL region of an IC device includes forming a metal layer on a lower via. The method includes forming a photo key in an upper portion of the metal layer. The method includes forming an insulating material on the photo key. Moreover, the method includes planarizing the insulating material and the metal layer that includes the photo key.

A stacked integrated circuit (IC) device includes a first die including active circuitry and a power distribution network (PDN). The first die has a first set of contacts on a first side of the first die. The stacked IC device also includes a second die coupled to the first side of the first die on the first side of the second die. The second die also includes a second set of contacts on a second side of the second die to electrically connect circuitry of the second die to the substrate. The stacked IC device also includes an integrated capacitor device (ICD) coupled to the first side of the first die. The ICD is electrically connected to the PDN via a first set of contacts and includes one or more through ICD conductors to electrically connect the PDN to a substrate.

An apparatus and method for low page overhead recompression. In one embodiment a memory buffer integrated circuit (IC) device is disclosed that includes a first circuit configured to independently compress equally sized portions of a page of data, and a second circuit configured to store the compressed data portions at respective addresses in memory. The memory buffer IC device also includes a third circuit configured to store a page table comprising an entry with information related to the respective memory addresses.

An IC device includes a static random access memory device (SRAM device) positioned in a substrate, wherein the SRAM device comprises a first complementary field-effect transistor (CFET) having a first pass-gate transistor positioned at a first height, a second CFET having a first pull-down transistor positioned at the first height and a first pull-up transistor positioned at a second height, a third CFET having a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height, and a fourth CFET having a second pass-gate transistor positioned at the first height.Each of the first and second pull-down transistors has a gate extending in a gate direction and having a first output working configuration, and each of the first and second pass-gate transistors has a gate extending in the gate direction and having a second output working configuration that differs from the first output working configuration.

Integrated circuit (IC) devices having shared, dual-metal gates for complementary transistors. An IC device includes a shared gate structure over first and second stacks of nanoribbons with complementary conductivities and a substrate, and the gate structure includes first, second, and third gate metals with the first gate metal over and around the nanoribbons in the first stack, the second gate metal over and around the nanoribbons in the second stack, and the third gate metal around and between the nanoribbons in the first stack, between the first and second stacks, in contact with both the first and second gate metals, and extending beyond the first metal over the substrate. The first gate metal may act as a temple for selective deposition of the third gate metal. The second gate metal may be conformally deposited over the nanoribbons in the second stack and on the third gate metal.

Integrated circuit (IC) structures including backend switches for inter-die connectivity are disclosed. In one example, an IC device includes a first device region and a second device region over a substrate (e.g., discrete device regions or dies), and a backend transistor (e.g., a backend transistor over one or more metal layers over the substrate), where the backend transistor is coupled with the first device region and the second device region. In one example, the first device region and the second device region may be coplanar device regions separated by a scribe region or stacked device regions. In one example, the pitch and / or thickness of a metal layer over the backend switch is smaller than the pitch and / or thickness of a layer below the backend switch.

Disclosed herein are IC devices with 3D interlocked corrugated capacitor structures. An example IC device includes a support structure (e.g., a substrate, a die, a wafer, or a chip), an insulator material over the support structure, and a first and a second corrugated capacitor structures extending into the insulator material, where a projection of at least one of the protrusions of the first corrugated capacitor structure onto a plane parallel to the support structure overlaps with a projection of at least one of the protrusions of the second corrugated capacitor structure onto the plane.

In an aspect, an IC device may include a base substrate including an embedded component and a first metallization structure. The first metallization structure includes a plurality of first metal layers, a plurality of first dielectric layers, a plurality of first vias configured to couple adjacent metal layers of the plurality of first metal layers through the plurality of first dielectric layers and a reserve capacitor disposed within one of the plurality of first dielectric layers. The reserve capacitor directly coupled between a first contact pad and a second contact pad formed in one of the plurality of first metal layers, and electrically coupled to the embedded component.

A stacked integrated circuit (IC) device (100) includes a first die (110) having a first face (112), a first active region (116) adjacent the first face, and a first die interconnect contact (122) disposed on the first face and connected to a first circuit. The stacked IC device includes a second die (130) having a second face (132), a second active region (136) adjacent the second face, and a second die interconnect contact (142) disposed on the second face and connected to a second circuit. The first face is oriented toward the second face, and the first die interconnect contact is connected to the second die interconnect contact. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face (124), the second face (144), or both. The stacked IC device also includes an interconnect conductor connected to the redistribution layer to provide a signal path from the first die (122), the second die (142), or both to a set of external contacts (162).

Methods for forming via openings by using a lamellar triblock copolymer, a polymer nanocomposite, and a mixed epitaxy approach are disclosed. An example method includes forming a guiding pattern (e.g., a topographical guiding pattern, chemical guiding pattern, or mixed guiding pattern) on a surface of a layer of an IC device, forming lamellar structures based on the guiding pattern by using the lamellar triblock copolymer or forming cylindrical structures based on the guiding pattern by using the polymer nanocomposite, and forming via openings by removing a lamella from each of at least some of the lamellar structures or removing a nanoparticle from each of at least some of the cylindrical structures.

An integrated sensor array device and method. The method includes providing a partially completed semiconductor substrate having a material stack used to form a sensor array device with a plurality of device regions. One or more isolation trench regions separating the device regions can be formed in a front-end isolation process during the formation of the device regions or in a back-end isolation process following a bonding process to integrate the sensor array device to an integrated circuit (IC) device. Prior to the front-end or back-end processing, metal interconnect materials within a passivation material can be formed via a planarization process to provide connection to n-type and p-type contact regions of the sensor array device. The resulting planarized sensor array device can then be bonded to the IC device, and a plurality of surface relief structures can be formed overlying a backside surface region of the planarized sensor array device.

The application relates to a packaging structure of a power IC device, which comprises a heat sink, a substrate, a chip, a packaging layer and two or more spring screws; the substrate is arranged on the top surface of the heat sink, and the chip is arranged on the top surface of the substrate; the packaging layer is arranged on the substrate and wraps the chip, a preset distance is arranged between the packaging layer and the heat sink to form a deformation accommodating area; one surface of the substrate connected with the heat sink is provided with a connecting part, and the contact area of the connecting part with the heat sink is smaller than the contact area of the connecting part with the substrate; and the packaging layer is fixedly connected with the heat sink through the two or more spring screws. The preset distance is arranged between the packaging layer and the heat sink to form the deformation accommodating area; when the packaging layer expands due to temperature rise, the deformation accommodating area can provide sufficient deformation space for the packaging layer, so that the packaging layer is prevented from pulling apart the heat sink and the substrate when the packaging layer expands and directly contacts the heat sink.