462 results about "Ic devices" patented technology

IC devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on / in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of such edges. Angled transistors provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips.

A stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, and first die-interconnect contacts disposed on the first face and connected to first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, and second die-interconnect contacts disposed on the second face and connected to second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

An integrated circuit (IC) device has a memory region in which a plurality of memory cells is implemented. Each of the memory cells has a first dimension in a first horizontal direction. The IC device includes an edge region bordering the memory cell region in the first horizontal direction. The edge region has a second dimension in the first horizontal direction. The second dimension is less than or equal to about 4 times the first dimension. The IC device is formed by revising a first IC layout to generate a second IC layout. The second IC layout is generated by shrinking a dimension of the edge region in the first horizontal direction.

The embodiments of the present disclosure recognize the potential benefits of semiconductor IC device fabrication techniques to form a microdevice, such as a transistor, that includes structures, such as a source and / or drain, that are to be connected to a backside contact that is further associated with a backside back end of line (BEOL) network. The semiconductor IC device includes a bottom isolation extension (BIE) region. The BIE region is formed within a gate structure of the microdevice and may be located between the backside contact and the gate structure. The BIE region may provide for increased electrical isolation between the backside contact and the gate structure.

In an aspect, an IC device may include a structure wafer and a first die bonded to the structure wafer by a bonding layer. A first metallization structure is disposed below and electrically coupled to the first die opposite the structure wafer. A fill material is disposed between the structure wafer and the first metallization structure. A second metallization structure is disposed on top of the structure wafer. The second metallization structure includes a second plurality of inorganic dielectric layers. A second die is disposed on top of the second metallization structure and electrically coupled to the second metallization structure by a plurality of die connectors. A plurality of throughsubstrate vias electrically couple the first metallization structure to the second metallization structure.

An IC device includes a first interconnect structure configured to distribute a power supply voltage, a second interconnect structure configured to distribute a reference voltage, a third interconnect structure configured to distribute a first power gating signal, and a plurality of logic circuits. Each logic circuit of the plurality of logic circuits includes a power switch coupled in series with a logic gate between the first and second interconnect structures, and the power switch includes a control terminal coupled to the third interconnect structure.

A semiconductor IC structure includes a stacked transistor that has a top transistor stacked upon a bottom transistor. The bottom transistor includes at least a bottom source / drain region. The semiconductor IC structure further includes a replacement bottom source / drain region contact that includes a deep via region through at least the top semiconductor IC device and a monolithic region within the bottom semiconductor IC device directly coupled against a top surface of the bottom source / drain region. There is no interfacial impedance between the deep via region and the monolithic region. For example, there is no liner (e.g., such as a diffusion barrier, adhesion liner, or the like) between the deep via region and the monolithic region.

An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

An IC device includes an active area extending in a first direction in a front side of a semiconductor substrate, a first gate electrode overlying the active area and extending in a second direction perpendicular to the first direction, a metal-like defined (MD) segment extending in the second direction adjacent to the first gate electrode and overlying the active area, and a first feed-through via (FTV) directly contacting one of the first gate electrode or the MD segment and extending in a third direction perpendicular to the first and second directions to a back side of the semiconductor substrate.

Described herein are transistors with front-side and back-side routing, and IC devices including such transistors. The transistor includes a channel material having a longitudinal structure and formed in a dielectric material. A source region encloses a first portion of the channel material, a gate electrode encloses a second portion of the channel material, and a drain region encloses a third portion of the channel material. Each of the source region, gate electrode, and drain region have a first face and a second face opposite the first face, the first and second faces co-planar with the faces of the dielectric material. A first contact is coupled to the first face of the source region, and a second contact is coupled to the second face of the source region.

Voltage droop is mitigated within an integrated circuit (IC) device including a first processing device and scheduler circuitry. The first processing device executes operations of a first workload. The first processing device is associated with a first processing device voltage droop characteristic. The scheduler circuitry receives the first workload. The first workload is associated with a first workload voltage droop characteristic. Further, the scheduler circuitry assigns the first workload to the first processing device of the IC device based on the first workload voltage droop characteristic and the first processing device voltage droop characteristic.

A semiconductor IC device (50) includes a conductive through device connection. The connection may be located within a double diffusion break (DDB) region (51) separating the active regions (52, 53). The connection may include a dummy S / D region (24) between the front contact (30) and the back contact (32). The semiconductor IC device may further include a first (20) and / or a second diffusion interruption isolation rail (22). A connection may be between the first and second diffusion-interrupting isolation rails. The connection locations within the DDB region thus increase the packaging density of the semiconductor IC device. In addition, the connection may reduce wiring complexity and resistance through the semiconductor IC device, which may improve semiconductor IC device performance. Furthermore, the connections may utilize structural instances (e.g., front contacts, back contacts, dummy S / D regions, etc.) mirrored with structural instances used by micro devices (e.g., transistors, etc.) within the active region, which may reduce manufacturing complexity.

Liquid metal (LM) interconnects have angled features to reduce reflection loss and / or insertion loss of signals sent across the interconnects. The LM interconnects may be used to couple two electronic components, e.g., to physically and electrically couple an IC device and a circuit board together. One component has an array of LM wells, and the second component has a corresponding array of pins. The LM wells have tapered shapes, e.g., tapered sidewalls with LM within the sidewalls. A cap layer along seals the wells to hold the LM inside the wells. The pins on the second component have a flared portion that widens in the direction of the second component and tapers in the direction of the tip. When a pin is inserted into a corresponding LM well, the tip and straight (e.g., cylindrical) sections may be within the LM well, while the flared portion remains within the cap layer.

An interconnect fabric in an integrated circuit (IC) device can be hierarchically partitioned into a set of peripheral sub-fabrics and a glue sub-fabric coupled to each of the peripheral sub-fabrics based on the physical design information associated with the IC device. Each of the peripheral sub-fabrics and the glue sub-fabric can be implemented using 2:1 hierarchical multiplexers based on an agglomerative clustering scheme. Physically aware design of the hierarchical multiplexer tree along with the optimal placement of the 2:1 multiplexers can provide smaller overall wire length and reduced routing congestion in the interconnect.

The present disclosure describes an illustrative semiconductor IC device that includes an antenna diode that drains electrical charge build up created during backside BEOL network fabrication processes. The semiconductor IC device includes an active semiconductor IC device upon which the backside BEOL network is to be fabricated and a handler semiconductor device that includes a diode doped region. Charge build up that may occur during the fabrication of the backside BEOL network may be dissipated through the diode doped region. As such, parasitic charge build up that may damage the semiconductor IC device is limited, thereby increasing yield of, and thereby limiting semiconductor IC device failure.

A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Isolation structures between transistors in integrated circuit (IC) devices. An IC device includes transistors coupled to an interconnect network, and between the transistors a dielectric structure with a wider width away from the interconnect network and a narrower width nearer the interconnect network. Dielectric structures with wider back-side widths may separate gate electrodes and / or source and drain contacts of the transistors. The dielectric structures may be formed by etching an opening between metallization structures of the transistors from a back side of the device substrate and by depositing liner and fill dielectrics over the back-side opening.

An integrated circuit (IC) device includes a plurality of chiplets including a first device and a second device. A die-to-die (D2D) interconnect link connects between the first device and the second device. A link training and status state machine (LTSSM) of the IC device is configured to operate the degraded D2D interconnect link in a resilient link mode to provide a plurality of enabled lanes and a plurality of disabled lanes. The LTSSM detects a faulty lane among the plurality of enabled lanes, and replaces the faulty lane using a functional lane from the plurality of disabled lanes to maintain the degraded D2D interconnect link.

Integrated circuit (IC) devices are provided. An IC device includes a back-end-of-line (BEOL) region that includes a first via and a second via on a first lower metal line and a second lower metal line, respectively. The BEOL region includes a first upper metal line coupled to the first lower metal line by the first via, and a second upper metal line coupled to the second lower metal line by the second via. The first upper metal line and the first via each include a first metal. The second upper metal line and the second via each include a second metal that is different from the first metal. Moreover, the second upper metal line is wider than the first upper metal line. Related methods of forming BEOL regions of IC devices are also provided.

A integrated circuit (IC) package device includes a first substrate, an IC device mounted to a first surface of the first substrate, a second substrate, and first power delivery circuitry. The second substrate is mounted to a second surface of the first substrate. The first surface is opposite the second surface. The second substrate includes a decoupling capacitor. The first power delivery circuitry is mounted to the second substrate and coupled to the IC device through the second substrate and the first substrate.

Integrated circuit (IC) devices implementing bilayer memory stacking with compute logic circuits shared between bottom and top memory layers are disclosed. An example IC device includes a first IC structure that includes one or more memory layers but not necessarily compute logic circuits, the first IC structure being bonded with a second IC structure that includes at least one layer of compute logic circuits and further includes one or more memory layers stacked above the compute logic circuits. The first and second IC structures may be bonded so that the compute logic circuits of the second IC structure may be communicatively coupled to memory layers of both the first and second IC structures.

An integrated circuit (IC) device may implement a speech recognition model with a transformer-based architecture. The IC device may include an embedder unit, etched mind unit(s), a layer normalizer unit, a sampler unit, and a flow control unit. The embedder unit may be a hardware implementation of an embedder in the model. The etched mind unit(s) may be a hardware implementation of matrix multiplications and additions in the model. The layer normalizer unit may implement a layer normalizer in the model. The sampler unit may implement a sampler in the model. The sampler unit may use comparators to find the largest value of a vector received from the etched mind unit(s). The sampler unit may determine the index of the largest value and output a predicted token. The flow contour unit may orchestrate the other components of the IC device based on a timing sequence of the model.

An example IC device includes a plurality of vertical transistors which may be part of memory cells, thus realizing vertical-transistor based memory. The IC device further includes a wordline, electrically continuous along a first longitudinal axis and electrically coupled to gates of a first subset of the transistors, and a control line that may be either a bitline or a plateline, electrically continuous along a second longitudinal axis and wrapping around at least portions of channel materials of a second subset of the transistors, where the first subset and the second subset have one transistor in common. At least one of the first longitudinal axis and the second longitudinal axis is not parallel to any edges or borders of the support structure, and, as a result, such a memory is referred to as “diagonal memory.” The transistors may be hysteretic transistors and / or may be further coupled to hysteretic capacitors.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.

The invention provides a method for manufacturing a nanometer silicon through hole in a silicon wafer with an IC device and a packaging structure, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining a first silicon wafer, arranging an IC device on a first surface of the first silicon wafer through the execution of an IC technology, and forming an IC device layer; preparing a metal pad on the surface of the IC device layer; depositing and growing a dielectric layer on the IC device layer by using a dielectric layer material; preparing a first through hole in the growth dielectric layer, wherein the first through hole is located above the metal pad and is connected with the upper surface of the metal pad; preparing a first metal layer on the surface of the growth dielectric layer; a second through hole is formed in the second surface of the first silicon wafer, penetrates through the first silicon wafer and the IC device layer, is located below the metal pad and is connected with the lower surface of the metal pad; and preparing a second metal layer on the second surface to obtain the through-silicon-via structure.

The utility model relates to a switch mode power supply (SMPS) and integrated circuit (IC) equipment, and aims to realize soft start of a buck converter. The integrated circuit device includes: a buck converter; a control circuit of a buck converter includes: a comparator comparing a feedback voltage of the buck converter with a reference voltage increased from a first voltage to a second voltage; a pulse width modulator generating a pulse width modulated (PWM) signal having a time-varying pulse width proportional to the reference voltage; an AND gate which generates a first control signal by performing logic AND operation on the output of the comparator and the PWM signal; a pulse generator generating a second control signal by generating a pulse in response to a rising edge in an output of the comparator; and a selection circuit selecting the first control signal or the second control signal as a control signal of the buck converter based on an output voltage of the buck converter. The utility model is used in a switch mode power supply (SMPS) and integrated circuit (IC) equipment.

A method can include receiving a first power supply voltage at a first terminal substantially at a first side of an IC device; providing first and second rows of insulated gate field effect transistors (IGFETs) substantially at a second side of the IC device, each IGFET including first and second source / drains (S / Ds), channels, and a control gate that substantially surrounds the channels. A first power supply voltage can be coupled from the first terminal to an S / D of an IGFET in the first row via a first conductive via disposed between the first side and the second side and a first conductive line buried in and proximate the second side. IGFETs of the first row can have a first conductivity type. IGFETs of the second row can have a second conductivity type. Corresponding devices and systems are also disclosed.

An IC device design system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs, the storage medium and the code being configured to, with the processor, cause the system to receive an IC device layout diagram including a gate region having a width extending at least from a first edge of an active region to a second edge of the active region and a gate via at a location within the active region and along the width, receive a first gate resistance value corresponding to the gate region, retrieve a second gate resistance value from a resistance value reference based on the location and the width, and based on the second gate resistance value being greater than the first gate resistance value, add a gate terminal node and a resistor to a netlist corresponding to the gate region.

An IC device includes first and second transistors and a memory device. The first transistor includes a first source / drain (S / D) terminal coupled to a first select line, a second S / D terminal, and a gate coupled to a first word line. The second transistor includes a first S / D terminal coupled to a first bit line, a second S / D terminal, and a gate. The memory device is coupled to the second S / D terminal of the second transistor, and a first storage node includes the second S / D terminal of the first transistor and the gate of the second transistor.