459 results about "Ic manufacturing" patented technology

The invention discloses a data enhancement and yield analysis method and system for a multi-defect pattern wafer graph, and belongs to the technical field of integrated circuit manufacturing and detection. Obtaining an original multi-defect pattern wafer graph, and building a data set after the number is increased; multi-scale features of the wafer graph are extracted, defect features are formed through feature pyramid fusion, a defect activation module is used for generating position-sensitive defect activation feature graphs, and the defect activation feature graphs are normalized and aggregated into a defect feature matrix; each row of feature vectors of the matrix synchronously output defect type probabilities, confidence scores and grain level masks through three independent prediction heads, instance segmentation masks are calculated based on dynamic convolution, confidence re-scoring is implemented, and model training is completed through binary matching and combined loss; and finally, calculating a defect counting yield and a spatial distribution yield based on a segmentation result. The technical problems that in integrated circuit manufacturing, multi-defect wafer graph data is scarce, automatic analysis is insufficient, and a traditional detection function is single are solved.

The invention discloses an integrated circuit equipment data optimization monitoring system and method based on big data, and relates to the technical field of integrated circuit manufacturing. The method is used for solving the problems of insufficient multi-physical field monitoring, difficulty in abnormal traceability and lack of closed-loop control in plasma etching. A plasma sheath thickness inversion model and an etching selection ratio model are constructed by collecting radio frequency reflection phase, mass spectrum ion strength and wafer temperature data, and process parameter-plasma state dynamic coupling is established. Interference image distortion features and electron microscope size data are fused, micro-groove geometric parameters are analyzed, morphology instability risk indexes are generated, and nanoscale early warning is achieved. And designing a dual-channel fusion network, embedding a physical constraint attention mechanism, and generating an etching rate optimization instruction. On the basis of incremental learning, model parameters are updated online, a'monitoring-decision-feedback 'closed-loop system is formed, anomaly detection sensitivity and decision reliability are improved, and technical support is provided for intelligence of integrated circuit equipment.

The invention belongs to the technical field of integrated circuit manufacturing, and relates to an etching device for a thick copper PCB. Comprising a shell, material holes are formed in the two sides of the shell, a liquid conveying pipe is arranged on the upper side of the shell, the liquid conveying pipe is communicated with liquid distribution pipes which are distributed at equal intervals, the liquid distribution pipes penetrate through the shell and are communicated with spraying pipes, the lower sides of the spraying pipes are communicated with spraying heads which are distributed at equal intervals, a gas conveying pipe is arranged on the upper side of the shell, and the gas conveying pipe is communicated with the spraying heads. The air conveying pipe is communicated with air distributing pipes distributed at equal intervals, the air distributing pipes penetrate through the shell and are communicated with air spraying pipes, and the air spraying pipes are used for guiding air flow in the air spraying pipes to flow downwards. According to the invention, the vertical downward air flow is applied by means of the air injection pipe, and downward acting force is applied to the PCB by means of blowing of the air flow, so that the stability of the PCB in the etching process is kept while a supporting roller on the upper side of the PCB is omitted, and the etching efficiency and the etching uniformity are improved.

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a PCB welding machine which comprises a workbench, a supporting table is fixedly connected to the upper end of the workbench, a welding head is installed at the upper end of the supporting table in a sliding mode, a feeding assembly is arranged on one side of the supporting table, and the feeding assembly comprises two first rectangular strips arranged at the upper end of the workbench in a sliding mode. A plurality of sets of clamping assemblies are arranged between the two first rectangular strips, each clamping assembly comprises two L-shaped clamping strips, third round holes are formed in the middles of the L-shaped clamping strips, the multiple L-shaped clamping strips can slide on the outer side of a third cylindrical strip through the third round holes, the third cylindrical strip is arranged between the two first rectangular strips, and the clamping assemblies are arranged between the two first rectangular strips. An electric wire is clamped by driving the L-shaped clamping strip and then moved to a welding point of the PCB for welding, so that a worker does not need to approach a welding head of a welding machine in the welding process, and high-temperature scalding is prevented.

The invention relates to the technical field of integrated circuit manufacturing, in particular to a wafer-level multi-chip metal wiring method and a wafer. Metal wires are arranged in a layered mode, and preset intervals are set for isolation; jumper connection between the metal wires of different metal layers is achieved through the through holes at the intersections of the scribing grooves, high-density signal transmission is achieved through the multiple layers of metal wires, and the situation that two adjacent metal wires are short-circuited together due to cutting extrusion during scribing can be prevented through cross-layer jumpers and interval isolation arrangement of the metal wires. By means of the layered metal wiring structure and spaced wiring, efficient data burning of thousands of chips on the wafer is achieved, stray capacitance and short circuit risks are remarkably reduced, meanwhile, the wafer utilization rate and burning efficiency are improved, the number and grouping mode of the chip arrays can be flexibly adjusted according to requirements, and the method is suitable for large-scale popularization and application. And the manufacturing requirements of chips with different scales are met.

The invention relates to the field of integrated circuit manufacturing, in particular to a light source mask collaborative optimization method and device, and the method comprises the steps: obtaining an initial light source and an initial mask pattern; the initial mask pattern is a binary image; determining the adjusted initial light source and the adjusted initial mask pattern corresponding to the minimum function value of the light source mask collaborative optimization loss function as an optimized light source and an optimized mask pattern; the light source mask collaborative optimization loss function comprises a main pattern edge error item and a sub-resolution auxiliary pattern printing item; obtaining a simulation photoetching image, and judging whether a sub-resolution auxiliary pattern is printed in the simulation photoetching image or not; when the printed sub-resolution auxiliary pattern exists, outputting the latest optimized mask pattern as a process iteration mask pattern; calculating a proportion value; and when the proportion value does not exceed the qualified upper limit value, outputting an optimized light source and process iteration mask pattern. The method can ensure that no sub-resolution auxiliary pattern is printed and a larger process window is reserved.

The invention relates to an engineering image-text cross-modal automatic reconstruction method based on a large model. For a gas path diagram of integrated circuit manufacturing equipment, firstly, all characters in the diagram are analyzed by adopting a PDF analysis method, and are written into a character analysis result file; and then identifying an image main region through a YOLOv5 training model, writing the image main region into a main region identification result file, identifying various devices through the YOLOv5 training model, and writing the devices into a device identification result file. And obtaining a main area of the engineering drawing through the coverage function, filtering out characters and devices in the main area, recognizing a straight line through an LSD algorithm, and writing the straight line into a straight line recognition result file. And integrating all the analysis result files to form an input analysis file of the engineering drawing multi-modal large model. Advanced technologies such as artificial intelligence, PDF analysis and line segment recognition are comprehensively applied, sensing and data analysis of IC manufacturing equipment gas path diagram information are achieved, and deep fusion and reconstruction of multi-source engineering information are achieved.

Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and / or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time.

The invention discloses a method for controlling CMP (chemical mechanical polishing) dish-shaped pits, corrosion pits and interface corrosion of ruthenium barrier layer copper wiring, which is suitable for a manufacturing process of integrated circuits of 14 nanometers and below. According to the method, a specifically synthesized TTAK corrosion inhibitor is introduced into a polishing solution system, the oriented adsorption characteristic of the molecular structure of the TTAK corrosion inhibitor is utilized, the corrosion reaction of copper is selectively inhibited, meanwhile, the normal material removal efficiency of a ruthenium barrier layer and a TEOS dielectric layer is maintained, and cooperative regulation and control of the removal rate of the Cu / Ru / TEOS material are achieved. By means of the method, dished pits, corrosion pits and Fang type interface defects generated in the fine polishing and barrier layer polishing process can be effectively eliminated, and copper / ruthenium interface corrosion is improved. According to the method, the global planarization quality of the copper interconnection ruthenium barrier layer is remarkably improved, the interface bonding strength and the electrical reliability of an interconnection circuit are enhanced, and an effective solution is provided for performance optimization of an advanced process integrated circuit device.

The invention discloses a logic chip mask defect detection method, and relates to the technical field of integrated circuit manufacturing, and the method comprises the following steps: S1, constructing a scattering response model of sub-wavelength inorganic particles on the surface of a mask, and constructing a scattering response model of sub-wavelength inorganic particles on the surface of the mask under a set multi-angle polarized light incidence condition; non-linear disturbance influence of inorganic particles with different particle sizes on the reflected light phase in each incident polarization state is simulated, and a scattering response template containing standard phase disturbance characteristics is generated; and S2, based on a scattering response template, carrying out pixel-by-pixel matching analysis on the acquired multi-angle polarization phase diagram on the surface of the mask, identifying a local area matched with the template, and marking the local area as a suspected scattering interference area. According to the method, through construction of the scattering response template and multi-angle polarization consistency analysis, accurate distinguishing of artifacts and real defects is achieved, the recognition precision and stability under complex interference are improved in combination with structure retention type phase reconstruction and dynamic threshold recognition, and mask quality control and photoetching yield improvement are facilitated.

The invention relates to the technical field of integrated circuit manufacturing, in particular to a soaking device for a PCB. Comprising a box body, a feeding carrier roller set and a discharging carrier roller set are installed on the box body, a soaking pool, a liquid storage pool and a power pool are arranged in the middle of the box body, a power carrier roller set is obliquely arranged in the soaking pool, a motor is installed in the box body, a rotating roller is rotationally connected in the power pool, and a motor is installed in the rotating roller. An output shaft of the motor penetrates through the power pool and is fixedly connected with the rotating roller, and the rotating roller is slidably connected with moving strips which are evenly distributed in the circumferential direction. According to the PCB soaking device, the PCB is driven to move through the power carrier roller set in the soaking pool, the liquid medicine is driven to flow through the rotating rollers and the moving strips, the liquid medicine penetrates through or bypasses the PCB to circularly flow, the problem of poor cohesion between different processes in the PCB production process is solved, and the treatment efficiency of the PCB soaking process is improved through the structural design.

The invention discloses a high-efficiency intelligent card wire end burying positioning and distance adjusting device, and relates to the technical field of integrated circuit manufacturing. The high-efficiency intelligent card wire end burying positioning and distance adjusting device comprises a fixed winding unit, a guide adjusting unit, a conveying unit and a wire burying unit; a guide adjusting unit is fixedly installed on the fixed winding unit, a conveying unit is fixedly installed on the guide adjusting unit, and the conveying unit is connected with the fixed winding unit. According to the invention, through the flow cooperation of the fixed winding unit, the conveying assembly and the adjusting assembly, the precise conveying of the copper wire to the wire embedding assembly and the wire embedding operation of the intelligent card are realized, and during the spacing adjustment, by means of the cooperative driving of the guide assembly and the adjusting assembly, the multi-unit linkage distance adjustment of the wire embedding assembly can be realized, and the single wire embedding assembly can be finely adjusted independently; and meanwhile, the control modes of manual reference setting of thread end burying and other electric adjustment, touch screen one-key distance adjustment and single-head fine adjustment are matched.

The invention relates to the technical field of chemical mechanical grinding equipment, and discloses a polishing pad surface roughness monitoring device with an AI system, which comprises an optical sensor module, a data transmission module, a control and alarm module, a diamond disc fixing retaining ring, a waterproof cable slot and a diamond disc swinging arm, the diamond disc fixing seat is arranged on the side face of the diamond disc fixing seat, the data transmission module is arranged on the side face of the diamond disc fixing seat, and the control and alarm module is arranged on the side face of the diamond disc fixing seat. According to the polishing pad surface roughness monitoring device with the AI system and the method thereof, the precision and the stability of a manufacturing process are improved, the production efficiency is improved, the cost is reduced, diamond discs are simplified to be replaced, and the service life is prolonged; the method can be applied to the fields of semiconductor and integrated circuit manufacturing, precision optical element processing, high-precision metal surface treatment and the like, so that the product yield and the process stability are improved.

The invention relates to the technical field of circuit board analysis, in particular to an integrated circuit defect analysis method and system, and the method comprises the steps: extracting and screening E-test data of a target product from a big data platform for integrated circuit manufacturing; performing defect classification modeling processing on the screened E-test test data; calculating a defect correlation index according to the classification accuracy and the correlation metric value of each candidate E-test item; determining a defect judgment threshold value and a numerical value distribution direction related to the defect based on a logic regression classifier result of the key test item, and generating a binary defect distribution diagram corresponding to each jointed board; calculating the image similarity between the bad jointed board graph and each good jointed board graph; judging whether the image similarity is higher than a preset threshold value or not, and adding the jointed boards of the good jointed board graph into a virtual bad jointed board list; and based on the virtual bad jointed board list, analyzing and comparing the manufacturing process flow data of the virtual bad jointed board and the original defective jointed board, and determining the potential root cause causing the defect. According to the method, the problems that in the E-test scene of the circuit board, the number of defect samples is extremely small, categories are extremely unbalanced, an experience threshold value is difficult to set, and root causes are difficult to trace can be solved.

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

Disclosed is a method of correcting a measured spectrum for the effects of a source spectrum resulting from an illumination source. The method comprises obtaining a measured spectrum in terms of a measurement parameter, the measured spectrum being obtained from captured diffracted radiation from a periodic structure following illumination of said periodic structure using source radiation from said illumination source, the periodic structure being the spectrometer grating and an object being measured; determining an estimate of the source spectrum from the measured spectrum; and correcting the measured spectrum using the estimate of the source spectrum.

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a cladding plate pretreatment device for circuit board processing. The cleaning device aims to overcome the defect that cleaning water escapes to the cleaned surface of the circuit board, and the cleaning efficiency of the circuit board is affected. Comprising a conveying frame installed on a box body, a sprayer is installed in the box body, a plurality of spraying heads are installed on the sprayer, the conveying frame is rotationally connected with a plurality of electric control rotating rollers, and all the electric control rotating rollers located below the sprayer are in a circular truncated cone shape. And the spraying head gradually inclines towards the minimum diameter part of the electric control rotating roller from top to bottom. The circuit board is inclined, the cleaning water sprayed by the spraying head flows along the inclined surface of the circuit board, and the water flow direction of the surface of the circuit board is controlled, so that the diffusion direction of the cleaning water on the surface of the circuit board is controlled, and the probability that the cleaning water carries impurities and flows to the cleaned part of the circuit board is reduced; and the cleaning effect of the circuit board is improved.

The invention relates to the field of integrated circuit manufacturing, and particularly discloses a semiconductor photoelectric horizontal sensor and a preparation method and application thereof, the sensor is a sheet-shaped body, and the sensor comprises a substrate which comprises a plurality of photoelectric sensing diodes which are uniformly distributed on a circular ring with a first circle center axis perpendicular to the substrate as an axial symmetry axis; the annular cavity is positioned on the substrate and vertically corresponds to a circular ring formed by the plurality of photoelectric sensing diodes, and a rollable microgravity ball is arranged in the annular cavity; and the first signal light introduction part is located on the annular cavity, is annular, vertically corresponds to the annular cavity and is used for vertically introducing the annular signal light which is actively irradiated into the annular cavity. According to the invention, the rollable microgravity ball can freely roll at the lowest point of the annular cavity under the action of gravity, meanwhile, the actively irradiated annular signal light is vertically guided into the annular cavity, and the accurate angular position of the rollable microgravity ball is accurately sensed by the plurality of photoelectric sensing diodes.

The invention relates to the technical field of integrated circuit manufacturing, in particular to copper deposition equipment for a new energy vehicle lamp printing integrated circuit board and a working method thereof.The copper deposition equipment comprises a conveying mechanism, a copper deposition frame, a traveling crane and a clamping frame, a lifting table is arranged at the tail end of the conveying mechanism, and a plurality of rolling wheels are arranged on the other side of the lifting table; a plurality of layering plates are arranged at the two ends of the inner side of the copper deposition frame, a pair of clamping frames are clamped at the two ends of the copper deposition frame and located at the upper end of the copper deposition frame, the outer ends of the clamping frames are rotationally connected with the travelling crane, inclined chamfers are formed in the four corners of the upper end of the copper deposition frame, and triangular grooves are formed in the lower sides of the inclined chamfers; and a plurality of triangular clamping blocks are arranged on the inner side of the clamping frame, a first spring piece is arranged between the triangular clamping blocks, inclined chamfers are formed in the lower ends of the triangular clamping blocks in the same way, and the automatic loading function is conveniently, rapidly and efficiently achieved.

A system and method are disclosed for a superconducting traveling-wave parametric amplifier (TWPA) with improved control and performance. In a preferred embodiment, the amplifier comprises an integrated array of symmetric rf-SQUIDs in a transmission line structure. A device was fabricated using niobium superconducting integrated circuits, and confirmed predicted performance, with a maximum gain up to 17 dB and a bandwidth of 4 GHz. A similar device can be applied as a low-noise, low-dissipation microwave amplifier for output from a superconducting quantum computer, or as a preamplifier, switch, or frequency converter for a sensitive microwave receiver, or as an output amplifier for a frequency-multiplexed superconducting detector array.

The invention discloses a film stripping and cleaning device for PCB production, and belongs to the technical field of integrated circuit manufacturing. Comprising a supporting frame, a roller conveying module is arranged on the supporting frame, two sets of spraying modules are arranged in the supporting frame, each spraying module comprises a liquid inlet pipe, the liquid inlet pipes are fixedly connected to the supporting frame in a penetrating mode, and the liquid inlet pipes and the supporting frame are jointly and rotationally connected with symmetrically-distributed spraying pipes. The spraying pipes are fixedly connected with connecting gears, rack frames which are symmetrically distributed are slidably connected into the supporting frame, the connecting gears are meshed with the corresponding rack frames, and a pushing assembly is arranged on the supporting frame. The connecting gears drive the corresponding rotating liquid pipes to swing in a reciprocating mode, the rotating liquid pipes swing in a reciprocating mode to drive the nozzle sets on the rotating liquid pipes to swing synchronously, then the cleaning positions of the nozzle sets on the circuit board are continuously changed, and therefore the cleaning uniformity of the multiple nozzle sets on the circuit board is improved.

The invention relates to the field of integrated circuit manufacturing, in particular to a mask process correction method, device and equipment and a storage medium. Inputting the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model; determining a mask layer bottom simulation pattern size and a mask layer top simulation pattern size corresponding to each edge section in the simulation electron beam exposure pattern to obtain a corresponding side wall included angle; according to the size of the simulation pattern at the bottom of the mask layer, determining a size-included angle comparison data set corresponding to each edge section to obtain an included angle offset; further determining a target size offset; and adjusting the position of a corresponding edge section in the simulation pattern at the bottom of the mask layer according to the target size offset. The similarity between a wafer pattern obtained by carrying out a photoetching process on the mask layer corrected by the method and a photoetching target pattern is greatly improved.

The invention discloses a grid system for a plasma etching system and the plasma etching system, and belongs to the field of integrated circuit manufacturing, the grid system comprises a grid mesh close to a discharge outlet side of a discharge chamber,..., an Nth middle grid mesh and a grid mesh close to a dry etching part side which are arranged in sequence, and each grid mesh comprises a substrate, a plurality of grid mesh holes are uniformly distributed in the substrate, a first film layer with low surface energy and low sputtering yield is arranged on the outer surface of the substrate, and a second film layer with low surface energy and low sputtering yield is arranged on the inner wall of each grid mesh hole; n is an integer greater than or equal to 0. The invention can delay the loss of the grid mesh and delay the adsorption pollution on the surface of the grid mesh.

Disclosed are methods and systems for filling a gap. An exemplary method comprises providing a substrate to a reaction chamber. The substrate comprises the gap. The method further comprises at least partially filling the gap with a gap filling fluid. The methods and systems are useful, for example, in the field of integrated circuit manufacture.

The invention relates to a PINN-based negative development photoresist deformation parameter extraction method, belongs to the technical field of integrated circuit manufacturing, and solves the problem that deformation parameters of negative development photoresist are difficult to measure in the prior art. The negative developing photoresist deformation parameter extraction method comprises the following steps: determining center coordinate data of negative developing photoresist in a plurality of exposure areas before and after a photoetching process; inputting each piece of center coordinate data into a PINN model for training; in the PINN model, predicting according to each center coordinate to obtain a predicted thickness displacement corresponding to each center coordinate and a predicted deformation parameter of the negative developing photoresist; judging whether a loss function value of the PINN model reaches a loss threshold value or not; and if so, stopping training the PINN model, and outputting a predicted deformation parameter of the negative developing photoresist by the PINN model as a final deformation parameter of the negative developing photoresist. Therefore, the deformation parameters of the negative developing photoresist are extracted.

Using “in-situ on-die time-domain reflectometry (TDR)” with data signal paths of integrated circuits, printed circuit boards, and data processing equipment and systems allows testing, verification and troubleshooting of data channel signal path impedance variations including the package, escape routing, socket, board, and cable / connectors provides fast characterization thereof. Operation of “in-situ on-die TDR” uses existing analog-to-digital converter (ADC) and data transmitter (TX) drivers of an integrated circuit to act as a TDR sampling head by performing a user interface-based TDR sampling with a step-waveform generated by an integrated circuit TX driver. Then sampling the step-waveform with the ADC of the integrated circuit using spline interpolation to obtain the over-sampled waveform. Once the sampled step-waveform is obtained, the TDR profile of the sampled data channels may be calculated. Large amounts of impedance variation data may thus be collected during either integrated circuit manufacturer or customer-built data communications channel testing.

The invention discloses an etching groove and through hole line edge roughness optimization method, which belongs to the technical field of integrated circuit manufacturing, and comprises the following steps of: exposing on a substrate with a hard mask layer through a photoetching process to obtain a photoresist pattern; etching the photoresist pattern through an ion beam etching process to reduce the surface roughness of the side wall of the photoresist pattern groove or through hole structure; forming a covering film layer on the substrate through a deposition process; exposing the upper surface of the photoresist through a first etching process; the photoresist is etched through a second etching process, and the part, located on the side wall of the photoresist, of the covering film layer is left to serve as a new mask plate; the substrate is etched downwards through a third etching process, and the pattern of the new mask plate is transferred to the hard mask layer in the substrate; and removing the unwanted surface structure to obtain the required semiconductor structure. According to the method, the roughness of the line edge can be greatly reduced, a flat surface is obtained, surface defects are few, meanwhile, the cost is reduced, the efficiency is improved, and the requirement for higher fineness is met.

The invention relates to the field of computer vision and semiconductor manufacturing detection, in particular to a multi-scale feature fusion wafer defect detection method, which comprises the following steps of: acquiring a wafer image, and labeling particle defects existing in the image by using a manual labeling tool; the marked image is preprocessed; and constructing and training a defect intelligent identification model based on the convolutional neural network, and performing defect detection on the processed wafer image by using the model. The wafer particle defect intelligent detection method provided by the invention has remarkable advantages in the aspects of detection precision, recognition speed, defect classification, system stability, deployability and the like, can be widely applied to multiple fields of integrated circuit manufacturing, semiconductor packaging, silicon wafer detection and the like, and has good popularization and application prospects and industrial value.

The present invention belongs to the field of chip processing technology, specifically a chip plastic sealing device and method for integrated circuit production; it includes a processing table, on which a force-applying and continuous pressure mechanism for plastic sealing of the chip is provided; the force-applying and continuous pressure mechanism includes a fixed mold, the bottom of which is connected to the top of the processing table by bolts; the processing table is also equipped with a U-shaped base, and the opening of the U-shaped base faces the top of the processing table; a telescopic cylinder is installed on the U-shaped base by bolts, and the output end of the telescopic cylinder faces the top of the processing table and is also equipped with an H-shaped square plate; impurities or dust adhering to the fixed mold and the movable mold are cleaned by a gas-generating and cavity-clearing unit, and the cleaning process does not require manual operation by the staff, while avoiding the problem that the impurities inside the fixed mold and the movable mold are not completely cleaned due to negligence in the process, resulting in incomplete chip sealing, bubble generation, etc., thereby improving the plastic sealing effect of the device and further reducing the work intensity of the staff.

The invention relates to the field of integrated circuit manufacturing, in particular to the technical field of manufacturing of semiconductor device special equipment such as a photoetching machine and an etching machine special for production, and provides a through hole filling electroplating method and system for a printed circuit board. The method comprises the following steps: carrying out laser micro-through-hole processing on the printed circuit board; carrying out glue removal treatment on the printed circuit board with the micro through hole; carrying out black hole treatment or direct electroplating treatment on the degummed printed circuit board; performing porefilling electroplating on the treated printed circuit board by using an acidic copper plating porefilling special liquid medicine; in the hole filling electroplating process, a multi-stage electroplating current parameter program is adopted, in-hole pre-plating is carried out at low current density in the initial stage, it is ensured that hole walls are evenly covered, after the main hole filling stage is started, pulse or periodic reverse current is adopted, the current density is increased in a stepped mode, and through holes are filled with acid copper plating hole filling special liquid medicine; and parameters are adjusted at the last stage of filling to ensure that the copper thickness of the hole surface is uniform, and dished pits or excessive recesses are avoided.