218 results about "Ic manufacturing" patented technology

The invention belongs to the technical field of integrated circuit manufacturing, and relates to an etching device for a thick copper PCB. Comprising a shell, material holes are formed in the two sides of the shell, a liquid conveying pipe is arranged on the upper side of the shell, the liquid conveying pipe is communicated with liquid distribution pipes which are distributed at equal intervals, the liquid distribution pipes penetrate through the shell and are communicated with spraying pipes, the lower sides of the spraying pipes are communicated with spraying heads which are distributed at equal intervals, a gas conveying pipe is arranged on the upper side of the shell, and the gas conveying pipe is communicated with the spraying heads. The air conveying pipe is communicated with air distributing pipes distributed at equal intervals, the air distributing pipes penetrate through the shell and are communicated with air spraying pipes, and the air spraying pipes are used for guiding air flow in the air spraying pipes to flow downwards. According to the invention, the vertical downward air flow is applied by means of the air injection pipe, and downward acting force is applied to the PCB by means of blowing of the air flow, so that the stability of the PCB in the etching process is kept while a supporting roller on the upper side of the PCB is omitted, and the etching efficiency and the etching uniformity are improved.

The invention discloses a high-efficiency intelligent card wire end burying positioning and distance adjusting device, and relates to the technical field of integrated circuit manufacturing. The high-efficiency intelligent card wire end burying positioning and distance adjusting device comprises a fixed winding unit, a guide adjusting unit, a conveying unit and a wire burying unit; a guide adjusting unit is fixedly installed on the fixed winding unit, a conveying unit is fixedly installed on the guide adjusting unit, and the conveying unit is connected with the fixed winding unit. According to the invention, through the flow cooperation of the fixed winding unit, the conveying assembly and the adjusting assembly, the precise conveying of the copper wire to the wire embedding assembly and the wire embedding operation of the intelligent card are realized, and during the spacing adjustment, by means of the cooperative driving of the guide assembly and the adjusting assembly, the multi-unit linkage distance adjustment of the wire embedding assembly can be realized, and the single wire embedding assembly can be finely adjusted independently; and meanwhile, the control modes of manual reference setting of thread end burying and other electric adjustment, touch screen one-key distance adjustment and single-head fine adjustment are matched.

The invention relates to a PINN-based negative development photoresist deformation parameter extraction method, belongs to the technical field of integrated circuit manufacturing, and solves the problem that deformation parameters of negative development photoresist are difficult to measure in the prior art. The negative developing photoresist deformation parameter extraction method comprises the following steps: determining center coordinate data of negative developing photoresist in a plurality of exposure areas before and after a photoetching process; inputting each piece of center coordinate data into a PINN model for training; in the PINN model, predicting according to each center coordinate to obtain a predicted thickness displacement corresponding to each center coordinate and a predicted deformation parameter of the negative developing photoresist; judging whether a loss function value of the PINN model reaches a loss threshold value or not; and if so, stopping training the PINN model, and outputting a predicted deformation parameter of the negative developing photoresist by the PINN model as a final deformation parameter of the negative developing photoresist. Therefore, the deformation parameters of the negative developing photoresist are extracted.

The invention relates to the field of integrated circuit manufacturing, in particular to the technical field of manufacturing of semiconductor device special equipment such as a photoetching machine and an etching machine special for production, and provides a through hole filling electroplating method and system for a printed circuit board. The method comprises the following steps: carrying out laser micro-through-hole processing on the printed circuit board; carrying out glue removal treatment on the printed circuit board with the micro through hole; carrying out black hole treatment or direct electroplating treatment on the degummed printed circuit board; performing porefilling electroplating on the treated printed circuit board by using an acidic copper plating porefilling special liquid medicine; in the hole filling electroplating process, a multi-stage electroplating current parameter program is adopted, in-hole pre-plating is carried out at low current density in the initial stage, it is ensured that hole walls are evenly covered, after the main hole filling stage is started, pulse or periodic reverse current is adopted, the current density is increased in a stepped mode, and through holes are filled with acid copper plating hole filling special liquid medicine; and parameters are adjusted at the last stage of filling to ensure that the copper thickness of the hole surface is uniform, and dished pits or excessive recesses are avoided.

This invention discloses a method for manufacturing a flexible circuit board and a flexible circuit board, relating to the field of integrated circuit manufacturing technology. The method includes the following steps: providing a flexible copper-clad laminate (CCL) having a pre-processed area; drilling holes in the CCL to form positioning holes, the positioning holes partially overlapping with the pre-processed area and forming a semi-circular notch in the overlapping area; providing a punching die to punch the flexible CCL, the area covered by the projection of the punching die along the punching direction forming a first projection pattern, the first projection pattern partially overlapping with the pre-processed area and forming a pad half-hole in the overlapping area, the pad half-hole completely covering the semi-circular notch, and the sidewall of the pad half-hole forming a sidewall copper-plated area. By forming a larger sidewall copper-plated area formed by the sidewall of the pad half-hole, sufficient and stable solder volume can be provided for soldering, reducing the risk of cold solder joints and improving the yield of integrated circuit manufacturing, production of dedicated lithography machines, and etching machines.

The utility model relates to an integrated circuit printing device in the technical field of integrated circuit printing, which comprises a body and an adsorption platform, the adsorption platform is provided with a plurality of vacuum holes, the side edge of the body is provided with side edge vacuum holes, and the body is internally provided with a limiting pin. According to the utility model, an optimization mode that the PCB units are in one-to-one correspondence with the vacuum holes is adopted, so that the adsorption effect is greatly enhanced, the phenomena of substrate warping, shaking and the like caused by vacuum adsorption weakness in the printing process are effectively avoided, the solder paste printing balling quality is greatly improved, the defective rate of products is remarkably reduced, and the production efficiency is improved. And the production efficiency is greatly improved, and considerable economic benefits are created for integrated circuit manufacturing enterprises.

The invention relates to the field of integrated circuit manufacturing, in particular to an integrated circuit and a packaging method thereof. Etching an open groove in the blank area; embedding the embedded core particles into the open groove to obtain an integrated chip; a graphical insulation blocking layer is arranged on the upper surface of the integrated chip; obtaining a top wiring layer on the basis of the insulation blocking layer; inversely mounting external core particles on the top wiring layer; the external core particles are electrically connected with the embedded core particles through the top wiring layer. The core particles and the chip are silicon-based integrated circuits, thermal expansion coefficients are highly matched, and heat dissipation is facilitated; on one hand, the integration level of the core particles of the packaging device is improved, and on the other hand, vertical short-distance interconnection between the core particles is provided, so that the signal quality is guaranteed; through silicon vias penetrating through the embedded core particles are prevented from being formed in the embedded core particles, so that the signal transmission path is shortened, and meanwhile, the low production cost and the high embedded core particle setting flexibility are guaranteed.

The application provides a laser annealing method and system, and relates to the field of integrated circuit manufacturing. The method comprises the following steps: a first laser module is used to emit a first laser beam with a first wavelength to a wafer, and a second laser module is used to emit a second laser beam with a second wavelength to the wafer; the reflectivity of the wafer to the laser beams with the first wavelength and the second wavelength is measured, and a reflectivity ratio is obtained; the annealing temperature of the wafer is measured; according to the measured annealing temperature and a target annealing temperature, a target total power is determined, and according to the reflectivity ratio and the target total power, the power of the first laser module and the second laser module is adjusted. According to the method, the reflectivity of the wafer to the laser beams with the two wavelengths is complementary to a certain extent, so that the pattern effect can be improved, and the annealing temperature uniformity of the wafer is improved. According to the measurement results of the annealing temperature and the reflectivity, the power is adjusted, so that the annealing temperature non-uniformity of the wafer is corrected, and the annealing temperature uniformity of the wafer is further improved.

This invention relates to the field of CMOS integrated circuit manufacturing processes and discloses a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by implantation. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

The invention relates to the technical field of semiconductor packaging and integrated circuit manufacturing, belongs to the field of ultrasonic welding in metal wire bonding, and discloses a gold wire high-strength bonding structure and method on an organic substrate. One end of the gold bonding wire is welded on the chip, the other end of the gold bonding wire is welded on the substrate, and the welding end of the gold bonding wire on the substrate is fixed between the gold wire ball unit groups through superposition. According to the invention, the technical problems of two-welding crescent exposure, low bonding strength and poor reliability in the prior art are solved.

This invention relates to the field of circuit production line technology and discloses an automatic transfer system for integrated circuit production lines, addressing the technical problems of low transfer efficiency and poor space utilization in existing technologies. The system includes: a three-dimensional storage scheduling module located on one side of the production line, used to store wafer cassettes or photomasks and generate material release instructions according to the production cycle; a vertical conveying system located below the storage module, used to transport materials from a first plane where the three-dimensional storage is located to a second plane flush with the cleanroom floor; and a horizontal conveying system located on the second plane, used to receive materials and complete automatic handover with the production equipment. This application enables fully automated transportation of materials from three-dimensional storage to the production equipment without manual intervention, significantly reducing labor costs and improving the automation level of the production line and the utilization rate of storage space.

The invention belongs to the technical field of integrated circuit manufacturing and filters, and discloses a surface-mounted double-layer stacked microstrip band-pass filter. The filter comprises an upper metal layer, an upper substrate, a middle metal layer, a lower substrate and a lower metal layer which are sequentially arranged from top to bottom. A double-layer stacking method is adopted, the multi-order resonators are placed on the lower layer substrate, the upper layer metal layer, the side wall metalized through holes and the lower layer metal layer form a metal cavity structure, and the size of the filter is remarkably reduced; the multi-order resonator adopts a stepped impedance resonator structure, so that a low-frequency end zero point generated by high-order mode coupling can be effectively used, and better out-of-band rejection can be obtained; a ceramic substrate or a glass substrate with a relatively large dielectric constant is selected, so that the high-frequency loss of a passive device is remarkably reduced, and the quality factor is improved.

The invention discloses a wafer positioning device and method in back cleaning, and relates to the technical field of semiconductor chip packaging in IC manufacturing. The MEMS light receiving chip is attached to the substrate, and an MEMS light receiving chip light sensing area is arranged in the middle area of the upper surface of the MEMS light receiving chip; the MEMS light emitting chip is arranged above the MEMS light receiving chip in parallel, an MEMS light emitting chip light sensing area is arranged in the middle area of the lower surface of the MEMS light emitting chip, and the MEMS light emitting chip light sensing area and the MEMS light receiving chip light sensing area are arranged in a face-to-face mounting mode; and the at least two copper columns are arranged between the MEMS light receiving chip and the MEMS light emitting chip. Redundant structure materials and a multi-layer pressing process are replaced and omitted through copper column connection between the MEMS light receiving chip and the MEMS light emitting chip, and meanwhile the product size is reduced.

The embodiment of the application discloses a kind of circuit systems based on cascaded bidirectional gallium nitride, it is applied to integrated circuit manufacturing and production special photoetching machine, etching machine and other semiconductor device special equipment manufacturing field.Circuit system includes the first field effect tube, bidirectional gallium nitride device and second field effect tube connected in series, substrate selection switch between the substrate electrode of connecting bidirectional gallium nitride device and the source of each field effect tube, negative voltage grid drive network for driving each substrate selection switch, and clamping holding network for clamping or keeping the voltage of one end of each substrate selection switch, to inhibit "self-triggering" caused by device body capacitance charging under voltage rate of change (i.e. dv / dt), avoid two substrate selection switches to form straight-through while being turned on simultaneously.Especially suitable for the demand of strategic emerging industry high-performance integrated circuit and semiconductor special equipment manufacturing.

In accordance with some embodiments, methods, systems, and media for using synthetic images are provided. In some embodiments, a method involves obtaining a set of images associated with the integrated circuit fabrication chamber, wherein the set of images comprises at least a subset of synthetic images. Each synthetic image of the subset of synthetic images is a photo-realistic synthetic image. In some embodiments, at least a portion of the synthetic images represent an anomalous condition associated with the fabrication chamber, and each image in the set of images represents at least one of: 1) components of the fabrication chamber; 2) a process occurring in the fabrication chamber; or 3) wafer characteristics of a wafer being processed in the fabrication chamber. The method may further involve training a machine learning model using the set of images, wherein the trained machine learning model is usable to predict the anomalous condition.

This invention belongs to the technical field of integrated circuit manufacturing, and discloses a SAR-assisted pipelined analog-to-digital converter and its control method. The analog-to-digital converter includes a two-stage SAR ADC module, and the first stage capacitor array includes C 1 1 ~C 1 M‑1 C 1 2 ~C 1 M‑1 The reference voltage is V ref C 1 1 The reference voltage is V cm =V ref / 2, an improved monotonic switching scheme using redundant capacitors can perform successive approximation comparisons to obtain an M-bit digital code. After completing the first-stage conversion, a passive residual transfer scheme is used, along with inter-stage bit transfer, to enter the second-stage conversion. This second-stage conversion employs the same improved monotonic switching scheme as the first stage, performing successive approximation comparisons to obtain an N-bit digital code. Finally, through timing alignment, an M+N-bit digital code is obtained. This design saves device area and improves conversion efficiency.

The invention provides a three-dimensional chip packaging structure and a manufacturing method, and relates to the technical field of integrated circuit manufacturing. The display device at least comprises a first substrate; the second substrate is arranged on the first substrate, and an accommodating space is formed between the second substrate and the first substrate; and the chip stacking structure is arranged in the accommodating space between the first substrate and the second substrate, and the chip stacking structure is electrically connected with the second substrate and the first substrate. According to the invention, the integrated three-dimensional integration of multiple chips can be realized, the integration level of the transistor and the function unit is obviously improved, the interconnection density and the space utilization rate are optimized, the problems of insufficient interconnection density, bottleneck of electrical interconnection performance and the like of the traditional packaging are solved, and the packaging efficiency is improved. The chip size is reduced, the data transmission rate and the overall efficiency of the system are effectively improved, and high-speed and low-delay data interaction is achieved.

A computer-implemented method of processing first metrology data of a patterned portion of a substrate patterned using a wafer processing apparatus to generate predicted second metrology data of the, or another corresponding, patterned portion of the substrate, the first metrology data comprising metrology data from a first metrology domain which obtains metrology data using a first metrology process. The method comprises obtaining the first metrology data of the patterned portion of the substrate, and generating predicted second metrology data of the patterned portion of the substrate, or of the corresponding patterned portion of the substrate, based on the output of a first trained diffusion model conditioned on the first metrology data, the predicted second metrology data comprising predicted metrology data from a second metrology domain which obtains metrology data using a second metrology process.

This invention relates to the field of integrated circuit manufacturing, specifically disclosing a semiconductor photoelectric level sensor, its fabrication method, and its application. The sensor is a sheet-like structure comprising: a substrate including multiple photodiodes evenly distributed on a ring with a first circular axis perpendicular to the substrate as its axis of symmetry; a circular cavity located on the substrate, perpendicularly corresponding to the ring formed by the multiple photodiodes, and containing a rollable microgravity sphere; and a first signal light guide located on the circular cavity, also circular in shape and perpendicularly corresponding to the cavity, for vertically guiding actively irradiated circular signal light into the cavity. This invention utilizes the lowest point of the circular cavity where the rollable microgravity sphere can freely roll under gravity, and simultaneously guides actively irradiated circular signal light vertically into the cavity, with the multiple photodiodes accurately sensing the precise angular position of the rollable microgravity sphere.

The present application relates to the field of integrated circuit manufacturing, and particularly relates to a mask process correction method, device, equipment and storage medium, wherein a target mask pattern and a corresponding design thickness are received; the target mask pattern is input as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model; mask layer bottom simulation pattern sizes and mask layer top simulation pattern sizes corresponding to each edge section in the simulation electron beam exposure pattern are determined, to obtain corresponding side wall included angles; size-included angle comparison data groups corresponding to each edge section are determined according to the mask layer bottom simulation pattern sizes, to obtain included angle offset amounts; a target size offset amount is further determined; and the positions of the corresponding edge sections in the mask layer bottom simulation pattern are adjusted according to the target size offset amount. The similarity between the wafer pattern obtained by performing a photolithography process on the mask layer corrected by the present application and the photolithography target pattern is greatly improved.

The invention discloses a method for selectively regulating and controlling the size of a pattern through a low-temperature ion implantation process, and belongs to the technical field of integrated circuit manufacturing. Performing low-temperature ion implantation on the intermediate material to generate a modified layer on the vertical side wall of the non-hollow part of the intermediate film layer; selective growth is carried out through atomic layer deposition, a deposition layer covering the surface of the intermediate material is formed, the deposition layer forms an adjusted pattern structure, and the profile of the adjusted pattern structure is reduced relative to that of the intermediate pattern structure; part of the deposition layer is removed through wet etching, so that the upper part of the bottom film layer is exposed; performing thermal annealing treatment; and transferring the adjusted pattern structure to the bottom film layer through dry etching. According to the invention, the feature size of the pattern structure can be accurately controlled and reduced, the side wall of the pattern structure can obtain a flatter surface appearance without defects, and the performance of a semiconductor device can be improved.

The invention relates to the technical field of chip processing, and discloses a chip plastic packaging device for integrated circuit production, which comprises a supporting base and an upper supporting seat, the supporting base is provided with a processing table, a detection assembly, an adjusting assembly and a supporting assembly, and a lower mold is arranged below the upper supporting seat. Hydraulic and gear transmission is triggered by detecting the clamping action of a clamping block on a chip model, a main pull rod and an auxiliary pull rod of the adjusting assembly are driven to be synchronously linked, a fixing block is precisely matched with a step-shaped fixing groove of the lower mold, and elastic supporting of a telescopic rod and a supporting spring in the supporting assembly is matched; and after injection molding is completed, pressure relief generated when the upper mold ascends can trigger a supporting spring to rebound, a supporting table is driven to ascend, a fixing block is automatically pulled out of a fixing groove, and a one-way clamping plate is separated, so that automatic unlocking is achieved.

The invention relates to the technical field of integrated circuit manufacturing, in particular to a fan-out chip packaging structure and a packaging process thereof. Comprising a first plastic package body, a chip is fixedly connected to one side of the first plastic package body, a second plastic package body is fixedly connected to the side, close to the chip, of the first plastic package body, a heat dissipation piece is fixedly connected into the second plastic package body, two symmetrically-distributed connecting strips are fixedly connected to the side, close to the chip, of the heat dissipation piece, and a detection plate attached to the chip is fixedly connected to the two connecting strips jointly. The detection plate is fixedly connected with a plurality of abutting strips. The contact state of the abutting strip and the heat dissipation piece is controlled through thermal expansion and cold contraction of the detection plate and the abutting strip, then the heat exchange efficiency of the chip and the outside world is controlled, when the chip is initially started, the heat exchange efficiency of the chip and the outside world is reduced, the chip rapidly reaches the normal working temperature, and after the chip works normally, the working temperature of the chip is reduced. And the heat exchange efficiency of the chip and the outside is increased, so that the chip can work normally without increasing the system power consumption and influencing the normal heat dissipation of the chip.

A method for attaching and detaching electronics structures during integrated circuit manufacturing is disclosed. A stack is formed including a carrier and an electronics structure. Between the carrier and electronics structure, a broadband absorber layer is provided. The broadband absorber layer includes broadband absorber material and polymer. A layer of ultraviolet (UV) light curable adhesive is also provided between the carrier and the electronics structure. UV light is directed through the carrier in order to cure the UV curable adhesive. The electronics structure can be processed while secured to the carrier. The electronics structure is removable from the carrier by transmitting a light pulse from a flashlamp through the carrier to heat the broadband absorber layer. The heat can decompose the polymer to permit removal of the electronics structure from the carrier.

According to some embodiments, methods, systems, and media for using synthetic images are presented. In some embodiments, a method involves obtaining a set of images related to an integrated circuit fabrication chamber, where the set of images includes at least a subset of synthetic images. Each synthetic image of the subset of synthetic images is a photo-realistic synthetic image. In some embodiments, at least a portion of the synthetic images presents an abnormal condition related to the fabrication chamber, and each image in the set of images presents at least one of: 1) a component of the fabrication chamber; 2) a process occurring in the fabrication chamber; or 3) a wafer property of a wafer being processed in the fabrication chamber. The method can also involve using the set of images to train a machine learning model, where the trained machine learning model can be used to predict the abnormal condition.

The invention discloses a self-adaptive leveling and aligning system for integrated circuit manufacturing and a working method of the self-adaptive leveling and aligning system, and relates to the technical field of nanoimprint, in particular to a nanoscale self-adaptive leveling imprint system. The system comprises a UV lamp movement module, a visual detection module, a laser interferometer detection module, a gantry supporting module, an XY-axis movement module, a vibration isolation module, a Z-axis movement module, a high-precision rotary table module, a wafer feeding detection module, a wafer fixing module, a mask fixing module and a self-adaptive leveling module. According to the nanoscale self-adaptive leveling imprinting system, through cooperation of all the movement modules, nanoscale imprinting work is achieved, the nanoscale production requirement of current imprinting photoetching equipment is met, meanwhile, self-adaptive leveling of the relative position between a wafer and a mask can be achieved through the nanoscale self-adaptive leveling imprinting system, and the high-precision leveling problem between an imprinting template and a substrate is solved.

The invention relates to the technical field of integrated circuit manufacturing power supply control, and discloses a wafer surface state monitoring system in integrated circuit processing, which comprises a radio frequency electrical parameter acquisition module, a pulse time sequence synchronous control module, a load transient impedance analysis module and a power supply power closed-loop regulation module, the system synchronously controls and locks a circuit free oscillation attenuation window after radio frequency energy is cut off through a pulse time sequence, analyzes a pulse relaxation time constant representing a power supply loop terminal load capacitance characteristic, and generates a power supply adjusting instruction according to the constant. Matching network impedance noise interference during steady-state high-power output of the radio-frequency power supply is effectively avoided, and the monitoring signal-to-noise ratio of wafer surface load characteristics and the power supply closed-loop regulation and control precision are improved.

The application provides a surface plasmon photolithography device and a preparation method for improving imaging aspect ratio, which can be applied to the fields of integrated circuit manufacturing and photolithography technology. The surface plasmon photolithography device comprises a metal reflection layer, an optical metamaterial photoresist layer and a mask layer which are sequentially stacked from bottom to top; wherein the optical metamaterial photoresist layer comprises a photoresist and a metal nanoparticle array embedded in the photoresist, the metal nanoparticle array comprises at least one metal nanoparticle layer, and the metal nanoparticle layer is composed of metal nanoparticles arranged periodically; the metal nanoparticle layer is arranged in parallel to the mask layer, wherein when the metal nanoparticle layer comprises a plurality of metal nanoparticle layers, the different metal nanoparticle layers are located in different planes. The application further provides a preparation method of the surface plasmon photolithography device for improving imaging aspect ratio.

The utility model discloses a wafer film covering device for integrated circuit manufacturing relates to the field of integrated circuit manufacturing, including closed box, be provided with the film covering mechanism in the upper end in closed box, be provided with wafer bearing mechanism in the lower end in closed box, be provided with the loading positioning mechanism in closed box, and the loading positioning mechanism includes the positioning support, a plurality of circumferentially uniformly arranged deflection rods are rotationally connected on the positioning support, the cross connecting disc is fixed in the top of deflection rod, and the adjacent cross connecting disc is hinged through the connecting rod, and the other end fixed with the material receiving tray of deflection rod, and the material receiving tray is fixed with the positioning ring, and the positioning cylinder is hinged between one deflection rod on the positioning support. The beneficial effect lies in: before loading, the wafer is supported through a plurality of circumferentially uniformly arranged material receiving trays, and then a plurality of positioning rings synchronous movement is centered clamped to the wafer, thereby realizing the centring positioning of wafer, and this positioning mode has high centring accuracy, positioning speed is fast, and is convenient for taking and placing.

The invention discloses an integrated circuit bump mass transfer method, which belongs to the field of integrated circuit manufacturing, and comprises the following steps of: 1, preparing a substrate; 2, printing a welding agent on the surface of the substrate; step 3, mounting a copper column on the welding agent and performing reflow soldering operation; step 4, filling the bottom of the copper column with glue; and step 5, bonding the flip chip to the upper part of the substrate and carrying out reflow soldering operation. Through the epoxy resin fixing mode, the problem that a large amount of copper needles are transferred for secondary reflow soldering is solved, and the reliability of products is improved to a great extent. The method can also be applied to similar reflow soldering process procedures with two times or multiple times.