367 results about "Ic manufacturing" patented technology

A method for data mining information obtained in an integrated circuit fabrication factory (“fab”) that includes steps of: (a) gathering data from the fab from one or more of systems, tools, and databases that produce data in the fab or collect data from the fab; (b) formatting the data and storing the formatted data in a source database; (c) extracting portions of the data for use in data mining in accordance with a user specified configuration file; (d) data mining the extracted portions of data in response to a user specified analysis configuration file; (e) storing results of data mining in a results database; and (f) providing access to the results.

This invention relates to organometallic compounds represented by the formula (L₁)_yM(L₂)_z-y wherein M is a Group 5 metal or a Group 6 metal, L₁ is a substituted or unsubstituted anionic 6 electron donor ligand, L₂ is the same or different and is (i) a substituted or unsubstituted anionic 2 electron donor ligand, (ii) a substituted or unsubstituted cationic 2 electron donor ligand, or (iii) a substituted or unsubstituted neutral 2 electron donor ligand; y is an integer of 1, and z is the valence of M; and wherein the sum of the oxidation number of M and the electric charges of L₁ and L₂ is equal to 0.; a process for producing the organometallic compounds; and a method for depositing a metal and/or metal carbide/nitride layer, e.g., a tungsten, tungsten nitride, tungsten carbide, or tungsten carbonitride layer, on a substrate by the thermal or plasma enhanced dissociation of the organometallic precursor compounds, e.g., by CVD or ALD techniques. The metal and/or metal carbide layer is useful as a liner or barrier layer for conducting metals and high dielectric constant materials in integrated circuit manufacturing.

An aqueous-based composition and process for removing photoresist and/or bottom anti-reflective coating (BARC) material from a substrate having such material(s) thereon. The aqueous-based composition includes a quaternary ammonium base, at least one co-solvent, and optionally a chelator. The composition achieves high-efficiency removal of photoresist and/or BARC material in the manufacture of integrated circuitry without adverse effect on metal species on the substrate, such as copper, and without damage to SiOC-based dielectric materials employed in the semiconductor architecture.

A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.

A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.

The invention belongs to the technical field of the industrial robot, particularly to a magnetic driver used in the silicon slice transmission robot playing the silicon slice transmission and positioning action in the vacuum in the IC manufacturing industry. The magnetic driver comprises a drive input part for realizing the torque introduction, a drive output part for realizing the torque output, a case part and a magnetic circuit part; in the drive input part, the drive input part is connected with an input axis through an end bond, and the external rotor is connected with the input axis through the bond, and fixed with the case through a deep groove ball bearing. In the magnetic circuit part, the internal rotor and the internal permanent magnet, the external rotor and the external permanent magnet all adopt the glue joint. The magnetic driver of the invention has compact structure, tight magnet distribution, small volume, large transmission torque, easy control, stable operation, convenient dismounting, small sport inertia, applied in the vacuum robot with higher cleanness.

A method and system for a reject management protocol within a back-end IC manufacturing process. In one method embodiment, the present invention implements a tracking process for a die-strip. The present invention also maintains an electronic die-strip map database, and utilizes the tracking process to update the electronic die-strip map database as the die-strip moves in an in-line fashion from one sub-station to another within the manufacturing process. Information used to update the database can originate from one or more automated visual camera systems used for quality assurance. In so doing, the present invention categorizes the die on the die-strip based on information maintained by the electronic die-strip map database. This information can be used for die sorting and for die rejection. In one embodiment, an identifying code is placed on each die strip that can automatically identify the die-strip using the automated camera systems.

A joystick control device having cursor correcting function, in which the conventional adjustable resistor is replaced by a photoelectric element for detecting the movement of the joystick, thereby eliminates the ill effects caused by mechanical attrition of resistor. Additionally, the parameter drifts caused by IC manufacturing processes are corrected using shift correction of joystick; therefore, every individual mass-produced IC shows similar good behavior.

High-speed interconnect systems for connecting two or more electrical elements are provided for on-chip interconnects. The manufacturing process to fabricate the interconnect structure using standard IC process is also provided. The interconnect systems consists of the electrical signal line, inhomogeneous dielectric systems, and with and without ground line, wherein inhomogeneous dielectric system consisting of the opened-trenches into the dielectric substrate or comb-shaped dielectrics to reduce the microwave loss. The signal lines located below and/or above the opened trenches. The opened trenches helps to reduce the microwave-loss induced due to the dielectric material and increases the on-chip interconnects bandwidth. Alternatively, dielectric system can have the structure based on fully electronic or electromagnetic crystal or quasi crystal with the line defect. The interconnect system, can be made in IC for on-chip interconnects using conventional IC manufacturing technology and yet to increase the interconnects-bandwidth.

An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

The invention discloses a clock generating circuit for a radio frequency identification (RFID) tag and the calibrating method of the clock generating circuit and relates to the technical field of RFID. The clock generating circuit provided by the invention comprises a numerical control tuned oscillator, a controller, a counter and a digital baseband processing circuit. A demodulation signal Rx output by tag radio frequency is input to the tag digital baseband processing circuit and the controller, and a power-on reset signal Rst output by a reset signal generating circuit arranged at the front end of the tag radio frequency is input to the controller, the counter and the tag digital baseband processing circuit. A calibration-enable signal Calib_en output by the tag digital baseband processing circuit is connected to the input ends of the controller and the counter. The count output Count of the counter is connected to the input end of the controller, and Rst_cnt output by the controller is connected to the input end of the counter. By using the clock generating circuit and the calibrating method thereof, the influences of an integrated circuit manufacturing process, an application environment and temperature on the bit rate precision, the code, the duty ratio and the like of the chip of the RFID tag can be avoided, the power consumption of the chip of the tag can be reduced, and the finished product rate of the chip can be increased.

The invention relates to a method to avoid damage to metal from high density plasma CVD that adopts plasma assistant CVD method to etch surface sediment a SiO2 layer after finishing etching the metal in IC manufacturing process. It induces sediment thin film medium to decrease the damage to metal from high density plasma CVD sediment process. It uses tetraethylorthosilicate as front driving material to form a SiO2 layer to supply good protection for metal.

The invention relates to a processing technology of a silicon slice for manufacturing of an integrated circuit, in particular to a method for doubly setting and accurately positioning the centre of the silicon slice. The method comprises the following steps of: rotating the silicon slice along centre direction; identifying edges of the silicon slice sequentially by linear image identification sensors having different precisions; determining positions of a flat edge or a notch; determining the offset of the centre of the silicon slice; and moving the silicon slice by using a bidirectional movement motor to make the centre of the silicon slice overlapped with a designed position. Therefore, a transmission error of the silicon slice existing in processing equipment in the process of semiconductor industry is avoided, and the precision of the set centre of the silicon slice is equal to 1 mu m by using the double-setting method.

One embodiment of the present invention provides a system that predicts a manufacturing yield of a chip. During operation, the system first receives a chip layout. Next, the system identifies hotspots within the chip layout, wherein a hotspot is a location within the chip layout wherein a yield-indicative variable value falls in a low manufacturable range. The system then obtains yield scores for the hotspots, wherein a yield score indicates a failure probability for a corresponding hotspot. Next, the system predicts the manufacturing yield for the chip based on the hotspots and the yield scores for the hotspots.

The circuit design platform of this invention comprises: a portal provided with a network platform to install functional modules and to allow users to utilize said functional modules after login; a circuit design tool module to connect at least one circuit design software and to generate a circuit design descriptive data file; a circuit design database connection module to connect at least one circuit design database; a circuit design simulation module to connect at least one circuit design simulation software; an integrated circuit manufacture connection module to connect website of at least one integrated circuit manufacturer and to provide at least one integrated circuit processing attributes analysis tool to suggest suited manufacture process; a circuit test connection module to connect at least one circuit test service provider to conduct online or offline tests; and a management module for management and fee calculation of access of the above functional modules.

The invention discloses a semiconductor chip thickness reduction method and in particular relates to thickness reduction technique on semiconductor chips, etc., belonging to the integrated circuit manufacturing technical field. The semiconductor chip thickness reduction method is characterized in that semiconductor apparatuses are arranged in lines and rows, with the pictured sides facing downward; the target sides semiconductor apparatuses adhere to a protecting film, developing into a square or a rectangle; a sheet object matching with the semiconductors in area and thickness is arranged at the periphery of the square or the rectangle and is made into a square or a rectangle so that the semiconductor at the middle can be even in bearing stress during the thickness reduction process; the reduction amount is determined and the semiconductors are reduced in thickness through grinding; after the thickness reduction process, post treatment is done to the thinned chips; finally, desirable chips are turned out. The method requires no change to current thickness reduction equipment and fixtures; the thinned chips are the same in thickness and are in consistency with the thickness of the wafer; the yield is high and the thinned chips have no defects and cracks at the brims.

The invention discloses a high-voltage capacitance coupling based control chip of an isolated type power converter. The control chip comprises a secondary-side control circuit, a high-voltage capacitance isolation coupling circuit and a primary-side control circuit. As the on-ship high-voltage capacitance isolation coupling circuit is adopted, the peripheral circuit of the system is simplified while the control and detection precision is guaranteed; and as an auxiliary winding, a separate isolation circuit or an off-ship bias and compensation circuit is accordingly unnecessary, the area of a circuit board is reduced, costs of separate devices are reduced and the system reliability is improved. As a capacitance structure compatible with the existing technology is adopted, a capacitor and a control circuit can be manufactured on one same wafer directly without reconstructing the existing IC manufacturing process, and performance improvement is accordingly achieved without adding the chip manufacturing cost.

The invention discloses a method for predicting and correcting an integrated circuit (IC) manufacturing process based on time series analysis, which belongs to the field of IC manufacturing techniques. The data related to the IC manufacturing results are separated by establishing a process model to extract the easy-to-control process parameters related to the manufacturing results; the influence values of the other parameters are arranged in time order to form a time sequence; the overall change trend of the time sequence (potential change trend of the manufacturing results) is predicted by using the time series analysis algorithm such as autoregressive integrated moving average (ARMA) model; the predicted process fluctuation is compensated by regulating the easy-to-control process parameters to stabilize the manufacturing result and thus to realize the dynamic treatment of process parameters. The invention optimizes the process control without hardware investment and increase in manufacturing cost, and greatly increases the stability of manufacturing results.

This invention relates to a method for sealing porosity of at least a portion of an outer porous surface of an article, said method comprising (i) applying a sealant solution on the outer porous surface of said article, (ii) infiltrating at least a portion of the outer porous surface with said sealant solution, and (iii) allowing the infiltrated sealant solution to react, thereby forming an infiltrated solid precipitate, said infiltrated solid precipitate sealing the porosity of at least a portion of the outer porous surface of said article. The method is useful, for example, in the protection of integrated circuit manufacturing equipment, internal chamber components, and electrostatic chuck manufacture.

The invention relates to a method for preparing uniform nanometer-hole SiO2 low-dielectric films. The method uses POSS hybrid polymers in uniform ordered chemical connection as a template, a uniform film is formed on a substrate through spin coating, spray coating or other film preparation methods; moreover, the method adopts an in-situ oxidative cracking process to prepare a uniform porous IC low-dielectric film material adapted to requirements of IC manufacture procedure, and realizes the precise control on hole size, uniformity and structure in the material by changing the structure of a network template and controlling the structure of organic components among networks.