45 results about "Integrated circuit fabrication" patented technology

Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and / or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time.

A radio frequency (RF) power generator adapted for coupling to a multi-station integrated circuit fabrication chamber may include an oscillator to provide a periodic signal and one or more preamplifiers each having an input port to receive a signal from the oscillator and having an output port to provide an amplified signal. The RF generator may additionally include one or more constant-gain amplifiers, each having an input port to receive a signal from the one or more preamplifiers, and an output port configured for coupling an amplified signal to an electrode for generating a plasma in an assigned station of the multi-station integrated circuit fabrication chamber.

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

A system and method are disclosed for a superconducting traveling-wave parametric amplifier (TWPA) with improved control and performance. In a preferred embodiment, the amplifier comprises an integrated array of symmetric rf-SQUIDs in a transmission line structure. A device was fabricated using niobium superconducting integrated circuits, and confirmed predicted performance, with a maximum gain up to 17 dB and a bandwidth of 4 GHz. A similar device can be applied as a low-noise, low-dissipation microwave amplifier for output from a superconducting quantum computer, or as a preamplifier, switch, or frequency converter for a sensitive microwave receiver, or as an output amplifier for a frequency-multiplexed superconducting detector array.

This invention discloses an integrated integrated circuit chip structure and its fabrication method. The invention relates to the field of thermal design and thermal control technology for integrated circuit chips, addressing the problem of weak heat transfer capabilities at high heat flux density points in existing integrated circuit chips. An integrated integrated circuit chip with electrical and heat dissipation functions is fabricated on a semiconductor substrate wafer and then packaged. By combining integrated circuit fabrication technology and microfluidic fabrication technology, microfluidic channels are directly fabricated on the semiconductor substrate wafer during integrated circuit chip fabrication, rather than being fabricated separately after chip fabrication. This enables the fabrication of heat dissipation structures for multiple integrated circuit chips, reducing the cost of chip heat dissipation. A cover plate guides the cooling medium into the microfluidic channels, allowing heat from high heat flux density points on the chip to directly exchange with the cooling medium after conduction through the substrate, reducing thermal resistance during heat loss and improving heat dissipation capacity.

In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source / drain (S / D) feature on the substrate, a gate stack on the substrate, a contact hole over the S / D feature; and a dummy feature over the S / D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S / D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Embodiments of the present disclosure are in the field of advanced integrated circuit structure fabrication, and more particularly in the field of 10 nanometer node and smaller integrated circuit structure fabrication and resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate including an N-well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate and surrounds the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric. A metal layer is above the semiconductor fin. A conductive layer is above the gate dielectric layer above the semiconductor fin, the conductive layer comprising titanium, nitrogen, and oxygen. A P-type metal gate layer is above the conductive layer above the semiconductor fin.

In accordance with some embodiments, methods, systems, and media for using synthetic images are provided. In some embodiments, a method involves obtaining a set of images associated with the integrated circuit fabrication chamber, wherein the set of images comprises at least a subset of synthetic images. Each synthetic image of the subset of synthetic images is a photo-realistic synthetic image. In some embodiments, at least a portion of the synthetic images represent an anomalous condition associated with the fabrication chamber, and each image in the set of images represents at least one of: 1) components of the fabrication chamber; 2) a process occurring in the fabrication chamber; or 3) wafer characteristics of a wafer being processed in the fabrication chamber. The method may further involve training a machine learning model using the set of images, wherein the trained machine learning model is usable to predict the anomalous condition.

In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source / drain (S / D) feature on the substrate, a gate stack on the substrate, a contact hole over the S / D feature; and a dummy feature over the S / D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S / D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.

A method for integrated circuit (IC) fabrication, where the method includes providing a substrate including a first patterned layer and a second patterned layer, where the second patterned layer is aligned to the first patterned layer; measuring an overlay error of the second patterned layer with the first patterned layer across the substrate; based on the measuring, obtaining the overlay error of the second patterned layer with the first patterned layer; and exposing the second patterned layer to a first flux from a first location specific directional process to correct the overlay error.

Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.

The invention relates to the technical field of ceramic materials, and particularly discloses a silicon carbide ceramic suction cup and a preparation method and application thereof.The silicon carbide ceramic suction cup is prepared from silicon carbide powder, hydroxypropyl methyl cellulose, a sintering aid, a pore forming agent, chopped modified carbon fibers and porous carbon loaded with Si3N4 particles; the preparation method comprises the following steps: mixing silicon carbide powder, hydroxypropyl methyl cellulose, chopped modified carbon fiber, porous carbon loaded with Si3N4 particles and a sintering aid; polyvinylpyrrolidone and deionized water are added; adding a pore-forming agent to obtain ceramic slurry, and then drying and aging the ceramic slurry; after vacuum pugging, putting into a mold, baking at high temperature, cooling and demolding to obtain a blank; sintering the blank at high temperature in a nitrogen atmosphere to obtain the silicon carbide ceramic sucker; the invention further discloses application of the silicon carbide ceramic suction cup in integrated circuit manufacturing equipment. The preparation method has the characteristic of further improving the comprehensive mechanical property of the silicon carbide ceramic sucker.

The present invention relates to a method and device system for preparing a dialkylamino metal complex and a triguanidine metal complex. The preparation method provided by the present invention combines the regulation and control of reaction conditions to promote reactions that are favorable for product generation, reduce the occurrence of side reactions, avoid the defect of introducing metal impurities using n-butyl lithium, and avoid the generation of components such as lithium salts that are inconvenient for subsequent separation, thereby facilitating product purification. Moreover, the dialkylamino metal complex and triguanidine metal complex prepared by the present invention meet the purity requirements for precursor materials in integrated circuit manufacturing.

An apparatus to estimate parameters of a radio frequency (RF) signal may include a voltage sensor configured to provide an indication of a voltage of the RF signal as well as a current sensor configured to provide an indication of current conducted by the RF signal. The apparatus may additionally include an analog-to-digital converter coupled to an output port of the voltage sensor and the current sensor, wherein the analog-to-digital converter is configured to provide digital representations of an instantaneous voltage and an instantaneous current of the RF signal. The apparatus may additionally include one or more processors configured to transform the digital representations of the instantaneous voltage and current into frequency domain representations of a complex voltage and complex current.

This invention discloses a frequency converter circuit structure and its fabrication method for a double-sided integrated Schottky diode, relating to the field of terahertz high-frequency devices and integrated circuit fabrication technology. The structure includes a first Schottky die, a second Schottky die, and a suspended microstrip metal circuit layer. Both dies have a front side that forms a Schottky junction. The first Schottky die is positioned with the suspended microstrip metal circuit layer attached to its first back side, and the second Schottky die is positioned with the suspended microstrip metal circuit layer attached to its second back side. The two dies are mirror-symmetrical about the suspended microstrip metal circuit layer. This allows for a "back-to-back" stacking of the two Schottky dies through three-dimensional integration, increasing the number of Schottky junctions without significantly increasing the two-dimensional area of ​​the circuit. This effectively improves the power handling capability and integration density of the frequency converter circuit, while optimizing energy coupling efficiency, making it particularly suitable for high-power frequency doubling sources in the terahertz band.

An integrated circuit structure (700), comprising: a first fin (702) which contains silicon; a second fin (702) which contains silicon; an insulating structure (704) between the first fin and the second fin; a first epitaxial source or drain structure (910) on the first fin, wherein the first epitaxial source or drain structure and the first fin meet at a first interface; a second epitaxial source or drain structure (910) on the second fin, wherein the second epitaxial source or drain structure and the second fin meet at a second interface; a dielectric material layer (714) extending continuously from above the first interface but below a top surface of the first epitaxial source or drain structure, along a section of a side wall of the first fin, on the insulating structure, along a section of a side wall of the second fin, to above the second interface but below a top surface of the second epitaxial source or drain structure.

A method for integrated circuit (IC) fabrication, where the method includes providing a substrate including a first patterned layer and a second patterned layer, where the second patterned layer is aligned to the first patterned layer; measuring an overlay error of the second patterned layer with the first patterned layer across the substrate; based on the measuring, obtaining the overlay error of the second patterned layer with the first patterned layer; and exposing the second patterned layer to a first flux from a first location specific directional process to correct the overlay error.

An apparatus is provided that includes an integrated circuit die that includes an uppermost metal layer of an integrated circuit fabrication process, a plurality of first bonding pads disposed on the uppermost metal layer at a first bonding pad pitch, a first additional metal layer disposed above the uppermost metal layer, and a plurality of second bonding pads disposed on the first additional metal layer at a second bonding pad pitch greater than the first bonding pad pitch. The apparatus further includes a plurality of conductors each electrically coupling a unique one of the first bonding pads to a corresponding one of the second bonding pads.

The utility model relates to the technical field of integrated circuit preparation, in particular to a photoetching system capable of improving pattern precision, which is applied to an exposure substrate, the exposure substrate comprises a first photoetching area and a second photoetching area, and the photoetching system comprises a first photoetching component and a second photoetching component which are arranged at an interval; the first photoetching assembly comprises a first exposure light source and a spatial light modulator, and the first exposure light source can emit projection light carrying an exposure pattern to the first photoetching area after passing through the spatial light modulator; the second photoetching assembly comprises a second exposure light source, the second exposure light source can emit a laser beam, and the laser beam is used for being projected to a second photoetching area; according to the utility model, the first photoetching assembly and the second photoetching assembly are combined for photoetching, so that the photoetching precision can be improved, and the photoetching efficiency can also be improved, thereby improving the quality of photoetching patterns.

The invention discloses a method for manufacturing an HDI product by using a PTFE material, and relates to the field of integrated circuit manufacturing. The method for manufacturing the HDI product by using the PTFE material comprises the following steps of: selecting a base material to process an inner layer pattern, laminating to form a multilayer board, processing a blind hole, degumming the blind hole, metalizing the blind hole, performing hole filling process treatment, and processing an outer layer pattern of the multilayer board to obtain the HDI product. According to the method for manufacturing the HDI product through the PTFE material, a carbon dioxide laser and picosecond laser composite technology is adopted for machining the blind hole, carbon dioxide laser can efficiently achieve blind hole forming, picosecond laser can accurately remove residual glue at the bottom of the hole, the key problem that the residual glue in machining of the blind hole of the PTFE base material is difficult to remove is solved through the synergistic effect of the carbon dioxide laser and the picosecond laser, the whole technology steps are closely connected, and the production efficiency is improved. Stable preparation of HDI products made of PTFE materials can be achieved, the conductivity, the signal transmission performance and the structural stability of the products are improved, and a base material processing scheme is provided for integrated circuit manufacturing.

An apparatus for determining the occurrence of an abnormal plasma event at or near a processing station in a multi-station integrated circuit fabrication chamber is disclosed. In certain embodiments, light emissions generated in response to the abnormal plasma event can be detected by at least one of a plurality of photosensors. A processor can cooperate with the plurality of photosensors to determine that the abnormal plasma event has occurred at or near a particular processing station in the multi-station integrated circuit fabrication chamber.

Methods and systems for filling gaps are disclosed. An exemplary method includes providing a substrate to a reaction chamber. The substrate includes a gap. The method further includes forming a convertible layer on the substrate and exposing the substrate to a conversion reactant. Thus, at least a portion of the convertible layer is converted into a gap fill fluid. The gap filling fluid at least partially fills the gap. The methods and systems are useful, for example, in the field of integrated circuit fabrication.

Some embodiments relate to a method that includes depositing a first layer of hard mask material over a layer of dielectric material; etching the first layer of the hard mask material, the etched first layer of hard mask material including an etched portion having a first lateral dimension; depositing a second layer of the hard mask material over the first layer of the hard mask material; etching at least a portion of the second layer of the hard mask material, while allowing a remaining portion of the hard mask material, to expose a portion of the layer of the dielectric material that has a second lateral dimension less than the first lateral dimension; and etching a trench into the layer of the dielectric material at the exposed portion of the layer of the dielectric material.

a transmission device and the fabricating method therefor, a quantum device integration component and a quantum computer, and belongs to the field of quantum information. The transmission device includes: a substrate; a micro-strip line layer formed on the substrate; a dielectric layer formed on the micro-strip line layer; and a ground layer and a port pad formed on the dielectric layer, wherein the ground layer is electrically connected to a ground plate of the micro-strip line layer, and the port pad is electrically connected to a conductor strip of the micro-strip line layer. The transmission device can be fabricated based on the existing integrated circuit fabricating process. In this transmission device, the micro-strip line layer can have a multi-layer stacking arrangement, so that high-density wiring on the substrate with a limited area can be achieved to adapt to the packaging needs of large-scale quantum chips.

In an integrated circuit (IC) fabrication process, devices or sub-circuits are fabricated in respective first and second electrical isolation regions. A back-to-back (B2B) diodes sub-circuit is fabricated in a third electrical isolation region, which includes a first diode whose cathode is connected with a first terminal and whose anode is connected with a second terminal, and a second diode whose anode is connected with the first terminal and whose cathode is connected with the second terminal. Electrostatic discharge protection is provided to the first and second electrical isolation regions by electrically connecting the first terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the first device or sub-circuit and the second terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the second device or sub-circuit. Thereafter, the first device or sub-circuit and the second device or sub-circuit are electrically connected.

Methods and systems for filling gaps are disclosed. An exemplary method includes providing a substrate to a reaction chamber. The substrate includes a gap. The method further includes at least partially filling the gap with a gap filling fluid. The method then includes subjecting the gap filling fluid to a transition treatment, thereby forming a transition material in the gap. The methods and systems are useful, for example, in the field of integrated circuit fabrication.

An apparatus to determine occurrence of an anomalous plasma event occurring at or near a process station of a multi-station integrated circuit fabrication chamber is disclosed. In particular embodiments, optical emissions generated responsive to the anomalous plasma event may be detected by at least one photosensor of a plurality of photosensors. A processor may cooperate with the plurality of photosensors to determine that the anomalous plasma event has occurred at or near by a particular process station of the multi-station integrated circuit fabrication chamber.

The invention belongs to the technical field of integrated circuit manufacturing, and discloses a P-type silicon needle structure, an electron field emission array cathode and a preparation method thereof. The method comprises the following steps: firstly, etching a plurality of windows arranged in an array on a silicon substrate coated with a protective layer; etching the windows by adopting anisotropic etching liquid, and forming an inverted frustum structure on each window; and finally, continuously carrying out electrochemical etching on the window by adopting an electrochemical etching solution, and forming a groove and a silicon needle extending from the bottom of the groove to the opening direction of the groove at the position of the window. The electron field emission array cathode is prepared by plating a tungsten film on the P-type silicon needle structure through a film plating process. The cathode in the invention has a silicon needle array structure with an ultra-large length-diameter ratio, so that the cathode has more excellent field emission performance.