17 results about "Integrated circuit fabrication" patented technology

This invention discloses an integrated integrated circuit chip structure and its fabrication method. The invention relates to the field of thermal design and thermal control technology for integrated circuit chips, addressing the problem of weak heat transfer capabilities at high heat flux density points in existing integrated circuit chips. An integrated integrated circuit chip with electrical and heat dissipation functions is fabricated on a semiconductor substrate wafer and then packaged. By combining integrated circuit fabrication technology and microfluidic fabrication technology, microfluidic channels are directly fabricated on the semiconductor substrate wafer during integrated circuit chip fabrication, rather than being fabricated separately after chip fabrication. This enables the fabrication of heat dissipation structures for multiple integrated circuit chips, reducing the cost of chip heat dissipation. A cover plate guides the cooling medium into the microfluidic channels, allowing heat from high heat flux density points on the chip to directly exchange with the cooling medium after conduction through the substrate, reducing thermal resistance during heat loss and improving heat dissipation capacity.

In accordance with some embodiments, methods, systems, and media for using synthetic images are provided. In some embodiments, a method involves obtaining a set of images associated with the integrated circuit fabrication chamber, wherein the set of images comprises at least a subset of synthetic images. Each synthetic image of the subset of synthetic images is a photo-realistic synthetic image. In some embodiments, at least a portion of the synthetic images represent an anomalous condition associated with the fabrication chamber, and each image in the set of images represents at least one of: 1) components of the fabrication chamber; 2) a process occurring in the fabrication chamber; or 3) wafer characteristics of a wafer being processed in the fabrication chamber. The method may further involve training a machine learning model using the set of images, wherein the trained machine learning model is usable to predict the anomalous condition.

A method for integrated circuit (IC) fabrication, where the method includes providing a substrate including a first patterned layer and a second patterned layer, where the second patterned layer is aligned to the first patterned layer; measuring an overlay error of the second patterned layer with the first patterned layer across the substrate; based on the measuring, obtaining the overlay error of the second patterned layer with the first patterned layer; and exposing the second patterned layer to a first flux from a first location specific directional process to correct the overlay error.

The invention relates to the technical field of ceramic materials, and particularly discloses a silicon carbide ceramic suction cup and a preparation method and application thereof.The silicon carbide ceramic suction cup is prepared from silicon carbide powder, hydroxypropyl methyl cellulose, a sintering aid, a pore forming agent, chopped modified carbon fibers and porous carbon loaded with Si3N4 particles; the preparation method comprises the following steps: mixing silicon carbide powder, hydroxypropyl methyl cellulose, chopped modified carbon fiber, porous carbon loaded with Si3N4 particles and a sintering aid; polyvinylpyrrolidone and deionized water are added; adding a pore-forming agent to obtain ceramic slurry, and then drying and aging the ceramic slurry; after vacuum pugging, putting into a mold, baking at high temperature, cooling and demolding to obtain a blank; sintering the blank at high temperature in a nitrogen atmosphere to obtain the silicon carbide ceramic sucker; the invention further discloses application of the silicon carbide ceramic suction cup in integrated circuit manufacturing equipment. The preparation method has the characteristic of further improving the comprehensive mechanical property of the silicon carbide ceramic sucker.

An apparatus to estimate parameters of a radio frequency (RF) signal may include a voltage sensor configured to provide an indication of a voltage of the RF signal as well as a current sensor configured to provide an indication of current conducted by the RF signal. The apparatus may additionally include an analog-to-digital converter coupled to an output port of the voltage sensor and the current sensor, wherein the analog-to-digital converter is configured to provide digital representations of an instantaneous voltage and an instantaneous current of the RF signal. The apparatus may additionally include one or more processors configured to transform the digital representations of the instantaneous voltage and current into frequency domain representations of a complex voltage and complex current.

This invention discloses a frequency converter circuit structure and its fabrication method for a double-sided integrated Schottky diode, relating to the field of terahertz high-frequency devices and integrated circuit fabrication technology. The structure includes a first Schottky die, a second Schottky die, and a suspended microstrip metal circuit layer. Both dies have a front side that forms a Schottky junction. The first Schottky die is positioned with the suspended microstrip metal circuit layer attached to its first back side, and the second Schottky die is positioned with the suspended microstrip metal circuit layer attached to its second back side. The two dies are mirror-symmetrical about the suspended microstrip metal circuit layer. This allows for a "back-to-back" stacking of the two Schottky dies through three-dimensional integration, increasing the number of Schottky junctions without significantly increasing the two-dimensional area of ​​the circuit. This effectively improves the power handling capability and integration density of the frequency converter circuit, while optimizing energy coupling efficiency, making it particularly suitable for high-power frequency doubling sources in the terahertz band.

A method for integrated circuit (IC) fabrication, where the method includes providing a substrate including a first patterned layer and a second patterned layer, where the second patterned layer is aligned to the first patterned layer; measuring an overlay error of the second patterned layer with the first patterned layer across the substrate; based on the measuring, obtaining the overlay error of the second patterned layer with the first patterned layer; and exposing the second patterned layer to a first flux from a first location specific directional process to correct the overlay error.

An apparatus is provided that includes an integrated circuit die that includes an uppermost metal layer of an integrated circuit fabrication process, a plurality of first bonding pads disposed on the uppermost metal layer at a first bonding pad pitch, a first additional metal layer disposed above the uppermost metal layer, and a plurality of second bonding pads disposed on the first additional metal layer at a second bonding pad pitch greater than the first bonding pad pitch. The apparatus further includes a plurality of conductors each electrically coupling a unique one of the first bonding pads to a corresponding one of the second bonding pads.

The invention discloses a method for manufacturing an HDI product by using a PTFE material, and relates to the field of integrated circuit manufacturing. The method for manufacturing the HDI product by using the PTFE material comprises the following steps of: selecting a base material to process an inner layer pattern, laminating to form a multilayer board, processing a blind hole, degumming the blind hole, metalizing the blind hole, performing hole filling process treatment, and processing an outer layer pattern of the multilayer board to obtain the HDI product. According to the method for manufacturing the HDI product through the PTFE material, a carbon dioxide laser and picosecond laser composite technology is adopted for machining the blind hole, carbon dioxide laser can efficiently achieve blind hole forming, picosecond laser can accurately remove residual glue at the bottom of the hole, the key problem that the residual glue in machining of the blind hole of the PTFE base material is difficult to remove is solved through the synergistic effect of the carbon dioxide laser and the picosecond laser, the whole technology steps are closely connected, and the production efficiency is improved. Stable preparation of HDI products made of PTFE materials can be achieved, the conductivity, the signal transmission performance and the structural stability of the products are improved, and a base material processing scheme is provided for integrated circuit manufacturing.

The invention belongs to the technical field of integrated circuit manufacturing, and discloses a P-type silicon needle structure, an electron field emission array cathode and a preparation method thereof. The method comprises the following steps: firstly, etching a plurality of windows arranged in an array on a silicon substrate coated with a protective layer; etching the windows by adopting anisotropic etching liquid, and forming an inverted frustum structure on each window; and finally, continuously carrying out electrochemical etching on the window by adopting an electrochemical etching solution, and forming a groove and a silicon needle extending from the bottom of the groove to the opening direction of the groove at the position of the window. The electron field emission array cathode is prepared by plating a tungsten film on the P-type silicon needle structure through a film plating process. The cathode in the invention has a silicon needle array structure with an ultra-large length-diameter ratio, so that the cathode has more excellent field emission performance.

The invention discloses a low-cost preparation method of a gold-plated thin film circuit, and belongs to the field of integrated circuit manufacturing, and the method comprises the following steps: S1, forming a seed layer on the surface of a substrate, forming a first intermediate product, enabling the seed layer to comprise a bottoming metal layer and a diffusion barrier metal layer, enabling the bottoming metal layer to cover the substrate, and enabling the diffusion barrier metal layer to cover the first intermediate product; the diffusion barrier metal layer covers the bottoming metal layer, and the thickness of the seed layer is marked as H1; s2, the first intermediate product is subjected to pattern conversion to form a second intermediate product with a patterned gold layer, the thickness of the patterned gold layer is H2, the thickness of gold required by the customer is recorded as Hcustomer, and H2 = Hcustomer; s3, an intermediate product III with an additional layer is formed, the thickness of the additional layer is H3, the additional layer is formed on the gold layer, and the thickness of the additional layer is recorded as H3; and S4, forming a gold-plated thin film circuit, which comprises the following steps: S41, performing dry etching to remove the seed layer and the additional layer which are not covered by the patterned gold layer. The manufacturing cost of the gold-plated film circuit can be reduced.

The technology disclosed in this patent document can be implemented to combine quantum computing and classical digital computing in a scalable computing system based on superconducting qubits using Josephson junctions that exhibit low dissipation long coherence times and can be fabricated with well-developed integrated circuit fabrication techniques. More specifically, the disclosed technology can be implemented by using two radio frequency (RF) superconducting quantum interference device (SQUID) circuits coupled in balance to preserve general symmetry and form a quantum readout circuit for reading and digitizing a superconducting qubit state with improved readout fidelity and sensitivity.

The application provides a preparation method and device system of dialkylamino metal halide and diimino bis(dialkylamino) metal complex, and the device system corresponds to the preparation method. The preparation method promotes the reaction of the formation of the favorable product, reduces the occurrence of the side reaction, avoids the defects of the introduction of metal impurities by using n-butyl lithium, avoids the generation of lithium salt and other components which are inconvenient for subsequent separation, and facilitates the purification of the product. Moreover, the dialkylamino metal halide and diimino bis(dialkylamino) metal complex prepared by the application meet the purity requirements of the precursor material in integrated circuit manufacturing.

The invention discloses an all-solid-state thin film lithium ion battery and a preparation method thereof. The all-solid-state thin film lithium ion battery structurally comprises a substrate, a positive current collector layer, a positive electrode layer, a solid electrolyte layer, a negative electrode layer and a negative current collector layer which are sequentially arranged from bottom to top. The flexible isolation layer is introduced into the battery structure, so that the erosion of water and oxygen to the solid electrolyte film in the manufacturing process can be effectively isolated, the atmospheric permeation is continuously blocked in the battery using process, the battery reliability is remarkably improved, and the cycle life of the battery is remarkably prolonged. In addition, the arrangement of the flexible isolation layer can relieve the stress generated by the volume expansion of the battery in the charging and discharging process, and enhances the reliability and mechanical strength of the battery. The method is suitable for an integrated circuit manufacturing process, and large-scale production and integration with high precision, high consistency and low cost can be realized.

The application discloses a kind of hydrogen bond induced self-assembly and the layered homopolymer supramolecule with feature size below 5nm and preparation method thereof.The prepared homopolymer supramolecule is based on polyvinylimidazole, is constructed by hydrogen bond interaction with long alkyl chain carboxylic acid / alcohol (as hydrogen bond donor), and is simply synthesized by using hot pouring process.The material can complete efficient self-assembly simultaneously in the hot pouring process, and obtain low-layered nanometer pattern below 5nm.The application realizes microphase separation by hydrogen bond induced self-assembly, and the feature size of pattern can be accurately controlled by changing the length of alkane side chain, to provide a convenient and efficient new strategy for super-high resolution patterning material used in integrated circuit manufacturing field.

Embodiments relate to a three-dimensional integrated circuit (3D IC) fabrication process involving wafer-to-wafer bonding of a first wafer to a second wafer. The process includes partially cutting trenches in the second wafer's streets, aligning interconnects between the two wafers, and coupling them to form a wafer stack. The second wafer is then thinned to expose the partially cut trenches, and materials between the second wafer's dies are removed to expose die pads on the first wafer for external connection, enabling the creation of a 3D IC with improved connectivity and functionality.