752 results about "Metal silicide" patented technology

A method includes forming a bottom-tier transistor and a top-tier transistor over the bottom-tier transistor, the top-tier transistor comprising a first channel layer, a first gate structure around the first channel layer, and a plurality of first source / drain regions on opposite sides of the first channel layer; forming a first dielectric layer over the first source / drain regions of the top-tier transistor; etching the first dielectric layer to form a first opening exposing one of the first source / drain regions of the top-tier transistor; selectively forming a first metal silicide on the one of the first source / drain regions; selectively forming a first metal cap on the first metal silicide and not on the first dielectric layer; forming a front-side contact on the first metal cap.

The invention relates to the field of superhigh-temperature ceramic coating precursor powder, in particular to a preparation method of ZrB2-SiC-ZrSix gradient superhigh-temperature ceramic coating precursor powder. The preparation method comprises the following steps: firstly, taking Zr, B4C and Si as raw materials, mixing according to a proportion, and then briquetting; and putting the briquetting material into a combustion synthesis furnace, and starting a combustion synthesis reaction in a vacuum environment. And after the combustion synthesis reaction is finished, taking out a product, and carrying out secondary crushing to obtain ZrB2-SiC-ZrSix gradient ultra-high-temperature ceramic coating precursor powder. The problem of high-temperature cracking caused by large difference of thermal expansion coefficients of components of a traditional alloying system and a graphite matrix is avoided. The problem that a traditional SiC-based system is difficult to alloy is solved, alloying compounding of the amorphous metal silicide ZrSix is coordinated, and the high-oxygen-barrier strengthening method has the advantage that high-oxygen-barrier strengthening is achieved through multiphase alloying of powder.

Provided are metal silicide contact forming processes including providing a substrate having a bottom crystalline silicon and di-electric sidewalls. This may be followed by metal layer deposition to form metal layer selectively on the bottom crystalline silicon using a metal halide precursor and a reducing agent. A ratio of a reducing agent flow rate to a metal halide precursor flow rate is at least 10:1, or 10:1-10,000:1. After the metal layer deposition, the substrate is annealed to convert the metal layer to a metal silicide layer without any substrate contamination.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and forming a gate structure, a side wall and an active / drain region on the substrate; forming a protective layer which covers the substrate and at least covers part of the side wall, close to the substrate, of the side wall; removing a part of the side wall which is not covered by the protective layer; removing the protective layer; forming metal silicide on the gate structure and / or the source / drain region; and forming a dielectric layer covering the gate structure, the side wall, the source / drain region and the substrate, and forming a contact hole exposing the metal silicide in the dielectric layer. The stress proximity technology is arranged before the metal silicide is formed, and when part of the side wall is removed, the protection layer is adopted to protect the substrate and part of the side wall close to the substrate, so that the loss of the substrate can be avoided on the basis of improving the filling window and improving the stress, and the reliability of the device is improved. Therefore, the loss of the metal silicide caused by the removal of the side wall is avoided, the etching through phenomenon of the metal silicide is avoided, and finally the performance of the semiconductor device is improved.

Integrated circuit (IC) die packages including a glass with conductive through-glass vias (TGVs). The TGVs are lined with a buffer comprising an inorganic material having a low elastic (Young's) modulus. The buffer may thereby accommodate internal stress between the glass and through via metallization formed over the buffer. The compliant inorganic material may be a metal or metal alloy, for example, different than that of the via metallization. The inorganic material may also be a metal nitride, metal silicide, or metal carbide. A TGV buffer may be one material layer of a stack comprising two or more material layers deposited upon TGV sidewall surfaces. A routing structure may be built-up on at least one side of the glass and IC die assembled to the routing structure. The buffer Ipresent within the TGVs may be absent from metal features of the routing structure.

The invention relates to the technical field of batteries, in particular to a negative electrode material, a preparation method thereof and a battery. The negative electrode material comprises a silicon nano material; the metal silicide layer at least partially coats the surface of the silicon nano material; the nitrogen and sulfur doped carbon layer at least partially coats the surface of the metal silicide; and the thickness of the metal silicide layer is greater than that of the nitrogen and sulfur doped carbon layer. According to the negative electrode material, the preparation method thereof and the battery provided by the invention, the coating structure of the negative electrode material is optimized, and the metal silicide / heteroatom doped carbon double-layer coated silicon nano material can be prepared by adopting a synthesis method which is low in energy consumption and capable of constructing a functional multi-layer coating structure, so that the long cycle life and the high-rate fast charging performance can be considered at the same time.

The invention discloses a preparation method of a toughening environmental barrier coating, and relates to a preparation method of a coating. The invention aims to solve the problem of poor fracture toughness of the existing environmental barrier coating. The method comprises the following steps: 1, pretreating a base material; 2, preparing a bonding layer; and 3, preparing the environmental barrier layer. The high-melting-point metal silicide prepared on the surface of the base material or the bonding layer compounded by the high-melting-point metal silicide and the rare earth silicate has excellent temperature resistance and good interface bonding strength, and due to the addition of the rare earth silicate, the expansion coefficient of the bonding layer is highly matched with that of the base material; according to the prepared yttrium oxide stabilized zirconia fiber, mullite fiber or silicon carbide fiber reinforced rare earth silicate environmental barrier layer, the fracture toughness of pure Yb2SiO5 is improved to 6.5 MPa.m < 1 / 2 >-8.0 MPa.m < 1 / 2 > from about 1.85 MPa.m < 1 / 2 >. The strengthening and toughening environmental barrier coating prepared by the invention has very important significance on development of thermal protection coatings of hot end parts of aircrafts with high thrust-weight ratios in China.

Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.

The invention discloses a semiconductor test structure and a manufacturing method thereof, and belongs to the technical field of semiconductors, and the test structure at least comprises a substrate which comprises a plurality of active regions which are arranged in parallel; the grid electrodes are arranged on the active areas in parallel, grid electrode dielectric layers are arranged between the grid electrodes and the active areas, and the grid electrodes are perpendicular to the active areas; the first metal silicide is at least arranged on a part of the grid electrode and the side wall of one side of the grid electrode and extends to the active region; at least one test hole group is formed in a single active region between adjacent grids, and the test hole group and the first metal silicide are distributed in a staggered manner; the connecting hole is formed in the active region on one side of the plurality of grids; the at least one first test point is arranged on the test hole group and is connected with the test hole group; and the second test point is arranged on the connecting hole and is connected with the connecting hole. According to the semiconductor test structure and the manufacturing method thereof provided by the invention, the manufacturing quality of the metal silicide can be fed back in time, and the monitoring efficiency is improved.

A semiconductor device may include a semiconductor substrate including a horizontal portion and a vertical portion protruding upward from the horizontal portion, a bit line on the semiconductor substrate and extending in a first direction parallel to a bottom surface of the semiconductor substrate, a word line on the bit line and extending in a second direction parallel to the bottom surface of the semiconductor substrate that is different from the first direction, a semiconductor pattern on the vertical portion of the semiconductor substrate and extending in a third direction perpendicular to the bottom surface of the semiconductor substrate, and a metal silicide pattern between the semiconductor pattern and the bit line. The semiconductor pattern may include a source / drain region adjacent to the bit line and a channel region on the source / drain region, and the metal silicide pattern may be in contact with the source / drain region and the bit line.

The invention provides a method for forming a semiconductor device, which comprises the following steps of: removing a pad oxide layer of a medium-voltage region and pad oxide layers of a source region and a drain region of a high-voltage region at the same time instead of removing pad oxide layer residues caused by the pad oxide layers when a second gate oxide layer is etched, so that the pad oxide layer with beak defects is removed; in other words, no pad oxide layer remains in the source region and the drain region of the high-voltage region in the subsequent etching for forming the gate structure, so that the metal silicide layer formed on the semiconductor substrate of the source region and the drain region of the high-voltage region in the subsequent process is not influenced; and the contact between a plug formed on the source region and the drain region of the high-voltage region and the substrate is not influenced, so that the electrical property and the reliability of the high-voltage device are not influenced.

A semiconductor structure and a fabricating method are provided. The semiconductor structure includes a substrate, active pillars, gate structures, a metal silicide layer, and a spacer. The active pillars are positioned on the substrate and are arranged in an array, and the active pillars extend along a direction perpendicular to the substrate. The gate structures are arranged at intervals along a first direction, and the gate structures are arranged surrounding a part of the active pillars. The metal silicide layer is positioned on a top surface of the active pillar, and a projection of the metal silicide layer on the substrate is overlapped with a projection of the top surface of the active pillar on the substrate. The spacer is positioned between adjacent gate structures and adjacent active pillars, and a height of the spacer is higher than a height of a top surface of the metal silicide layer.

The invention discloses an SRAM (Static Random Access Memory) memory cell, a static random access memory and a preparation method thereof, and belongs to the field of semiconductors. Channel directions of two transmission gate transistors are set as a first direction, channel directions of two pull-up transistors are set as a second direction, and channel directions of two pull-down transistors are set as a third direction; the third direction and the first direction are crystal orientations of the same family, and the two pull-up transistors are arranged in a sinking manner; active regions of the pull-up transistor and other transistors are staggered so as to improve the heat dissipation capability; in order to manufacture the structure, a corresponding preparation method is designed, in the preparation process, the grid electrode of the pull-up transistor is stepped, so that the grid electrode of the pull-up transistor can be connected with the active region of the transmission grid transistor through a metal silicification technology, the contact resistance is greatly reduced, and the performance of the device is improved. Therefore, the performance of the whole device is improved, and the read-write speed is higher than that of the prior art under the same condition.

Methods for selective deposition are described herein. The method includes depositing an oxide on a first portion of a substrate surface selected from the group consisting of a metal surface, a metal nitride surface, and a metal silicide surface. The method further includes selectively depositing a molybdenum film on a second portion of the surface of the substrate, the second portion having no oxide deposited thereon.

The invention discloses a semiconductor test structure and a test method thereof. According to the invention, the P-type well regions and the N-type well regions which are alternately distributed are formed in the active region, and the S-shaped active region metal silicide strips serving as S-shaped test structures are formed on the surface of the active region; the two ends of the snakelike active region metal silicide strip are located above the well regions of different conduction types respectively, so that the snakelike active region metal silicide strip covers the surfaces of the PN junctions which are connected in series; through the snakelike test structure, the square resistance of the snakelike active region metal silicide strip can be accurately measured, whether electric leakage exists in the substrate or not is detected, and whether continuity of the snakelike active region metal silicide strip is abnormal or not and whether bridging exists or not is detected. Furthermore, a cross comb-shaped test structure used for measuring the breakdown voltage of the metal silicide layer of the active region to judge whether the isolation between the active regions meets the requirement is formed in the region where the snake-shaped test structure is located, so that the comprehensiveness of the test structure can be improved, and the test area of a test pattern in a chip is saved; the area utilization rate is effectively improved.

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the steps: enabling a pad oxide layer and a silicide barrier layer to cover the surfaces of a first region and a second region in a conformal manner, and removing the silicide barrier layer of the first region; the sacrificial material layer fills and covers the surfaces of the first region and the second region; part of the sacrificial material layer is removed to be lower than the preset height of the gate structure, the exposed pad oxide layer is removed, and the first region side wall structure is thinned to expose the top wall of the gate structure; and removing the sacrificial material layer, thinning the side wall structure in the first region, removing the pad oxide layer, exposing the surface of the substrate in the first region, and forming a metal silicide. After the silicide barrier layer is removed and before the side wall structure is thinned, the sacrificial material layer is arranged to cover the pad oxide layer on the surface of the substrate, the line width effect is reduced, meanwhile, the surface material of the substrate and doping distribution are protected against loss, and the limitation of the SPT technology on the metal silicide technology is reduced; and meanwhile, the etching selection ratio of the pad oxide layer removal and the first thinning process is set, so that the protection of the sacrificial material layer on the pad oxide layer is ensured.

The invention discloses a method for measuring metal silicide resistance in a semiconductor device, a polycrystalline silicon size monitoring method and a product electrical property monitoring method. The method comprises the following steps: respectively applying a high potential or a low potential to two ends of a square resistor corresponding to the metal silicide, and measuring the total resistance value of the square resistor of the metal silicide; because the total resistance value of the metal silicide square resistor is interfered by the resistor of the ion implantation layer, the total resistance value of the metal silicide square resistor is used as the metal silicide resistor after the interference of the resistor of the ion implantation layer is removed. According to the method, the interference problem of the ion implantation layer is innovatively proposed and is removed through an accurate calculation method, so that the actual resistance value of the metal silicide which is not interfered by the ion implantation layer can be obtained. Compared with a traditional measurement method, the measurement result of the method is more accurate and reliable, and a solid data basis is provided for subsequent polycrystalline silicon size monitoring and semiconductor device performance evaluation.

The invention provides an epitaxial process concentration monitoring method, which comprises the following steps of: providing a substrate, and forming an N-type epitaxial layer on the substrate; a deep groove is formed in the epitaxial layer, P columns are formed in the deep groove through epitaxy, and one P-type column and one corresponding adjacent N-type column form a super junction unit; selecting at least one test area on the P column to carry out P-type ion heavy doping injection so as to form a P-type heavy doping area; and forming a metal silicide layer of which the resistance value is not higher than a preset value on the P-type heavily doped region, and performing an electrical test by using the metal silicide layer to obtain a resistance test value of the P column, the resistance test value being used for representing the quantity of charges filled in the deep trench epitaxy so as to monitor the PN charge matching state of the super junction. According to the method, the metal silicide process which is simple in process and short in period is adopted, and the purpose of monitoring the epitaxial process concentration can be achieved quickly.

The invention provides a contact hole test structure and a manufacturing method thereof, a method for detecting excessive etching of a contact hole and a semiconductor device structure. The contact hole test structure comprises a substrate; the first well region is located in the substrate, and the second well region is located in the first well region; the second metal silicide layer is positioned on the surface of the second well region; the first metal silicide layer is positioned on the surface of a part of the first well region; the first metal silicide layer and the second metal silicide layer are arranged at an interval; the dielectric layer is located on the first metal silicide layer and the second metal silicide layer, the first contact hole structure is located in the dielectric layer and electrically connected with the first metal silicide layer, and the second contact hole structure is electrically connected with the second metal silicide layer. The first test end is electrically connected with the first contact hole structure; and the second test end is electrically connected with the second contact hole structure. According to the invention, whether the etching through phenomenon occurs in the contact hole can be judged through the obtained electrical performance test data, and more time and labor are saved.

The invention provides a chip, a manufacturing method thereof and electronic equipment, the chip comprises a transistor, a metal silicide layer, an etching stop layer, an interlayer dielectric layer and a plurality of first contact holes, the metal silicide layer is at least arranged on a source electrode and a drain electrode of the transistor, and the first contact holes penetrate through the etching stop layer and the interlayer dielectric layer; the chip further comprises a barrier layer, the barrier layer is arranged between the metal silicide layer and the etching stop layer, and under the etching condition of the etching stop layer, the etching rate of the etching stop layer is larger than that of the barrier layer. Therefore, when the etching stop layer is etched, the barrier layer can be prevented from being etched, so that the barrier layer can play a role in stopping etching, the metal silicide layer is prevented from being etched, the metal silicide layer is protected, a source electrode and a drain electrode in the transistor cannot be influenced even if the metal silicide layer is thin, and the reliability of the transistor is improved. And the source electrode and the drain electrode are protected, so that the manufacturing yield of the chip is improved.

The invention discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The manufacturing method comprises the steps that a substrate is provided, a gate structure and side wall structures on the two sides are formed on the substrate, and a lightly doped region and a heavily doped region are formed in the portions, on the two sides of the gate structure, of the substrate; forming a first etching stop layer covering the substrate, the gate structure and the side wall structure on the substrate; forming an opening in the first etching stop layer by etching, wherein the opening exposes a part of the heavily doped region and at least a part of the gate structure; forming a compensation epitaxial layer in the opening, wherein the compensation epitaxial layer covers a part of the heavily doped region; at least metallizing the compensation epitaxial layer to form a metal silicide layer; forming an interlayer dielectric layer on the substrate and the metal silicide layer; etching the interlayer dielectric layer to the metal silicide layer to form a connecting hole; and forming a barrier layer and a conductive structure in the connecting hole. According to the semiconductor device and the manufacturing method thereof, the saturation current can be improved, and the performance and the yield of the semiconductor device can be improved.

The invention relates to a preparation method of an LDMOS device and the LDMOS device, and relates to the technical field of semiconductors, in the preparation method, a first etching machine table is adopted for a self-aligned polycrystalline silicon material layer, a second etching machine table is adopted for a shielding material layer, and special etching machine tables are adopted for different materials, so that the etching precision can be improved, and the manufacturing cost is reduced. Therefore, the material loss caused by incomplete etching of the material needing to be etched or over-etching during etching is avoided, and the yield of the product is improved. In addition, according to the formed LDMOS device, the metal silicide covering the shielding layer serves as a supplementary grid electrode of the grid electrode of the LDMOS device, so that the length of a conducting channel is increased, and the LDMOS device has better high voltage resistance.

The invention provides a silicon carbide transistor structure and a preparation method thereof. The method comprises the steps that a silicon carbide substrate is formed, a well region is formed in the silicon carbide substrate, and a first doped region is formed in the well region; forming a groove in the first doped region and executing ion implantation to form a second doped region extending into the well region; forming a gate structure and a gate dielectric layer completely wrapping the gate structure on the top surface of the silicon carbide substrate; and forming a contact hole which penetrates through the gate dielectric layer and at least partially exposes the second doped region, and forming a metal silicide layer in contact with the second doped region in the contact hole. According to the invention, the first doped region formed in the well region is etched to form the groove, and then the second doped region extending into the well region is formed at the groove, so that the region voltage drop of the first doped region can be reduced, and the purpose of effectively reducing the VFSD of the device is achieved.

The invention provides a method for manufacturing a semiconductor structure, which comprises the following steps of: providing a substrate comprising a substrate layer and a gate structure, forming a side wall on the side surface of the gate structure, forming an active region and a drain region on the upper surface layer of the substrate layer, and forming metal silicide layers on the source region and the drain region; putting the substrate into an etching cavity and carrying out surface treatment by adopting oxygen plasma so as to generate a protective oxide layer on the metal silicide layer; thinning the side wall; and forming a CESL stress layer, an interlayer dielectric layer and a contact hole. According to the invention, the problem of metal silicide loss can be effectively improved, the loss of the metal silicide is only limited to the oxidation loss part, the loss cannot be increased due to the increase of the etching amount of the side wall, and the process window can be expanded. In addition, the oxygen plasma surface treatment is carried out in the etching cavity, so that the process cavity does not need to be replaced, and the process simplification and the cost reduction are facilitated. And the treatment temperature is relatively low, so that the stability of the metal silicide is facilitated.

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate, and forming a doped polycrystalline silicon electrode layer on the substrate; a first side wall, a second side wall and a protection side wall are formed on the side surface of the doped polycrystalline silicon electrode layer; an ion implantation process is carried out on the substrate, a first doped region and a second doped region are formed, and the first doped region and the second doped region are located on the two sides of the doped polycrystalline silicon electrode layer respectively; patterning the second side wall with partial height to expose the side surface of the first side wall with partial height; removing the protection side wall and the exposed first side wall with partial height, and exposing the side surface of the doped polycrystalline silicon electrode layer with partial height; a first metal silicide layer is formed in the doped polycrystalline silicon electrode layer, a second metal silicide layer is formed in the first doped region and the second doped region, and the thickness of the first metal silicide layer is larger than that of the second metal silicide layer.

Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.

Techniques described herein include forming respective (different) types of metal silicide layers for p-type source / drain regions and n-type source / drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source / drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source / drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source / drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source / drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source / drain region. This reduces the contact resistance for both p-type source / drain regions and n-type source / drain regions.

Disclosed in the present application are a split-gate floating-gate flash memory device and a manufacturing method therefor. The method comprises: S1: providing a flash memory device, the flash memory device comprising a substrate and gate structures grown on the substrate, select gate protection layers being formed at the tops of the gate structures, third spacer dielectric layers being formed on both sides of each gate structure, and source-drain regions being formed in the substrate located on both sides of each gate structure; S2: using the select gate protection layers and the third spacer dielectric layer as hard masks to perform self-aligned etching on the source-drain regions, so as to form shallow trench contact holes; and S3, depositing metal silicide in the shallow trench contact holes. The solution of the present application can solve the problem of interference in related technologies between adjacent units during programming processes.

The invention relates to a method for realizing an integrated ultrahigh-temperature environmental barrier composite coating, which comprises the following steps of: pre-coating a high-entropy alloy or a boride layer thereof and a molybdenum metal pre-coating on the surface of a substrate, and carrying out silicon-boron co-embedding deposition through a pre-oxidation process to form an ordered Mo-Si-B multi-layer structure in the molybdenum metal layer; a composite coating composed of metal silicide and silicon dioxide is cold-sprayed on the Mo-Si-B multilayer structure, and a composite self-healing layer of a three-dimensional network structure is formed through high-temperature thermal sintering; and alloy oxide is subjected to cold spraying or magnetron sputtering outside the composite self-healing layer to form the water vapor resistant layer. According to the invention, through an integrated coating preparation process, advantages of different components are complementary, and effective protection of various refractory alloys in a wide temperature range (room temperature-1700 DEG C) can be realized.

An integrated circuit device includes gate structures arranged on an upper surface of a substrate, a first impurity region arranged at the upper surface of the substrate, wherein the first impurity region is adjacent to a first gate structure of the gate structures, a first contact pad arranged on the upper surface of the substrate, wherein the first contact pad comprises a recess recessed in a vertical direction perpendicular to the upper surface of the substrate from an upper surface of the first contact pad toward the upper surface of the substrate, a metal silicide layer disposed in the recess, and a contact via connected to the metal silicide layer and extending in the vertical direction. A lower end of the contact via is disposed in the recess and connected to the metal silicide layer. The contact via is spaced apart from the substrate in the vertical direction.