528 results about "Metal silicide" patented technology

Provided are metal silicide contact forming processes including providing a substrate having a bottom crystalline silicon and di-electric sidewalls. This may be followed by metal layer deposition to form metal layer selectively on the bottom crystalline silicon using a metal halide precursor and a reducing agent. A ratio of a reducing agent flow rate to a metal halide precursor flow rate is at least 10:1, or 10:1-10,000:1. After the metal layer deposition, the substrate is annealed to convert the metal layer to a metal silicide layer without any substrate contamination.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and forming a gate structure, a side wall and an active / drain region on the substrate; forming a protective layer which covers the substrate and at least covers part of the side wall, close to the substrate, of the side wall; removing a part of the side wall which is not covered by the protective layer; removing the protective layer; forming metal silicide on the gate structure and / or the source / drain region; and forming a dielectric layer covering the gate structure, the side wall, the source / drain region and the substrate, and forming a contact hole exposing the metal silicide in the dielectric layer. The stress proximity technology is arranged before the metal silicide is formed, and when part of the side wall is removed, the protection layer is adopted to protect the substrate and part of the side wall close to the substrate, so that the loss of the substrate can be avoided on the basis of improving the filling window and improving the stress, and the reliability of the device is improved. Therefore, the loss of the metal silicide caused by the removal of the side wall is avoided, the etching through phenomenon of the metal silicide is avoided, and finally the performance of the semiconductor device is improved.

The invention relates to the technical field of batteries, in particular to a negative electrode material, a preparation method thereof and a battery. The negative electrode material comprises a silicon nano material; the metal silicide layer at least partially coats the surface of the silicon nano material; the nitrogen and sulfur doped carbon layer at least partially coats the surface of the metal silicide; and the thickness of the metal silicide layer is greater than that of the nitrogen and sulfur doped carbon layer. According to the negative electrode material, the preparation method thereof and the battery provided by the invention, the coating structure of the negative electrode material is optimized, and the metal silicide / heteroatom doped carbon double-layer coated silicon nano material can be prepared by adopting a synthesis method which is low in energy consumption and capable of constructing a functional multi-layer coating structure, so that the long cycle life and the high-rate fast charging performance can be considered at the same time.

The invention discloses a preparation method of a toughening environmental barrier coating, and relates to a preparation method of a coating. The invention aims to solve the problem of poor fracture toughness of the existing environmental barrier coating. The method comprises the following steps: 1, pretreating a base material; 2, preparing a bonding layer; and 3, preparing the environmental barrier layer. The high-melting-point metal silicide prepared on the surface of the base material or the bonding layer compounded by the high-melting-point metal silicide and the rare earth silicate has excellent temperature resistance and good interface bonding strength, and due to the addition of the rare earth silicate, the expansion coefficient of the bonding layer is highly matched with that of the base material; according to the prepared yttrium oxide stabilized zirconia fiber, mullite fiber or silicon carbide fiber reinforced rare earth silicate environmental barrier layer, the fracture toughness of pure Yb2SiO5 is improved to 6.5 MPa.m < 1 / 2 >-8.0 MPa.m < 1 / 2 > from about 1.85 MPa.m < 1 / 2 >. The strengthening and toughening environmental barrier coating prepared by the invention has very important significance on development of thermal protection coatings of hot end parts of aircrafts with high thrust-weight ratios in China.

A semiconductor device may include a semiconductor substrate including a horizontal portion and a vertical portion protruding upward from the horizontal portion, a bit line on the semiconductor substrate and extending in a first direction parallel to a bottom surface of the semiconductor substrate, a word line on the bit line and extending in a second direction parallel to the bottom surface of the semiconductor substrate that is different from the first direction, a semiconductor pattern on the vertical portion of the semiconductor substrate and extending in a third direction perpendicular to the bottom surface of the semiconductor substrate, and a metal silicide pattern between the semiconductor pattern and the bit line. The semiconductor pattern may include a source / drain region adjacent to the bit line and a channel region on the source / drain region, and the metal silicide pattern may be in contact with the source / drain region and the bit line.

A semiconductor structure and a fabricating method are provided. The semiconductor structure includes a substrate, active pillars, gate structures, a metal silicide layer, and a spacer. The active pillars are positioned on the substrate and are arranged in an array, and the active pillars extend along a direction perpendicular to the substrate. The gate structures are arranged at intervals along a first direction, and the gate structures are arranged surrounding a part of the active pillars. The metal silicide layer is positioned on a top surface of the active pillar, and a projection of the metal silicide layer on the substrate is overlapped with a projection of the top surface of the active pillar on the substrate. The spacer is positioned between adjacent gate structures and adjacent active pillars, and a height of the spacer is higher than a height of a top surface of the metal silicide layer.

The invention discloses an SRAM (Static Random Access Memory) memory cell, a static random access memory and a preparation method thereof, and belongs to the field of semiconductors. Channel directions of two transmission gate transistors are set as a first direction, channel directions of two pull-up transistors are set as a second direction, and channel directions of two pull-down transistors are set as a third direction; the third direction and the first direction are crystal orientations of the same family, and the two pull-up transistors are arranged in a sinking manner; active regions of the pull-up transistor and other transistors are staggered so as to improve the heat dissipation capability; in order to manufacture the structure, a corresponding preparation method is designed, in the preparation process, the grid electrode of the pull-up transistor is stepped, so that the grid electrode of the pull-up transistor can be connected with the active region of the transmission grid transistor through a metal silicification technology, the contact resistance is greatly reduced, and the performance of the device is improved. Therefore, the performance of the whole device is improved, and the read-write speed is higher than that of the prior art under the same condition.

The invention discloses a semiconductor test structure and a test method thereof. According to the invention, the P-type well regions and the N-type well regions which are alternately distributed are formed in the active region, and the S-shaped active region metal silicide strips serving as S-shaped test structures are formed on the surface of the active region; the two ends of the snakelike active region metal silicide strip are located above the well regions of different conduction types respectively, so that the snakelike active region metal silicide strip covers the surfaces of the PN junctions which are connected in series; through the snakelike test structure, the square resistance of the snakelike active region metal silicide strip can be accurately measured, whether electric leakage exists in the substrate or not is detected, and whether continuity of the snakelike active region metal silicide strip is abnormal or not and whether bridging exists or not is detected. Furthermore, a cross comb-shaped test structure used for measuring the breakdown voltage of the metal silicide layer of the active region to judge whether the isolation between the active regions meets the requirement is formed in the region where the snake-shaped test structure is located, so that the comprehensiveness of the test structure can be improved, and the test area of a test pattern in a chip is saved; the area utilization rate is effectively improved.

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the steps: enabling a pad oxide layer and a silicide barrier layer to cover the surfaces of a first region and a second region in a conformal manner, and removing the silicide barrier layer of the first region; the sacrificial material layer fills and covers the surfaces of the first region and the second region; part of the sacrificial material layer is removed to be lower than the preset height of the gate structure, the exposed pad oxide layer is removed, and the first region side wall structure is thinned to expose the top wall of the gate structure; and removing the sacrificial material layer, thinning the side wall structure in the first region, removing the pad oxide layer, exposing the surface of the substrate in the first region, and forming a metal silicide. After the silicide barrier layer is removed and before the side wall structure is thinned, the sacrificial material layer is arranged to cover the pad oxide layer on the surface of the substrate, the line width effect is reduced, meanwhile, the surface material of the substrate and doping distribution are protected against loss, and the limitation of the SPT technology on the metal silicide technology is reduced; and meanwhile, the etching selection ratio of the pad oxide layer removal and the first thinning process is set, so that the protection of the sacrificial material layer on the pad oxide layer is ensured.

The invention provides a chip, a manufacturing method thereof and electronic equipment, the chip comprises a transistor, a metal silicide layer, an etching stop layer, an interlayer dielectric layer and a plurality of first contact holes, the metal silicide layer is at least arranged on a source electrode and a drain electrode of the transistor, and the first contact holes penetrate through the etching stop layer and the interlayer dielectric layer; the chip further comprises a barrier layer, the barrier layer is arranged between the metal silicide layer and the etching stop layer, and under the etching condition of the etching stop layer, the etching rate of the etching stop layer is larger than that of the barrier layer. Therefore, when the etching stop layer is etched, the barrier layer can be prevented from being etched, so that the barrier layer can play a role in stopping etching, the metal silicide layer is prevented from being etched, the metal silicide layer is protected, a source electrode and a drain electrode in the transistor cannot be influenced even if the metal silicide layer is thin, and the reliability of the transistor is improved. And the source electrode and the drain electrode are protected, so that the manufacturing yield of the chip is improved.

The invention discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The manufacturing method comprises the steps that a substrate is provided, a gate structure and side wall structures on the two sides are formed on the substrate, and a lightly doped region and a heavily doped region are formed in the portions, on the two sides of the gate structure, of the substrate; forming a first etching stop layer covering the substrate, the gate structure and the side wall structure on the substrate; forming an opening in the first etching stop layer by etching, wherein the opening exposes a part of the heavily doped region and at least a part of the gate structure; forming a compensation epitaxial layer in the opening, wherein the compensation epitaxial layer covers a part of the heavily doped region; at least metallizing the compensation epitaxial layer to form a metal silicide layer; forming an interlayer dielectric layer on the substrate and the metal silicide layer; etching the interlayer dielectric layer to the metal silicide layer to form a connecting hole; and forming a barrier layer and a conductive structure in the connecting hole. According to the semiconductor device and the manufacturing method thereof, the saturation current can be improved, and the performance and the yield of the semiconductor device can be improved.

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate, and forming a doped polycrystalline silicon electrode layer on the substrate; a first side wall, a second side wall and a protection side wall are formed on the side surface of the doped polycrystalline silicon electrode layer; an ion implantation process is carried out on the substrate, a first doped region and a second doped region are formed, and the first doped region and the second doped region are located on the two sides of the doped polycrystalline silicon electrode layer respectively; patterning the second side wall with partial height to expose the side surface of the first side wall with partial height; removing the protection side wall and the exposed first side wall with partial height, and exposing the side surface of the doped polycrystalline silicon electrode layer with partial height; a first metal silicide layer is formed in the doped polycrystalline silicon electrode layer, a second metal silicide layer is formed in the first doped region and the second doped region, and the thickness of the first metal silicide layer is larger than that of the second metal silicide layer.

Techniques described herein include forming respective (different) types of metal silicide layers for p-type source / drain regions and n-type source / drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source / drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source / drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source / drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source / drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source / drain region. This reduces the contact resistance for both p-type source / drain regions and n-type source / drain regions.

An integrated circuit device includes gate structures arranged on an upper surface of a substrate, a first impurity region arranged at the upper surface of the substrate, wherein the first impurity region is adjacent to a first gate structure of the gate structures, a first contact pad arranged on the upper surface of the substrate, wherein the first contact pad comprises a recess recessed in a vertical direction perpendicular to the upper surface of the substrate from an upper surface of the first contact pad toward the upper surface of the substrate, a metal silicide layer disposed in the recess, and a contact via connected to the metal silicide layer and extending in the vertical direction. A lower end of the contact via is disposed in the recess and connected to the metal silicide layer. The contact via is spaced apart from the substrate in the vertical direction.

The invention provides a deep trench capacitor and a preparation method thereof. The preparation method comprises the following steps: forming a deep trench in a substrate; forming a first dielectric layer on the inner wall of the deep trench; forming a second dielectric layer on the surface of a part of the first dielectric layer on the deep trench to reduce the opening of the deep trench, the second dielectric layer further extending to the surface of the first dielectric layer above the substrate; the deep trench is filled with polycrystalline silicon, the polycrystalline silicon seals an opening of the deep trench, the polycrystalline silicon forms an air gap in the lower part of the deep trench, and the polycrystalline silicon further extends to the surface of a second dielectric layer above the substrate; forming grooves in the second dielectric layer, the first dielectric layer and the polycrystalline silicon on the surface of the substrate; forming a side wall on the side wall of the groove, wherein the side wall covers part of the surface of the substrate in the groove; a first metal silicide layer is formed on the surface of the polycrystalline silicon, a second metal silicide layer is formed on the surface of the substrate in the groove, and the first metal silicide layer and the second metal silicide layer form an upper pole plate and a lower pole plate of the capacitor respectively.

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate provided with a plurality trenches arranged at intervals; a bit line at least located on a sidewall of the trench, wherein both the bit line and the trench extend along a first direction; a bit line isolation layer filled in the trench; a plurality of first semiconductor pillars arranged at intervals on a surface of the substrate; a plurality of word lines arranged at intervals, wherein the word lines are separated from the substrate and cover the first semiconductor pillars by a certain height, the word line extends along a second direction, and the second direction is different from the first direction; and a dielectric layer at least located between the first semiconductor pillar and the word line.

The present invention provides a method for manufacturing a pellicle and a pellicle for extreme ultraviolet exposure manufactured by the method, the method comprising a step of forming a metal silicide capping layer by using a silicon precursor and a metal precursor, wherein the pellicle can exhibit excellent performance in terms of transmittance and thermal emissivity.

The invention discloses a test structure, a manufacturing method and a test method of resistance of a metal silicide layer, the test structure comprises a substrate, an epitaxial layer and the metal silicide layer, the epitaxial layer is arranged on the substrate, and the metal silicide layer is arranged on the epitaxial layer. According to the invention, the interference of ion implantation is structurally eliminated, and the real resistance characteristic of the metal silicide layer is ensured to be obtained, so that the real states of key process parameters such as the thickness and square resistance of the metal silicide layer, the sizes of a polycrystalline silicon gate and a silicon active region and the like and the uniformity of the key process parameters in a wafer can be accurately reflected; a reliable basis is provided for process monitoring and optimization, and the performance consistency and the manufacturing yield of the device are improved.

The invention discloses a semiconductor device and electronic equipment, the semiconductor device comprises a semiconductor substrate, a first barrier layer, a metal silicide layer, a gate stack structure and a gate side wall, the semiconductor substrate comprises a channel region, a source region and a drain region, the source region and the drain region are located on two sides of the channel region, the first barrier layer is located on the source region and the drain region, and the metal silicide layer is located on the gate side wall. The metal silicide layer covers one side, opposite to the semiconductor substrate, of the first barrier layer on the source electrode region and the drain electrode region. Grooves are formed in the source electrode region and the drain electrode region respectively, and the grooves are filled with first semiconductor materials. The first barrier layer comprises a second semiconductor material doped with first doping ions, and the lattice structure of the material of the metal silicide layer is different from the lattice structure of the first semiconductor material. According to the arrangement, the first barrier layer is arranged between the metal silicide layer and the first semiconductor material, so that material agglomeration and precipitation caused by direct contact between the first semiconductor material and the metal silicide layer can be avoided, and the performance of the semiconductor device is improved.

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body; the semiconductor body comprises a first surface and a second surface which are oppositely arranged, the semiconductor body further comprises a well region and a first region, the first surface is provided with a gate trench, and the gate trench extends into the semiconductor body from the first surface; the grid electrode is positioned in the grid electrode groove; the grid electrode comprises a polycrystalline silicon grid electrode layer, a metal grid electrode layer and a metal silicide grid electrode layer; the metal silicide gate layer is used for reducing the resistance value of the gate, and the metal gate layer is used for preventing metal in the metal silicide gate layer from diffusing to the polycrystalline silicon gate layer; the second insulating layer is positioned on one side of the gate far away from the semiconductor body; the vertical projection of the second insulating layer on the first surface covers the vertical projection of the gate on the first surface; the source electrode is positioned on the first surface; and a drain electrode located on the second surface. According to the invention, the problem of gate voltage delay is effectively solved.

A method of manufacturing a semiconductor memory device includes forming a metal seed pattern having a plurality of openings on a substrate, forming a metal silicide pattern from the substrate and the metal seed pattern, growing a single crystal semiconductor pattern in a vertical direction at an interface between the substrate and the metal silicide pattern where the vertical direction is perpendicular to the substrate, and growing a sacrificial semiconductor pattern in the vertical direction at an interface between the metal silicide pattern and the single crystal semiconductor pattern.

The invention provides a semiconductor structure and a preparation method of the semiconductor structure, and relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; stacking the substrate along the first direction to form a stacking structure, wherein the stacking structure comprises an active layer; forming an opening in at least one side of the active layer along the second direction, the opening penetrating through the stack structure and exposing the substrate; filling a metal material in the opening, and enabling the metal material and the exposed substrate to form a first protection layer; removing the metal material; wherein the first direction intersects with the upper surface of the substrate and is perpendicular to the second direction. When the opening is filled with the metal material, the metal material can be adsorbed on the exposed upper surface of the substrate and reacts with the substrate to form the first protection layer in a self-alignment mode, the process steps of deposition and etching are omitted, the process cost is saved, the first protection layer is a metal silicide and can resist a wet etching solution, the substrate is prevented from being damaged by the wet etching solution, and the yield of the substrate is improved. And the effect of protecting the substrate is achieved.

The invention provides a manufacturing method of a semiconductor device, and the method comprises the steps: opening a mask layer on a medium-voltage gate oxide layer in a low-voltage region after forming a medium-voltage gate oxide layer which at least covers a medium-voltage region and a low-voltage region and forming a patterned mask layer which is used for limiting the medium-voltage gate oxide layer needing to be reserved on the medium-voltage region; and opening the mask layer on the beak region of the high-voltage gate oxide layer in the high-voltage region, so that the beak region of the high-voltage gate oxide layer in the high-voltage region is thinned or removed while the medium-voltage gate oxide layer in the low-voltage region is thinned or removed by using a wet etching process, thereby avoiding increasing extra photomask cost and process cost and improving the yield. The problem that source and drain ions injected into the source electrode region subsequently are blocked due to the fact that the thickness of the beak region is increased is solved, the transverse distance from a metal silicide and a contact plug on the source electrode region subsequently to a channel is shortened, the resistance of the source electrode region is reduced, and the performance of the device is improved.

A power semiconductor device is provided. The power semiconductor device mainly comprises a first conductive-type highly-doped substrate and a second conductive-type contact region formed thereon. The contact region has a dual-layer doping structure comprising a highly-doped region and a lightly-doped region. Accordingly, the active area of the power device has a five-layer structure of a second conductive-type highly-doped region, a second conductive-type lightly-doped region, an intrinsic semiconductor epitaxial layer, a first conductive-type lightly-doped layer, and a first conductive-type highly-doped substrate, for improving the breakdown voltage of the power device. In addition, metal silicide layers are introduced on the front and back sides of the device and form ohmic contacts with the metal layers thereof to shorten the reverse recovery time (trr) of the device. The metal electrode on the front of the device has a plurality of ring-shaped designs, including at least one second conductive-type metal ring and one first conductive-type metal ring.

A method for forming a semiconductor structure includes: providing a substrate having a gate structure thereon, and source and drain regions in the substrate on both sides of the gate structure; forming an interlayer dielectric layer covering the gate structure, the source region, and the drain region on the substrate; forming a first contact hole exposing the source region and the drain region in the interlayer dielectric layer; forming a metal silicide stack at the bottom of the first contact hole, the metal silicide stack including at least one stacking unit, and the stacking unit including a silicon layer and a metal layer sequentially formed at the bottom of the first contact hole; annealing the metal silicide stack to obtain a metal silicide layer. The method for forming a semiconductor structure provided by the embodiments of the present invention not only avoids the problems of stress reduction and channel resistance increase caused by ion implantation in the source region and the drain region, but also greatly reduces the thermal accumulation brought about during the formation of the metal silicide, and a metal silicide layer with uniform composition and good quality can be obtained, which is beneficial to reducing the contact resistance and RC delay and improving the performance of the semiconductor structure.

The application discloses an SRAM memory unit, an SRAM device and a preparation method thereof, and belongs to the field of semiconductors. In the application, the active regions of NMOS and PMOS are arranged in the optimal directions respectively, then the PMOS is arranged in a sinking mode, so that the active regions of the two kinds of transistors are staggered to improve the heat dissipation capacity. In order to manufacture the above structure, the application designs a corresponding preparation method. In the preparation process, the gate of the pull-up transistor is stepped, so that the gate of the pull-up transistor can be connected with the active region of the transfer gate transistor through a metal silicide technology, thereby greatly reducing the contact resistance, that is, reducing the heat generation of the storage node, thereby improving the performance of the whole device, and the read-write speed is faster than that of the prior art under the same condition.

A semiconductor memory structure includes a semiconductor substrate, a bit line disposed on the semiconductor substrate, a dielectric liner disposed on a sidewall of the bit line and a capacitor contact disposed on a side of the bit line. The dielectric liner includes a first nitride liner disposed on a sidewall of the bit line, an oxide liner disposed on a sidewall of the first nitride liner, and a second nitride liner disposed on a sidewall of the oxide liner. The capacitor contact includes a semiconductor plug disposed on the semiconductor substrate, a metal plug disposed on the semiconductor plug, a metal silicide liner including a sidewall portion and a bottom portion extending along the sidewall and the bottom of the metal plug respectively, and a nitride layer disposed on the metal silicide liner. The sidewall portion is disposed directly above the second nitride liner.

The application discloses a method for realizing an integrated ultrahigh-temperature environmental barrier composite coating. After a high-entropy alloy or boride layer and a molybdenum metal pre-coating layer are pre-coated on the surface of a substrate, a silicon-boron co-embedding deposition is carried out through a pre-oxidation process to form an ordered Mo-Si-B multilayer structure in the molybdenum metal layer. A composite coating formed by a metal silicide and silicon dioxide is cold sprayed on the Mo-Si-B multilayer structure to form a three-dimensional network structure composite self-healing layer through high-temperature sintering. An alloy oxide is cold sprayed or magnetron sputtered outside the composite self-healing layer to form a water vapor resistant layer. Through the integrated coating preparation process, the advantages of different components are complementary, and the effective protection of various refractory alloys in a wide temperature range (room temperature-1700 DEG C) can be realized.

The invention provides a method for forming a titanium / titanium nitride film. The method comprises the following steps of: depositing a titanium metal layer on a semiconductor substrate; and performing thermal annealing treatment on the semiconductor substrate deposited with the titanium metal layer in a nitrogen-containing atmosphere, so that the titanium metal layer reacts with the semiconductor substrate to form a metal silicide, and meanwhile, the titanium metal layer reacts with the nitrogen-containing atmosphere to generate a titanium nitride layer. The silicide contact layer and the titanium nitride barrier layer are formed at the same time through the in-situ reaction, and the technological process is simplified. The titanium nitride layer formed by the method is thin, stress distribution of the wafer is effectively improved, the problem of wafer warping caused by the fact that the titanium nitride layer is too thick in a traditional process is solved, meanwhile, it is guaranteed that a silicon interface reacts sufficiently, contact resistance is reduced, and consistency of electrical parameters of a device is improved.

A three-dimensional semiconductor device may include: a semiconductor pattern extending in a first direction parallel to a bottom surface of a substrate; a word line surrounding a portion of the semiconductor pattern and extending in a second direction parallel to the bottom surface of the substrate and orthogonal to the first direction; a bit line on the first side surface of the semiconductor pattern and extending in a third direction perpendicular to the bottom surface of the substrate; a capacitor on a second side surface of the semiconductor pattern opposite to the first side surface; and a metal silicide pattern between the capacitor and the second side surface of the semiconductor pattern. The capacitor may include a first electrode surrounding the metal silicide pattern, a second electrode on the first electrode, and a dielectric layer between the first electrode and the second electrode. The first electrode may include a metal oxide material.